target: rename cortex_m3 to cortex_m

Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.

cfg files have also been updated to the new target name.

Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1518617150094ac37b462ca614d27cd5de3a572b..2af9e60d311bf1ca8270aadb0acd28deb58203f8 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -986,7 +986,7 @@ that the @code{reset-init} event handler does.
 Likewise, the @command{arm9 vector_catch} command (or
 @cindex vector_catch
 its siblings @command{xscale vector_catch}
-and @command{cortex_m3 vector_catch}) can be a timesaver
+and @command{cortex_m vector_catch}) can be a timesaver
 during some debug sessions, but don't make everyone use that either.
 Keep those kinds of debugging aids in your user config file,
 along with messaging and tracing setup.
@@ -1948,7 +1948,7 @@ don't want to reset all targets at once.
 Such a handler might write to chip registers to force a reset,
 use a JRC to do that (preferable -- the target may be wedged!),
 or force a watchdog timer to trigger.
-(For Cortex-M3 targets, this is not necessary. The target
+(For Cortex-M targets, this is not necessary.  The target
 driver knows how to use trigger an NVIC reset when SRST is
 not available.)
 
@@ -3953,7 +3953,7 @@ look like with more than one:
     TargetName         Type       Endian TapName            State
 --  ------------------ ---------- ------ ------------------ ------------
  0* at91rm9200.cpu     arm920t    little at91rm9200.cpu     running
- 1  MyTarget           cortex_m3  little mychip.foo         tap-disabled
+ 1  MyTarget           cortex_m   little mychip.foo         tap-disabled
 @end verbatim
 
 One member of that list is the @dfn{current target}, which
@@ -4065,7 +4065,7 @@ At this writing, the supported CPU types and variants are:
 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
 (Support for this is preliminary and incomplete.)
 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
-@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
+@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
 compact Thumb2 instruction set.
 @item @code{dragonite} -- resembles arm966e
 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
@@ -4119,7 +4119,7 @@ to be much more board-specific.
 The key steps you use might look something like this
 
 @example
-target create MyTarget cortex_m3 -chain-position mychip.cpu
+target create MyTarget cortex_m -chain-position mychip.cpu
 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
 $MyTarget configure -event reset-init @{ myboard_reinit @}
@@ -7300,7 +7300,7 @@ cores @emph{except the ARM1176} use the same six bits.
 @cindex Debug Access Port
 @cindex DAP
 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
-included on Cortex-M3 and Cortex-A8 systems.
+included on Cortex-M and Cortex-A8 systems.
 They are available in addition to other core-specific commands that may be available.
 
 @deffn Command {dap apid} [num]
@@ -7333,10 +7333,10 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap.
 Defaulting to 0.
 @end deffn
 
-@subsection Cortex-M3 specific commands
-@cindex Cortex-M3
+@subsection Cortex-M specific commands
+@cindex Cortex-M
 
-@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
+@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
 Control masking (disabling) interrupts during target step/resume.
 
 The @option{auto} option handles interrupts during stepping a way they get
@@ -7353,7 +7353,7 @@ with interrupts enabled, i.e. the same way the @option{off} option does.
 Default is @option{auto}.
 @end deffn
 
-@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
 @cindex vector_catch
 Vector Catch hardware provides dedicated breakpoints
 for certain hardware events.
@@ -7380,7 +7380,7 @@ must also be explicitly enabled.
 This finishes by listing the current vector catch configuration.
 @end deffn
 
-@deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
+@deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
 Control reset handling. The default @option{srst} is to use srst if fitted,
 otherwise fallback to @option{vectreset}.
 @itemize @minus
@@ -7388,7 +7388,7 @@ otherwise fallback to @option{vectreset}.
 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
 @item @option{vectreset} use NVIC VECTRESET to reset system.
 @end itemize
-Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
+Using @option{vectreset} is a safe option for all current Cortex-M cores.
 This however has the disadvantage of only resetting the core, all peripherals
 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
 the peripherals.
@@ -7407,7 +7407,7 @@ The most powerful mechanism is semihosting, but there is also
 a lighter weight mechanism using only the DCC channel.
 
 Currently @command{target_request debugmsgs}
-is supported only for @option{arm7_9} and @option{cortex_m3} cores.
+is supported only for @option{arm7_9} and @option{cortex_m} cores.
 These messages are received as part of target polling, so
 you need to have @command{poll on} active to receive them.
 They are intrusive in that they will affect program execution
@@ -7913,10 +7913,10 @@ and an RTOS until he told GDB to disable the IRQs while stepping:
 
 @example
 define hook-step
-mon cortex_m3 maskisr on
+mon cortex_m maskisr on
 end
 define hookpost-step
-mon cortex_m3 maskisr off
+mon cortex_m maskisr off
 end
 @end example
 

diff --git a/src/rtos/ChibiOS.c b/src/rtos/ChibiOS.c
index cf590b7fefc27ee162866c2a115a9b2d01113740..e0424c69df4a4dbe0e8bbfb48da3cb2ace46cc81 100644 (file)
--- a/src/rtos/ChibiOS.c
+++ b/src/rtos/ChibiOS.c
@@ -94,7 +94,7 @@ struct ChibiOS_params {
 
 struct ChibiOS_params ChibiOS_params_list[] = {
        {
-       "cortex_m3",                                                    /* target_name */
+       "cortex_m",                                                     /* target_name */
        0,
        NULL,                                                                   /* stacking_info */
        },

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index acf3689fafe1ea79eacc07f71fc34d1cac6390f6..51bd35e4ef4b4a9ff61d84a74ab2fc0b0c5eb1f8 100644 (file)
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -50,7 +50,7 @@ struct FreeRTOS_params {
 
 const struct FreeRTOS_params FreeRTOS_params_list[] = {
        {
-       "cortex_m3",                    /* target_name */
+       "cortex_m",                     /* target_name */
        4,                                              /* thread_count_width; */
        4,                                              /* pointer_width; */
        16,                                             /* list_next_offset; */

diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
index 571814cb54439cbb40b8c0d6a1ce3dba4dd7ec9b..86a249982548ed90b3a9a609ae4478f781db37e2 100644 (file)
--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -73,7 +73,7 @@ struct ThreadX_params {
 
 const struct ThreadX_params ThreadX_params_list[] = {
        {
-       "cortex_m3",                            /* target_name */
+       "cortex_m",                             /* target_name */
        4,                                                      /* pointer_width; */
        8,                                                      /* thread_stack_offset; */
        40,                                                     /* thread_name_offset; */

diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c
index 6a0ed4ec0619bae71c0c5cbac1ce30ab88f68fbc..f2c7f712688eb84eb779221f1d546124fba459b5 100644 (file)
--- a/src/rtos/eCos.c
+++ b/src/rtos/eCos.c
@@ -64,7 +64,7 @@ struct eCos_params {
 
 const struct eCos_params eCos_params_list[] = {
        {
-       "cortex_m3",                    /* target_name */
+       "cortex_m",                     /* target_name */
        4,                                              /* pointer_width; */
        0x0c,                                   /* thread_stack_offset; */
        0x9c,                                   /* thread_name_offset; */

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 7094b0708f250bf91daf8f77ebb7a54472915334..6fba9259b8fd65acc4f11a177e3cd3e1e1ba4bdd 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2256,9 +2256,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
                .chain = armv7m_command_handlers,
        },
        {
-               .name = "cortex_m3",
+               .name = "cortex_m",
                .mode = COMMAND_EXEC,
-               .help = "Cortex-M3 command group",
+               .help = "Cortex-M command group",
                .usage = "",
                .chain = cortex_m3_exec_command_handlers,
        },
@@ -2266,7 +2266,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-       .name = "cortex_m3",
+       .name = "cortex_m",
+       .deprecated_name = "cortex_m3",
 
        .poll = cortex_m3_poll,
        .arch_state = armv7m_arch_state,

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 90f947dfd7e344024f8611735364a854fe85d60a..0c72cc71b1e76399c267ec6190053cc0849fc436 100644 (file)
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -167,3 +167,9 @@ proc init_targets {} {
 # Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets
 proc init_board {} {
 }
+
+# deprecated target name cmds
+proc cortex_m3 args {
+       echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'"
+       eval cortex_m $args
+}

diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index b90e3f0157c93fcbeb1d9b9e78452f7eba9e907d..075b462d0a78b17fab6e2a08b98fea6545912360 100644 (file)
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -58,7 +58,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -69,4 +69,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg
index b628103ced608c29bec1d5a6ae2fe06f87ed5793..32f163e320b355d6c6d02b18c37aef38972dacfb 100644 (file)
--- a/tcl/target/at91sam3nXX.cfg
+++ b/tcl/target/at91sam3nXX.cfg
@@ -18,12 +18,12 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 

diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index c34121847798cee495d481f3ea7a33ab11821eb0..24b3deb8e6308bd271490b77a56120aed47dab4d 100644 (file)
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -35,7 +35,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -46,4 +46,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index 60967e927f1ca380636a17e5536a629fb3669b01..e81fcc8948d7543aea222c1680c251fdfeabf1a6 100644 (file)
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -29,7 +29,7 @@ reset_config trst_only
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # MB9BF506 has 64kB of SRAM on its main system bus 
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
@@ -44,4 +44,4 @@ adapter_khz 500
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg
index 57aa849201dc5d0c236f9ed703e4079312fe1552..ec5502884e49fb19b31fd0d07d691763b64de928 100644 (file)
--- a/tcl/target/k40.cfg
+++ b/tcl/target/k40.cfg
@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg
index a85fa909bf1240167e2d2756619e8ce3ecbb81d6..7ac8bb59b1f385d064d95667409d05087f3b6d57 100644 (file)
--- a/tcl/target/k60.cfg
+++ b/tcl/target/k60.cfg
@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/lpc1788.cfg b/tcl/target/lpc1788.cfg
index 16b62c8a1b942fd1f879572fc4ec8c5ba11d8f0e..e986353e9f09a2ff61e2e08c5b3e275767390c2e 100644 (file)
--- a/tcl/target/lpc1788.cfg
+++ b/tcl/target/lpc1788.cfg
@@ -17,4 +17,4 @@ set CCLK 12000
 source [find target/lpc17xx.cfg];
 
 # if srst is not fitted, use SYSRESETREQ to perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
index a64783dab2e75edb6119b5552eb7a8dc5785be71..01a8cd3785e8e33c3fcd735d337759e5ff4e4052 100644 (file)
--- a/tcl/target/lpc17xx.cfg
+++ b/tcl/target/lpc17xx.cfg
@@ -57,7 +57,7 @@ jtag_ntrst_delay 200
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
@@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init {
 
 # if srst is not fitted use VECTRESET to
 # perform a soft reset - SYSRESETREQ is not supported
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 1ea7a49e115d559d4371806220c7bd0cc3f68825..94aec38fef3b66f6699397cd79f59accc08da396 100644 (file)
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -24,8 +24,8 @@ if { [info exists M3_JTAG_TAPID] } {
 jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
 
 set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index fbbea97d7ff802ab602ec88cacd973b056e99843..47f252963a16975995d3af251fb2ba1e772885e3 100644 (file)
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
                                -expected-id $_M0_JTAG_TAPID
 
-target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
 
 # on this CPU we should use VECTRESET to perform a soft reset and
 # manually reset the periphery
 # SRST or SYSRESETREQ disable the debug interface for the time of
 # the reset and will not fit our requirements for a consistent debug
 # session
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index f16d7488868e7e6a7305197d59f81f0b120abc36..2e9f5543bc15d459ca0c207d56fc57a4ae8297a0 100644 (file)
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index 6e8acda5a8e9edd50a67e9a3fc67270914b52ac6..5fdd654daadae2d0c1674c4ea855a9024898515a 100644 (file)
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 06f27c56807be3df913ec4638558ecd16d5dd46c..9804bde79172a6ce4e8c152dff5142fbb53a6c8e 100644 (file)
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -52,7 +52,7 @@ if { [info exists WORKAREASIZE] } {
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
@@ -157,11 +157,11 @@ $_TARGETNAME configure -event reset-start {
        if {$device_class == 0 || $device_class == 1 ||
                $device_class == 3 || $device_class == 5} {
                # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
-               cortex_m3 reset_config sysresetreq
+               cortex_m reset_config sysresetreq
        } else {
                # Tempest and Firestorm default to using NVIC VECTRESET
                # peripherals will need reseting manually, see proc reset_peripherals
-               cortex_m3 reset_config vectreset
+               cortex_m reset_config vectreset
 
                # reset peripherals, based on code in
                # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index a686e51ac4d73f9dd850fd349ecc9865bb9c019e..7d3f42f3b9762a5d29f82b6fbf6cfc47df72e0c3 100644 (file)
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -68,7 +68,7 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
        -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -78,4 +78,4 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index cfd6274e68acc2128b39cf5bed5b699f41e57810..43a944c103d10f646e757fdf8235eb82358fdd45 100644 (file)
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 31993ff80076ca03e0d68ccdd2be0b463c022944..d092b6c887cd565260eb774cd84fc7f595d207b4 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 16beaa469d19e48b094d2b9e37cee4196156c388..374c3371699f79f418fcfea66a27be9fbbcf75bd 100644 (file)
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -51,7 +51,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -60,4 +60,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg
index eea082e65d80fbb78c69703a0ff3b6fedc124218..8e6a10e1f3c7adfe060a91152db4c5ab92c1dfe2 100644 (file)
--- a/tcl/target/stm32l.cfg
+++ b/tcl/target/stm32l.cfg
@@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 
 proc stm32l_enable_HSI {} {
        # Enable HSI as clock source