Bin Meng [Fri, 12 Dec 2014 13:05:25 +0000 (21:05 +0800)]
x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:23 +0000 (21:05 +0800)]
x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:22 +0000 (21:05 +0800)]
x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:21 +0000 (21:05 +0800)]
x86: Refactor u-boot.rom build rules
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:20 +0000 (21:05 +0800)]
tools/ifdtool: Support writing multiple files (-w) simultaneously
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:19 +0000 (21:05 +0800)]
x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 14:06:15 +0000 (19:36 +0530)]
x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Bin Meng [Fri, 12 Dec 2014 14:06:13 +0000 (19:36 +0530)]
spi: sf: Support byte program for sst spi flash
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Bin Meng [Wed, 10 Dec 2014 08:35:50 +0000 (16:35 +0800)]
x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().
Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Xiubo Li [Thu, 11 Dec 2014 19:15:26 +0000 (11:15 -0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i
Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ.
It should be CONFIG_TIMER_CLK_FREQ.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
[York Sun: This is the difference between two patch versions] Reviewed-by: York Sun <yorksun@freescale.com>
Simon Glass [Wed, 10 Dec 2014 15:55:57 +0000 (08:55 -0700)]
dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
Allen Martin [Thu, 4 Dec 2014 13:36:30 +0000 (06:36 -0700)]
ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.
The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.
Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
Simon Glass [Thu, 4 Dec 2014 13:36:29 +0000 (06:36 -0700)]
tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Wed, 10 Dec 2014 15:55:54 +0000 (08:55 -0700)]
dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.
Simon Glass [Wed, 10 Dec 2014 15:55:48 +0000 (08:55 -0700)]
dm: i2c: Implement driver model support in the i2c command
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.
Simon Glass [Wed, 10 Dec 2014 15:55:47 +0000 (08:55 -0700)]
dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
lib: errno: introduce errno_str(): returns errno related message
The functions error's numbers are standarized - but the error
messages are not.
The errors are often handled with unclear error messages,
so why not use an errno standarized messages.
Advantages:
- This could decrease the binary size.
- Appended with a detailed information,
the error message will be clear.
This commit introduces new function:
- const char *errno_to_str(int errno)
The functions returns a pointer to the errno corresponding text message:
- if errno is null or positive number - a pointer to "Success" message
- if errno is negative - a pointer to errno related message
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Tom Rini <trini@ti.com>
Masahiro Yamada [Thu, 20 Nov 2014 12:20:32 +0000 (21:20 +0900)]
lib: string: move strlcpy() to a common place
Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
Alison Wang [Wed, 3 Dec 2014 08:18:09 +0000 (16:18 +0800)]
kconfig: ls102xa: Change the prompt messages
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:59 +0000 (17:40 +0800)]
ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:58 +0000 (17:40 +0800)]
ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:57 +0000 (17:40 +0800)]
ls102xa: changing a few targets' configurations.
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:56 +0000 (17:40 +0800)]
ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.
Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:55 +0000 (17:40 +0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Fri, 21 Nov 2014 03:17:15 +0000 (11:17 +0800)]
fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:14 +0000 (17:38 +0800)]
arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:02 +0000 (17:38 +0800)]
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:48 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021ATWR board
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:47 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:46 +0000 (15:00 +0800)]
ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:43 +0000 (15:00 +0800)]
arm: spl: Add I2C linker list in generic .lds
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:42 +0000 (15:00 +0800)]
spl: Use u-boot.img instead of u-boot.bin
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:41 +0000 (15:00 +0800)]
ls102xa: pblimage: Add pblimage tool support for LS102xA
For LS102xA, the size of spl/u-boot-spl.bin is variable.
This patch adds the support to deal with the variable
u-boot size in pblimage tool. It will be padded to 64
byte boundary.
Use pblimage_check_params() to add the specific operations
for ARM, such as PBI CRC and END command and the calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:26 +0000 (00:03 +0900)]
ARM: UniPhier: detect the number of flash banks at run-time
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to. So, run-time
detection of the number of flash banks would be more user-friendly.
Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit 70879a92561a (flash:
do not fail even if flash_size is zero).
Now it is possible to throw away such a tricky workaround. This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.
Peter Kümmel [Sat, 29 Nov 2014 08:26:04 +0000 (17:26 +0900)]
kconfig: Fix warning "‘jump’ may be used uninitialized"
Warning:
In file included from scripts/kconfig/zconf.tab.c:2537:0:
scripts/kconfig/menu.c: In function ‘get_symbol_str’:
scripts/kconfig/menu.c:590:18: warning: ‘jump’ may be used uninitialized in this function [-Wmaybe-uninitialized]
jump->offset = strlen(r->s);
Simplifies the test logic because (head && local) means (jump != 0)
and makes GCC happy when checking if the jump pointer was initialized.
Signed-off-by: Peter Kümmel <syntheticpp@gmx.net> Signed-off-by: Michal Marek <mmarek@suse.cz>
[ imported from Linux Kernel, commit 2d5603060967 ] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suriyan Ramasami [Thu, 27 Nov 2014 21:24:16 +0000 (13:24 -0800)]
fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined
The boot commands - bootz/bootm mandate a third argument which is the
address to the FDT blob. In cases where this argument is not specified,
boot fails with a message indicating a missing FDT.
This causes non-FDT kernels to fail to boot. This patch allows both FDT
and non-FDT kernels to boot by making the third parameter to the bootm/bootz
optional.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
[trini: Update again for covering appended DTB case after last revert in
this area] Signed-off-by: Tom Rini <trini@ti.com>
projects / u-boot / log