Chen-Yu Tsai [Tue, 9 Dec 2014 08:56:53 +0000 (16:56 +0800)]
sun6i: Add new board Merrii Hummingbird A31
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sun, 7 Dec 2014 19:55:10 +0000 (20:55 +0100)]
sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 2 Dec 2014 09:29:42 +0000 (10:29 +0100)]
sun6i: Update Colombus defconfig settings
The Colombus defconfig settings are missing a number of settings for recently
added features, because we did not know exactly how things were hooked up.
Maxime Ripard has run various tests to get us the necessary details, this
commit updates the defconfig with this info.
This commit also updates the dram clk and zq values with values verified
by Maxime to be the ones used by the original firmware for this board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 16 Nov 2014 10:33:56 +0000 (11:33 +0100)]
sun6i: Add new CSQ_CS908 board
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
Hans de Goede [Sat, 15 Nov 2014 18:46:39 +0000 (19:46 +0100)]
sun6i: Make dram clk and zq value Kconfig options
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Bin Meng [Tue, 6 Jan 2015 14:14:21 +0000 (22:14 +0800)]
x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:19 +0000 (22:14 +0800)]
x86: Move CONFIG_SYS_CAR_xxx to Kconfig
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:18 +0000 (22:14 +0800)]
x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:17 +0000 (22:14 +0800)]
x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:14 +0000 (22:14 +0800)]
x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:13 +0000 (22:14 +0800)]
x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:14 +0000 (16:18 -0700)]
x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Simon Glass [Thu, 1 Jan 2015 23:18:11 +0000 (16:18 -0700)]
x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Simon Glass [Thu, 1 Jan 2015 23:18:09 +0000 (16:18 -0700)]
x86: board_f: Adjust x86 boot order for performance
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Simon Glass [Thu, 1 Jan 2015 23:18:07 +0000 (16:18 -0700)]
x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Simon Glass [Thu, 1 Jan 2015 23:18:06 +0000 (16:18 -0700)]
x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Simon Glass [Thu, 1 Jan 2015 23:18:02 +0000 (16:18 -0700)]
x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at present.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 31 Dec 2014 08:05:14 +0000 (16:05 +0800)]
x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:13 +0000 (16:05 +0800)]
x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:12 +0000 (16:05 +0800)]
serial: ns16550: Support ns16550 compatible pci uart devices
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:11 +0000 (16:05 +0800)]
fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
Bin Meng [Tue, 30 Dec 2014 08:02:05 +0000 (16:02 +0800)]
x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 30 Dec 2014 14:53:21 +0000 (22:53 +0800)]
pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 30 Dec 2014 14:53:20 +0000 (22:53 +0800)]
x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 24 Dec 2014 05:06:39 +0000 (13:06 +0800)]
x86: Clean up the board dts files
This commits cleans up the board dts files.
- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
skeleton.dtsi
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Pali Rohár [Thu, 8 Jan 2015 09:11:40 +0000 (10:11 +0100)]
Nokia RX-51: Do not call secure PPA routine on non secure devices
Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is
crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function
for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only
on real secure device and not in qemu.
This board patch just disable calling secure PPA routine on non secure devices.
Qemu implements GP device and with this patch u-boot is working in qemu again.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz>
Masahiro Yamada [Fri, 19 Dec 2014 05:27:13 +0000 (14:27 +0900)]
ARM: remove redudant information from Kconfig files
- "string" type for SYS_* is defined in arch/Kconfig
- SYS_CPU "armv7" has been replaced with "select CPU_V7"
- SYS_SOC "tegra124" is already defined in tegra124/Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Bo Shen <voice.shen@atmel.com>
Kevin Hilman [Mon, 15 Dec 2014 20:07:52 +0000 (12:07 -0800)]
common/board_f.c: fix compile error when tracing disabled
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to `trace_early_init'
To fix, wrap trace init calls with #ifdef CONFIG_TRACE.
While at it, remove the static inline version of the init call from
trace.h as suggested by Simon Glass, since it doesnt work.
Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
Łukasz Majewski [Fri, 21 Nov 2014 08:22:43 +0000 (09:22 +0100)]
fix: tools: kwbimage.c: Initialize headersz to suppress warning
When building with my toolchain (4.8.2):
CROSS_COMPILE=/home/lukma/work/ptxdist/toolchains/arm/OSELAS.Toolchain-2013.12.0/arm-v7a-linux-gnueabi/gcc-4.8.2-glibc-2.18-binutils-2.24-kernel-3.12-sanitized/bin/arm-v7a-linux-gnueabi-
I see following WARNING:
tools/kwbimage.c: In function "kwbimage_set_header":
tools/kwbimage.c:803:8: warning: "headersz" may be used uninitialized in this function [-Wmaybe-uninitialized]
memcpy(ptr, image, headersz);
^
This fix aims to suppress it.
Alexey Brodkin [Mon, 29 Dec 2014 12:42:57 +0000 (15:42 +0300)]
arc: introduce "mdbtrick" target
MetaWare debugger (MDB) is still used as a primary tool for interaction
with target via JTAG. Moreover some very advanced features are not yet
implemented in GDB for ARC (and not sure if they will be implemnted
sometime soon given complexity and rare need for those features for
common user).
So if we're talking about development process when U-Boot is loaded in
target memory not by low-level boot-loader but manually through JTAG
chances are high developer uses MDB for it.
But MDB doesn't support PIE (position-independent executable) - it will
refuse to even start - that means no chance to load elf contents on
target.
Then the only way to load U-Boot in MDB is to fake it by:
1. Reset PIE flag in ELF header
This is simpe - on attempt to open elf MDB checks header and if it
doesn't match its expectation refuces to use provided elf.
2. Strip all debug information from elf
If (1) is done then MDB will open elf but on parsing of elf's debug
info it will refuse to process due to debug info it cannot understand
(symbols with PIE relocation).
Even though it could be done manually (I got it documented quite a while
ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated
way is very convenient. User may build U-Boot that will be loaded on
target via MDB saying "make mdbtrick".
Then if we now apply the manipulation MDB will happily start and will
load all required sections into the target.
Indeed there will be no source-level debug info available. But still MDB
will do its work on showing disassembly, global symbols, registers,
accessing low-level debug facilities etc.
As a summary - this is a pretty dirty hack but it simplifies life a lot
for us ARc developers.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de>
Masahiro Yamada [Fri, 26 Dec 2014 13:20:58 +0000 (22:20 +0900)]
mtd: nand: do not scan BBT after scrub
Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.
It violates the intention of NAND_SKIP_BBTSCAN.
Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.
Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub. We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
Its git-log claimed that it reinstated the change as by commit fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".
It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).
projects / u-boot / log