Sergei Poselenov [Thu, 14 Aug 2008 12:08:28 +0000 (14:08 +0200)]
ARM: fix warning: target CPU does not support interworking
This patch fixes warnings like this:
start.S:0: warning: target CPU does not support interworking
which come from some ARM cross compilers and are caused by hard-coded
(with "--with-cpu=arm9" configuration option) ARM targets (which
support ARM Thumb instructions), while the ARM target selected from
the command line (with "-march=armv4") doesn't support Thumb
instructions.
This warning is issued by the compiler regardless of the real use of
the Thumb instructions in code.
To fix this problem, we use options according to compiler version
being used.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
Stefan Roese [Mon, 8 Sep 2008 08:01:48 +0000 (10:01 +0200)]
ppc4xx: Remove CONFIG_CS8952_PHY define
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.
Stefan Roese [Fri, 5 Sep 2008 12:11:40 +0000 (14:11 +0200)]
ppc4xx: Fix compilation warning for PIP405
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.
Kumar Gala [Fri, 5 Sep 2008 19:40:29 +0000 (14:40 -0500)]
Fix compiler warning in mpc8xxx ddr code
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here
Add a warning in DDR1 case if cas_latency isn't a value we know about.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Kumar Gala [Sat, 30 Aug 2008 00:08:29 +0000 (19:08 -0500)]
Prevent crash if random/invalid ramdisks are passed to bootm
Adds returning an error from the ramdisk detection code if
its not a real ramdisk (invalid). There is no reason we can't
just return back to the console if we detect an invalid
ramdisk or CRC error.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Prevent crash if random DTB address is passed to bootm
This patch adds bootm_start() return value check. If
error status is returned, we do not proceed further to
prevent board reset or crash as we still can recover
at this point.
Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the
corresponding kind of reset to OHCI's hc_reset() if the newly
introduced CONFIG_PCI_EHCI_DEVNO option is set (e.g. for Socrates
board).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Markus Klotzbuecher <mk@denx.de>
Stefan Roese [Fri, 5 Sep 2008 08:47:46 +0000 (10:47 +0200)]
devices: Use list_add_tail() instead of list_add() to register a device
This patch fixes a problem spotted on Glacier/Canyonlands (and most
likely lots of other board ports), that no serial output was seen
after console initialization in console_init_r(). This is because the
last added console device was used instead of the first added.
This patch fixes this problem by using list_add_tail() instead of
list_add() to register a device. This way the first added console
is used again.
Adam Graham [Wed, 3 Sep 2008 19:26:28 +0000 (12:26 -0700)]
ppc4xx: IBM Memory Controller DDR autocalibration routines
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).
Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B". DDR autocalibration Method_A scans the full range
of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B. Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.
The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1) SDRAM0_RQDC.[RQFD]
2) SDRAM0_RFDC.[RFFD]
This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:
and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].
Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
This patch provides an unificated way of handling xilinx v5 ppc440 boards.
It unificates 3 different things:
1) Source code
A new board called ppc440-generic has been created. This board includes
a generic tlb initialization (Maps the whole memory into virtual) and
defines board_pre_init, checkboard, initdram and get_sys_info weakly,
so, they can be replaced by specific functions.
If a new board needs to redefine any of the previous functions
(specific initialization) it can create a new directory with the
specific initializations needed. (see the example ml507 board).
2) Configuration file
Common configurations are located under configs/xilinx-ppc440.h, this
header file interpretes the xparameters file generated by EDK and
configurates u-boot in correspondence. Example: if there is a Temac,
allows CMD_CONFIG_NET
Specific configuration are located under specific configuration file.
(see the example ml507 board)
3) Makefile
Some work has been done in order to not duplicate work in the Main
Makefile. Please see the attached code.
In order to support new boards they can be implemented in the next way:
a) Simple Generic Board (90% of the time)
Using EDK generates a new xparameters.h file, replace
ppc440-generic/xparameters.h and run make xilinx-ppc440-generic_config
&& make
b) Simple Boards with special u-boot parameters (9 % of the time)
Create a new file under configs for it (use ml507.h as example) and
change your paramaters. Create a new Makefile paragraph and compile
c) Complex boards (1% of the time)
Create a new folder for the board, like the ml507
Finally, it adds support for the Avnet FX30T Evaluation board, following
the new generic structure:
Cheap board by Avnet for evaluating the Virtex5 FX technology.
This patch adds support for:
- UartLite
- 16MB Flash
- 64MB RAM
Prior using U-boot in this board, read carefully the ERRATA by Avnet
to solve some memory initialization issues.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
Nick Spence [Thu, 28 Aug 2008 21:09:25 +0000 (14:09 -0700)]
mpc83xx: clean up cache operations and unlock_ram_in_cache() functions
Cleans up some latent issues with the data cache control so that
dcache_enable() and dcache_disable() will work reliably (after
unlock_ram_in_cache() has been called)
Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Nick Spence [Thu, 28 Aug 2008 21:09:19 +0000 (14:09 -0700)]
mpc83xx: Store and display Arbiter Event Register values
Record the Arbiter Event Register values and optionally display them.
The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.
Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
#define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
and type register values
#define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter
event register values
Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
#define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
only events, so that it can still capture
other real problems.
Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Nick Spence [Sat, 23 Aug 2008 06:52:50 +0000 (23:52 -0700)]
MPC83XX: Fix GPIO configuration - set gpio level before direction
Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.
Set gpio level register before direction register to inhibit
glitches on high level output pins.
Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.
Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.
Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Stefan Roese [Mon, 1 Sep 2008 06:35:37 +0000 (08:35 +0200)]
ppc4xx: Remove reference to common/lists.o from some esd linker scripts
This patch removes some direct references to common/lists.o from some
esd linker scripts. This is necessary because the lists source was moved
and is not in the "common" directory anymore.
ppc4xx: Remove obsolete or unused functions from some esd boards
This patch removes initdram() and testdram() from most esd 405 platforms.
Some boards also have an empty dummy implementation of
misc_init_f(). This is also removed.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
If a board has a variable number of flash banks, there are empty entries
in flash_info[] and CFG_DIRECT_FLASH_TFTP is set, tftp boot fails with
"Outside available Flash". This patch skips flash banks with unknown
flash ids.
Signed-off-by: Jochen Friedrich <jochen@scram.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
net: smc911x: Add pkt_data_pull and pkt_data_push function
The RSK7203 board has the SMSC9118 wired up 'incorrectly'.
Byte-swapping is necessary, and so poor performance is inevitable.
This problem cannot evade by the swap function of CHIP, this can
evade by software Byte-swapping.
And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
functions necessary to solve this problem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andy Fleming [Sun, 31 Aug 2008 21:33:30 +0000 (16:33 -0500)]
Add pixis_set_sgmii command
The 8544DS and 8572DS platforms support an optional SGMII riser card to
expose ethernet over an SGMII interface. Once the card is in, it is also
necessary to configure the board such that it uses the card, rather than
the on-board ethernet ports. This can either be done by flipping dip switches
on the motherboard, or by modifying registers in the pixis. Either way
requires a reboot.
This adds a command to allow users to choose which ports are routed through
the SGMII card, and which through the onboard ports. It also allows users
to revert to the current switch settings.
This code does not work on the 8572, as the PIXIS is different.
Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andy Fleming [Sun, 31 Aug 2008 21:33:29 +0000 (16:33 -0500)]
Add SGMII support for the 8544 DS
The 8544 DS has an optional SGMII Riser card, which uses different PHY
addresses. Check if we are in SGMII mode, and invoke the SGMII Riser
setup code if so.
Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andy Fleming [Sun, 31 Aug 2008 21:33:28 +0000 (16:33 -0500)]
Add support for Freescale SGMII Riser Card
The 8544DS and 8572DS systems have an optional SGMII riser card which
exposes new ethernet ports which are connected to the eTSECs via an
SGMII interface. The SGMII PHYs for this board are offset from the standard
PHY addresses, so this code modifies the passed in tsec_info structure to
use the SGMII PHYs on the card, instead.
Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andy Fleming [Sun, 31 Aug 2008 21:33:26 +0000 (16:33 -0500)]
Pass in tsec_info struct through tsec_initialize
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
projects / u-boot / log