]> git.sur5r.net Git - u-boot/log
u-boot
15 years agoOMAP3 MMC: Fix warning dereferencing type-punned pointer
Dirk Behme [Mon, 28 Sep 2009 12:17:50 +0000 (08:17 -0400)]
OMAP3 MMC: Fix warning dereferencing type-punned pointer

Fix warning
Dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
CC: Steve Sakoman <sakoman@gmail.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
15 years agoMerge branch 'arm/master' into arm/next
Tom Rix [Sun, 4 Oct 2009 10:40:07 +0000 (05:40 -0500)]
Merge branch 'arm/master' into arm/next

Conflicts:
board/AtmarkTechno/suzaku/Makefile
board/amcc/acadia/acadia.c
board/amcc/katmai/katmai.c
board/amcc/luan/luan.c
board/amcc/ocotea/ocotea.c
board/cm-bf537u/Makefile
board/cray/L1/L1.c
board/csb272/csb272.c
board/csb472/csb472.c
board/eric/eric.c
board/eric/init.S
board/eukrea/cpuat91/Makefile
board/exbitgen/exbitgen.c
board/exbitgen/init.S
board/freescale/mpc8536ds/config.mk
board/g2000/g2000.c
board/jse/sdram.c
board/mpl/mip405/mip405.c
board/mpl/pip405/pip405.c
board/netstal/hcu5/hcu5.c
board/netstal/mcu25/mcu25.c
board/sc3/sc3.c
board/w7o/init.S
board/w7o/w7o.c
common/cmd_reginfo.c
cpu/ppc4xx/40x_spd_sdram.c
cpu/ppc4xx/44x_spd_ddr.c
doc/README.sbc8548
drivers/misc/fsl_law.c
fs/ubifs/ubifs.c
include/asm-ppc/immap_85xx.h

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
15 years agoSupport for the OpenRD base board
Simon Kagstrom [Mon, 21 Sep 2009 22:31:01 +0000 (04:01 +0530)]
Support for the OpenRD base board

The implementation is borrowed from the sheevaplug board and the Marvell
1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
15 years agoKirkwood: mv88f6281gtw_ge: Add kwbimage build support
Prafulla Wadaskar [Mon, 21 Sep 2009 14:45:17 +0000 (20:15 +0530)]
Kirkwood: mv88f6281gtw_ge: Add kwbimage build support

This patch adds kwbimage configuration file
(used by mkimage utility)
to support u-boot.kwb target on mv88f6281gtw_ge board.

To create Kirkwood boot image to be flashed on SPI Flash,
additional parameter u-boot.kwb need to be passed during make.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
15 years agoKirkwood: rd6281a: Add kwbimage build support
Prafulla Wadaskar [Mon, 21 Sep 2009 12:53:11 +0000 (18:23 +0530)]
Kirkwood: rd6281a: Add kwbimage build support

This patch adds kwbimage configuration file
(used by mkimage utility)
to support u-boot.kwb target on rd6281a platform.

To create Kirkwood boot image to be flashed on NAND,
additional parameter u-boot.kwb need to be passed during make.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
15 years agoAdd support for Eukrea CPU9260/CPU9G20 SBC
Tom Rix [Sun, 27 Sep 2009 16:10:09 +0000 (11:10 -0500)]
Add support for Eukrea CPU9260/CPU9G20 SBC

these boards are built around Atmel's AT91SAM9260/9G20 and have
up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND
and include a 10/100 Ethernet PHY in RMII mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
15 years agoAdd support for Eukrea CPUAT91 SBC
Tom Rix [Sun, 27 Sep 2009 12:47:24 +0000 (07:47 -0500)]
Add support for Eukrea CPUAT91 SBC

CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR
flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII
mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
15 years agompc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]
Wolfgang Denk [Fri, 25 Sep 2009 12:16:00 +0000 (14:16 +0200)]
mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agomucmc52, uc101: delete ata@3a00 node, if no CF card is detected
Heiko Schocher [Wed, 23 Sep 2009 05:56:08 +0000 (07:56 +0200)]
mucmc52, uc101: delete ata@3a00 node, if no CF card is detected

U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.

Signed-off-by: Heiko Schocher <hs@denx.de>
15 years agompc5200, mucmc52, uc101: config cleanup
Heiko Schocher [Wed, 23 Sep 2009 05:56:04 +0000 (07:56 +0200)]
mpc5200, mucmc52, uc101: config cleanup

- As these boards are similiar, collect common config options
  in manroland/common.h and manroland/mpc52xx-common.h
  for mpc5200 specific common options for this manufacturer.
- add OF support
- update default environment

Signed-off-by: Heiko Schocher <hs@denx.de>
Minor edit of commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoFix "ppc/85xx: Clean up use of LAWAR defines" breakage
Wolfgang Denk [Thu, 24 Sep 2009 22:57:49 +0000 (00:57 +0200)]
Fix "ppc/85xx: Clean up use of LAWAR defines" breakage

Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoAdd Elpida Memory Configuration to mpc5121ads Boards
Martha M Stan [Mon, 21 Sep 2009 18:08:00 +0000 (14:08 -0400)]
Add Elpida Memory Configuration to mpc5121ads Boards

Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor coding style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agompc512x: Streamlined fixed_sdram() init sequence.
Martha M Stan [Mon, 21 Sep 2009 18:07:14 +0000 (14:07 -0400)]
mpc512x: Streamlined fixed_sdram() init sequence.

Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor cleanup:

Re-ordered default_mddrc_config[] to have matching indices.

This allows to use the same index "N" for source and target fields;
before, we had code like this

out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);

which always looked like a copy & paste error because 2 != 3.

Also, use NULL when meaning a null pointer.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoppc/p4080: Determine various chip frequencies on CoreNet platforms
Kumar Gala [Thu, 19 Mar 2009 07:46:19 +0000 (02:46 -0500)]
ppc/p4080: Determine various chip frequencies on CoreNet platforms

The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/p4080: Handle timebase enabling and frequency reporting
Kumar Gala [Thu, 17 Sep 2009 06:52:37 +0000 (01:52 -0500)]
ppc/p4080: Handle timebase enabling and frequency reporting

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/p4080: Add various p4080 related defines (and p4040)
Kumar Gala [Thu, 19 Mar 2009 07:39:17 +0000 (02:39 -0500)]
ppc/p4080: Add various p4080 related defines (and p4040)

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/p4080: CoreNet platfrom style secondary core release
Kumar Gala [Thu, 17 Sep 2009 06:44:39 +0000 (01:44 -0500)]
ppc/p4080: CoreNet platfrom style secondary core release

The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/p4080: CoreNet platfrom style CCSRBAR setting
Kumar Gala [Thu, 17 Sep 2009 06:44:00 +0000 (01:44 -0500)]
ppc/p4080: CoreNet platfrom style CCSRBAR setting

On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoppc/p4080: Add support for CoreNet style platform LAWs
Kumar Gala [Thu, 19 Mar 2009 07:32:23 +0000 (02:32 -0500)]
ppc/p4080: Add support for CoreNet style platform LAWs

On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address.  Also, the target IDs
on CoreNet platforms have been completely re-assigned.

Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.

Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/p4080: Add p4080 platform immap definitions
Kumar Gala [Wed, 16 Sep 2009 14:43:12 +0000 (09:43 -0500)]
ppc/p4080: Add p4080 platform immap definitions

The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform.  We reuse the 85xx immap and just add new definitions for
local access and global utils.  The global utils is now broken into
global utils, clocking and run control/power management.

The offsets from CCSR for a number of blocks have also changed.  We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform.  We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Fix enabling of L2 cache
Kumar Gala [Tue, 22 Sep 2009 20:45:44 +0000 (15:45 -0500)]
ppc/85xx: Fix enabling of L2 cache

We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years ago85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ
Vivek Mahajan [Tue, 22 Sep 2009 07:18:27 +0000 (12:48 +0530)]
85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ

The code assumed names where just numbers and always prefixed 'mpc'.
However newer QorIQ don't follow the mpc naming scheme.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: add cpu init config file for boot from NAND
Mingkai Hu [Tue, 22 Sep 2009 06:53:21 +0000 (14:53 +0800)]
ppc/85xx: add cpu init config file for boot from NAND

When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoimmap_85xx: add porpllsr's plat ratio definition
Mingkai Hu [Tue, 22 Sep 2009 06:53:34 +0000 (14:53 +0800)]
immap_85xx: add porpllsr's plat ratio definition

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: add ld script file for boot from NAND
Mingkai Hu [Tue, 22 Sep 2009 06:53:10 +0000 (14:53 +0800)]
ppc/85xx: add ld script file for boot from NAND

The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agompc8610hpcd: Use common 86xx fdt fixup code
Peter Tyser [Tue, 22 Sep 2009 04:09:28 +0000 (23:09 -0500)]
mpc8610hpcd: Use common 86xx fdt fixup code

Using the common 86xx fdt fixups removes some board-specific code and
should make the mpc8610hpcd easier to maintain in the long run.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc85x0: tidy up Makefile to use new configuration script.
Paul Gortmaker [Mon, 21 Sep 2009 21:19:17 +0000 (17:19 -0400)]
sbc85x0: tidy up Makefile to use new configuration script.

Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the boards config header.  This takes advantage of
that for the sbc8540/sbc8560 boards.

There were a couple of cheezy comments pointing at incorrect
files, or files that don't exist, so I've cleaned those up too.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: allow enabling PCI via a make config option
Paul Gortmaker [Mon, 21 Sep 2009 00:36:06 +0000 (20:36 -0400)]
sbc8548: allow enabling PCI via a make config option

Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,

This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: update PCI/PCI-e support code
Paul Gortmaker [Mon, 21 Sep 2009 00:36:05 +0000 (20:36 -0400)]
sbc8548: update PCI/PCI-e support code

The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile.  This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.

It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.

Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agofsl_pci: create a SET_STD_PCI_INFO() helper wrapper
Paul Gortmaker [Mon, 21 Sep 2009 00:36:01 +0000 (20:36 -0400)]
fsl_pci: create a SET_STD_PCI_INFO() helper wrapper

Recycle the recently added PCI-e wrapper used to reduce board
duplication of code by creating a similar version for plain PCI.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: correct local bus SDRAM size from 64M to 128M
Paul Gortmaker [Mon, 21 Sep 2009 00:36:04 +0000 (20:36 -0400)]
sbc8548: correct local bus SDRAM size from 64M to 128M

The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4.  It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had.  In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: use I/O accessors
Paul Gortmaker [Mon, 21 Sep 2009 00:36:03 +0000 (20:36 -0400)]
sbc8548: use I/O accessors

Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: remove eTSEC3/4 voltage hack
Paul Gortmaker [Mon, 21 Sep 2009 00:36:02 +0000 (20:36 -0400)]
sbc8548: remove eTSEC3/4 voltage hack

With only eTSEC1 and 2 being brought out to RJ-45 connectors, we
aren't interested in the eTSEC3/4 voltage hack on this board

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: enable access to second bank of flash
Paul Gortmaker [Fri, 18 Sep 2009 23:08:41 +0000 (19:08 -0400)]
sbc8548: enable access to second bank of flash

The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot.  There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.

The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: cosmetic line re-wrap
Paul Gortmaker [Wed, 23 Sep 2009 21:30:57 +0000 (17:30 -0400)]
sbc8548: cosmetic line re-wrap

Fix the extra long lines to be consistent with u-boot coding style.
No functional change here.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
15 years agosbc8548: get_clock_freq is not valid for this board
Paul Gortmaker [Fri, 18 Sep 2009 23:08:40 +0000 (19:08 -0400)]
sbc8548: get_clock_freq is not valid for this board

The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms.  It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: delete unused MPC8548CDS info carried over from port
Paul Gortmaker [Fri, 18 Sep 2009 23:08:39 +0000 (19:08 -0400)]
sbc8548: delete unused MPC8548CDS info carried over from port

There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.

Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot.  That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.

Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: enable use of PCI network cards
Paul Gortmaker [Fri, 18 Sep 2009 23:08:44 +0000 (19:08 -0400)]
sbc8548: enable use of PCI network cards

Create a board_eth_init to allow a place to hook in
the PCI ethernet init after all the eTSEC are up
and configured.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: 32bit DDR changes for P1020/P1011
Poonam Aggrwal [Sat, 19 Sep 2009 12:20:17 +0000 (17:50 +0530)]
ppc/85xx: 32bit DDR changes for P1020/P1011

The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.

As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agosbc8548: replace README with completely new document
Paul Gortmaker [Fri, 18 Sep 2009 23:08:46 +0000 (19:08 -0400)]
sbc8548: replace README with completely new document

The previous README.sbc8548 was pretty much content-free. Replace
it with something that actually gives the end user some relevant
hardware details, and also lists the u-boot configuration choices.

Also in the cosmetic department, fix the bogus line in the Makefile
that was carried over from the SBC8560 Makefile, and the typo in
the sbc8548.c copyright.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Clean up use of LAWAR defines
Kumar Gala [Sat, 19 Sep 2009 16:20:54 +0000 (11:20 -0500)]
ppc/85xx: Clean up use of LAWAR defines

On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h.  Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Clean up mpc8572DS PCI setup code
Kumar Gala [Thu, 3 Sep 2009 15:20:09 +0000 (10:20 -0500)]
ppc/85xx: Clean up mpc8572DS PCI setup code

Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Clean up p2020ds PCI setup code
Kumar Gala [Thu, 3 Sep 2009 14:42:01 +0000 (09:42 -0500)]
ppc/85xx: Clean up p2020ds PCI setup code

Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Clean up p1_p2_rdb PCI setup
Kumar Gala [Thu, 3 Sep 2009 15:09:04 +0000 (10:09 -0500)]
ppc/85xx: Clean up p1_p2_rdb PCI setup

General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Simplify the top makefile for P1_P2_RDB boards
Kumar Gala [Thu, 10 Sep 2009 21:31:53 +0000 (16:31 -0500)]
ppc/85xx: Simplify the top makefile for P1_P2_RDB boards

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Simplify the top makefile for 36-bit config for P2020DS
Kumar Gala [Thu, 10 Sep 2009 21:26:37 +0000 (16:26 -0500)]
ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS
Kumar Gala [Thu, 10 Sep 2009 21:23:45 +0000 (16:23 -0500)]
ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds
Mingkai Hu [Fri, 18 Sep 2009 03:45:09 +0000 (11:45 +0800)]
ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Fix LCRR_CLKDIV defines
Kumar Gala [Wed, 16 Sep 2009 03:21:58 +0000 (22:21 -0500)]
ppc/85xx: Fix LCRR_CLKDIV defines

For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.

All 83xx and early (e500v1) PQ3 devices support:
 clk/2: CLKDIV = 2
 clk/4: CLKDIV = 4
 clk/8: CLKDIV = 8

Newer PQ3 (e500v2) and MPC86xx support:
 clk/4: CLKDIV = 2
 clk/8: CLKDIV = 4
 clk/16: CLKDIV = 8

Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the defines reflect their logical view (not the value of the field).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
15 years agoMAKEALL: Use POSIX math
Peter Tyser [Mon, 21 Sep 2009 17:04:33 +0000 (12:04 -0500)]
MAKEALL: Use POSIX math

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years agoMAKEALL: Add summary information
Peter Tyser [Mon, 21 Sep 2009 17:04:32 +0000 (12:04 -0500)]
MAKEALL: Add summary information

This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.

This information is useful when doing compile testing to quickly
determine which boards are broken.

As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years agogalaxy5200: enable version environment variable
Eric Millbrandt [Mon, 21 Sep 2009 16:05:55 +0000 (11:05 -0500)]
galaxy5200: enable version environment variable

Add version environment variable configuration to the galaxy5200
board header file.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
Edited commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agodigsy_mtc: Add TCR register value for RTC (DS1339)
Werner Pfister [Mon, 21 Sep 2009 12:49:56 +0000 (14:49 +0200)]
digsy_mtc: Add TCR register value for RTC (DS1339)

Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
15 years agortc/ds1337.c: Allow to set TCR register
Werner Pfister [Mon, 21 Sep 2009 12:49:55 +0000 (14:49 +0200)]
rtc/ds1337.c: Allow to set TCR register

This is needed to correctly start the charging of an attached capacitor
or battery.

Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
15 years agoubifs: Add support for looking up directory and relative symlinks
Simon Kagstrom [Tue, 15 Sep 2009 07:53:29 +0000 (09:53 +0200)]
ubifs: Add support for looking up directory and relative symlinks

This patch adds support for resolving symlinks to directories as well as
relative symlinks. Symlinks are now always resolved during file lookup,
so the load stage no longer needs to special-case them.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Fix PCIE PLL lock on 440SPe Yucca board
Rupjyoti Sarmah [Mon, 21 Sep 2009 18:26:19 +0000 (11:26 -0700)]
ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board

u-boot reports a PCIE PLL lock error at boot time on Yucca board, and
left PCIe nonfunctional. This is fixed by making u-boot function
ppc4xx_init_pcie() to wait 300 uS after negating reset before the
first check of the PLL lock.

Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Make DDR2 timing for intip more robust
Dirk Eibach [Mon, 21 Sep 2009 11:27:14 +0000 (13:27 +0200)]
ppc4xx: Make DDR2 timing for intip more robust

DDR2 timing for intip was on the edge for some of the available chips
for this board. Now it is verfied to work with all of them.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoboard/linkstation/ide.c: Fix compile warning
Wolfgang Denk [Mon, 14 Sep 2009 22:26:02 +0000 (00:26 +0200)]
board/linkstation/ide.c: Fix compile warning

Fix warning: ide.c:60: warning: dereferencing type-punned pointer will
break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Guennadi Liakhovetski <lg@denx.de>
15 years agoppc: Clean up calling of phy_reset() during init
Peter Tyser [Thu, 17 Sep 2009 03:03:08 +0000 (22:03 -0500)]
ppc: Clean up calling of phy_reset() during init

Remove board-specific #ifdefs for calling phy_reset() during
initializtion

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years agoppc: Clean up calling of misc_init_r() during init
Peter Tyser [Thu, 17 Sep 2009 03:03:07 +0000 (22:03 -0500)]
ppc: Clean up calling of misc_init_r() during init

Remove board-specific #ifdefs for calling misc_init_r() during
initializtion

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Heiko Schocher <hs@denx.de>
15 years agoRemove deprecated 'autoscr' command/variables
Peter Tyser [Thu, 17 Sep 2009 02:38:10 +0000 (21:38 -0500)]
Remove deprecated 'autoscr' command/variables

The more standard 'source' command provides identical functionality to
the autoscr command.

Environment variable names/values on the MVBC_P, MVBML7, kmeter1,
mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'.

The 'autoscript' and 'autoscript_uname' environment variables are
also removed.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Heiko Schocher <hs@denx.de>
15 years agompc512x. Micron nand flash needs a reset before a read command is issued.
Paul Gibson [Wed, 16 Sep 2009 00:05:00 +0000 (10:05 +1000)]
mpc512x. Micron nand flash needs a reset before a read command is issued.

Micron nand flash needs a reset before a read command is issued.
The current mpc5121_nfc driver ignores the reset command.

15 years agoFDT: remove obsolete OF_CPU and OF_SOC macros.
Marcel Ziswiler [Wed, 9 Sep 2009 19:18:41 +0000 (21:18 +0200)]
FDT: remove obsolete OF_CPU and OF_SOC macros.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Heiko Schocher <hs@denx.de>
15 years agoTI: DaVinci DM365: Minor config cleanup
Sandeep Paulraj [Mon, 14 Sep 2009 18:57:47 +0000 (14:57 -0400)]
TI: DaVinci DM365: Minor config cleanup

The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag.
This is already included when we include the
config_cmd_default.h header file. So this flag is removed.
Also another flag to enable NAND functions was being
enabled incorrectly.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
15 years agoTI DaVinci DM365: Removing header file which does not exist
Sandeep Paulraj [Mon, 14 Sep 2009 19:03:06 +0000 (15:03 -0400)]
TI DaVinci DM365: Removing header file which does not exist

The DaVinci DM365 EVM board specific code was including a header file
which does not exist. So removing this header file.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
15 years agoTI DaVinci: DM355: Config Cleanup and Update
Sandeep Paulraj [Tue, 8 Sep 2009 22:08:06 +0000 (18:08 -0400)]
TI DaVinci: DM355: Config Cleanup and Update

This patch does the following
1) Enables the NAND driver which is now available.
2) Enables the 'CONFIG_MTD_DEVICE' as without this the
compilation will fail
3) We now have a safe place to store environment and defines
an offset where this can be stored. This offset value is such that it is after
the location where U-Boot is flashed using TI flash utilities.
4) Enables Bootdelay
5) Increases malloc() arena size. Manufacturers are coming out with
NAND with large blocks sizes of upto 1 MiB. It has been noticed that
as the block size of the NAND used is increased, if this particular
value is not increased, the NAND driver will output out of memory
errors.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
15 years agoboard/flagadm/flash.c: fix compile warning
Wolfgang Denk [Mon, 14 Sep 2009 22:09:21 +0000 (00:09 +0200)]
board/flagadm/flash.c: fix compile warning

Fix warning: flash.c:531: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kári Davíðsson <kd@flaga.is>
15 years agoCorrect ffs/fls regression for PowerPC etc
Simon Kagstrom [Thu, 17 Sep 2009 13:15:52 +0000 (15:15 +0200)]
Correct ffs/fls regression for PowerPC etc

Commits

  02f99901ed1c9d828e3ea117f94ce2264bf8389e
  52d61227b66d4099b39c8309ab37cb67ee09a405

introduced a regression where platform-specific ffs/fls implementations
were defined away. This patch corrects that by using PLATFORM_xxx
instead of the name itself.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Consolidate get_OPB_freq()
Stefan Roese [Mon, 14 Sep 2009 09:13:34 +0000 (11:13 +0200)]
ppc4xx: Consolidate get_OPB_freq()

All 4xx variants had their own, mostly identical get_OPB_freq()
function. Some variants even only had the OPB frequency calculated
in this routine and not supplied the sys_info.freqOPB variable
correctly (e.g. 405EZ). This resulted in incorrect OPB values passed
via the FDT to Linux.

This patch now removes all those copies and only uses one function
for all 4xx variants (except for IOP480 which doesn't have an OPB).

Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Enable commands for FDT enabled Linux booting on AMCC Acadia
Stefan Roese [Fri, 11 Sep 2009 15:09:45 +0000 (17:09 +0200)]
ppc4xx: Enable commands for FDT enabled Linux booting on AMCC Acadia

Acadia still used the "old" arch/ppc bootm commands for booting
Linux images without FDT. This patch now enables these fdt-aware
boot commands for Acadia as well.

Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Fix 405EZ uart base baud calculation
Stefan Roese [Fri, 11 Sep 2009 15:07:55 +0000 (17:07 +0200)]
ppc4xx: Fix 405EZ uart base baud calculation

With this fix, Linux correctly configures the baudrate when booting
with FDT passed from U-Boot to Linux.

Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc/85xx: Disable all async interrupt sources when we boot
Kumar Gala [Fri, 11 Sep 2009 20:28:41 +0000 (15:28 -0500)]
ppc/85xx: Disable all async interrupt sources when we boot

We should make sure to clear MSR[ME, CE, DE] when we boot an OS image
since we have changed the exception vectors and the OSes vectors might
not be setup we should avoid async interrupts at all costs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
Kumar Gala [Fri, 11 Sep 2009 18:52:45 +0000 (13:52 -0500)]
ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL

By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
Kumar Gala [Fri, 11 Sep 2009 18:41:49 +0000 (13:41 -0500)]
ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL

Use write_tlb and don't use memset so we can use the same code for
cpu_init_early_f between NAND SPL and not.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoNAND boot: change NAND loader's relocate SP to CONFIG param
Mingkai Hu [Fri, 11 Sep 2009 02:53:08 +0000 (10:53 +0800)]
NAND boot: change NAND loader's relocate SP to CONFIG param

So that we can set the NAND loader's relocate stack pointer
to the value other than the relocate address + 0x10000.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: add boot from NAND/eSDHC/eSPI support
Mingkai Hu [Fri, 11 Sep 2009 06:19:10 +0000 (14:19 +0800)]
ppc/85xx: add boot from NAND/eSDHC/eSPI support

The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Move code around to prep for NAND_SPL
Kumar Gala [Fri, 11 Sep 2009 17:32:01 +0000 (12:32 -0500)]
ppc/85xx: Move code around to prep for NAND_SPL

If we move some of the functions in tlb.c around we need less
ifdefs.  The first stage loader just needs invalidate_tlb and
init_tlbs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Repack tlb_table to save space
Kumar Gala [Fri, 11 Sep 2009 16:30:30 +0000 (11:30 -0500)]
ppc/85xx: Repack tlb_table to save space

We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up.  This savings can be helpful for NAND
style first stage boot loaders.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Introduce low level write_tlb function
Kumar Gala [Fri, 11 Sep 2009 16:27:00 +0000 (11:27 -0500)]
ppc/85xx: Introduce low level write_tlb function

Factor out the code we use to actually write a tlb entry.

set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Enable usb ehci support for p2020ds board
Roy Zang [Thu, 10 Sep 2009 06:44:48 +0000 (14:44 +0800)]
ppc/85xx: Enable usb ehci support for p2020ds board

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/8xxx: Misc DDR related fixes
Kumar Gala [Thu, 10 Sep 2009 19:54:55 +0000 (14:54 -0500)]
ppc/8xxx: Misc DDR related fixes

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoppc/85xx: Remove some bogus code from external interrupt handler.
Scott Wood [Thu, 20 Aug 2009 22:45:00 +0000 (17:45 -0500)]
ppc/85xx: Remove some bogus code from external interrupt handler.

Skipping the interrupted instruction will accomplish nothing other
than turning a spurious interrupt into a crash.

External interrupts are not machine checks, so don't count them as such.

Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Scott Wood [Thu, 20 Aug 2009 22:45:05 +0000 (17:45 -0500)]
ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.

Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoppc/85xx: Don't enable interrupts before we're ready
Scott Wood [Thu, 20 Aug 2009 22:44:20 +0000 (17:44 -0500)]
ppc/85xx: Don't enable interrupts before we're ready

We cannot handle any exceptions while running in AS1, as the exceptions
will transition back to AS0 without a valid mapping.

Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agompc8260: remove Ethernet node fixup to use generic FDT code.
Marcel Ziswiler [Fri, 11 Sep 2009 11:50:33 +0000 (07:50 -0400)]
mpc8260: remove Ethernet node fixup to use generic FDT code.

Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its
configs for the common mpc8260 code to use generic Ethernet fixup.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Tested-by: Heiko Schocher <hs@denx.de>
15 years agotools/netconsole: use ncb automatically if available
Mike Frysinger [Wed, 9 Sep 2009 16:20:21 +0000 (12:20 -0400)]
tools/netconsole: use ncb automatically if available

The standard netcat, while ubiquitous, doesn't handle broadcast udp packets
properly.  The local ncb util does however.  So if ncb can be located in
the standard locations, automatically use that instead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agotools/netconsole: make a bit more robust
Mike Frysinger [Wed, 9 Sep 2009 16:20:20 +0000 (12:20 -0400)]
tools/netconsole: make a bit more robust

The netcat utility likes to exit when it receives an empty packet (as it
thinks this means EOF).  This can easily occur when working with command
line editing as this behavior will be triggered when using backspace.  Or
with tabs and command line completion.  So create two netcat processes -
one to only listen (and put it into a loop), and one to do the sending.
Once the user quits the transmitting netcat, the listening one will be
killed automatically.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoarm: Define test_and_set_bit and test_and_clear bit for ARM
Simon Kagstrom [Mon, 24 Aug 2009 07:10:16 +0000 (09:10 +0200)]
arm: Define test_and_set_bit and test_and_clear bit for ARM

Needed for (e.g.) ubifs support to work.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
15 years agoDefine ffs/fls for all architectures
Simon Kagstrom [Mon, 24 Aug 2009 07:10:12 +0000 (09:10 +0200)]
Define ffs/fls for all architectures

UBIFS requires fls(), which is not defined for arm (and some other
architectures) and this patch adds it. The implementation is taken from
Linux and is generic. ffs() is also defined for those that miss it.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
15 years agoarm: Make arm bitops endianness-independent
Simon Kagstrom [Mon, 24 Aug 2009 07:10:03 +0000 (09:10 +0200)]
arm: Make arm bitops endianness-independent

Bring over the bitop implementations from the Linux
include/asm-generic/bitops/non-atomic.h to provide
endianness-independence.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
15 years agoMove __set/clear_bit from ubifs.h to bitops.h
Simon Kagstrom [Mon, 24 Aug 2009 07:09:50 +0000 (09:09 +0200)]
Move __set/clear_bit from ubifs.h to bitops.h

__set_bit and __clear_bit are defined in ubifs.h as well as in
asm/include/bitops.h for some architectures. This patch moves
the generic implementation to include/linux/bitops.h and uses
that unless it's defined by the architecture.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
15 years agostandalone: convert to kbuild style
Mike Frysinger [Fri, 4 Sep 2009 23:54:45 +0000 (19:54 -0400)]
standalone: convert to kbuild style

Clean up the arch/cpu/board/config checks as well as redundant setting of
srec/bin variables by using the kbuild VAR-$(...) style.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agomkconfig: split the board make target to multiple config targets
Wolfgang Denk [Tue, 15 Sep 2009 20:12:31 +0000 (22:12 +0200)]
mkconfig: split the board make target to multiple config targets

To simplify the top level makefile it useful to be able to parse
the top level makefile target to multiple individual target, then
put them to the config.h, leave the board config file to handle
the different targets.

Note that this method uses the '_'(underline) as the delimiter when
splits the board make target.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
This also reverts commit 511c02f611cb5afa1b8ca5980caaaabaa0de377f.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agokwbimage.c: Fix compile warning when building on 64 bit systems (again)
Wolfgang Denk [Tue, 15 Sep 2009 19:13:27 +0000 (21:13 +0200)]
kwbimage.c: Fix compile warning when building on 64 bit systems (again)

Commit 51003b89 attempted to fix a build problem on 64 bit systems,
but just turned it into a build problem on 32 bit systems (silly me).

Now do the Right Thing (TM) and use a "%zu" printf format.

Also fix spelling error.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoboard/amcc/common/flash.c: Fix compile warning
Wolfgang Denk [Fri, 11 Sep 2009 09:30:34 +0000 (11:30 +0200)]
board/amcc/common/flash.c: Fix compile warning

Fix warning: ../common/flash.c:917: warning: dereferencing type-punned
pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
15 years agoboard/amcc/yucca/flash.c: Fix compile warning
Wolfgang Denk [Fri, 11 Sep 2009 09:47:07 +0000 (11:47 +0200)]
board/amcc/yucca/flash.c: Fix compile warning

Fix warning: flash.c:919: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
15 years agoboard/amcc/taihu/flash.c: Fix compile warning
Wolfgang Denk [Fri, 11 Sep 2009 09:44:39 +0000 (11:44 +0200)]
board/amcc/taihu/flash.c: Fix compile warning

Fix warnings:
flash.c: In function 'write_word_1':
flash.c:696: warning: dereferencing type-punned pointer will break strict-aliasing rules
flash.c: In function 'write_word_2':
flash.c:1044: warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
15 years agoboard/etin/debris/phantom.c: Fix compile error
Wolfgang Denk [Fri, 11 Sep 2009 09:37:20 +0000 (11:37 +0200)]
board/etin/debris/phantom.c: Fix compile error

Fix build problem caused by commit e84aba13: "Replace BCD2BIN and
BIN2BCD macros with inline functions"

phantom.c:163: error: redefinition of 'bcd2bin'
/home/wd/git/u-boot/work/include/bcd.h:16: error: previous definition of 'bcd2bin' was here
phantom.c:168: error: redefinition of 'bin2bcd'
/home/wd/git/u-boot/work/include/bcd.h:21: error: previous definition of 'bin2bcd' was here

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Sangmoon Kim <dogoil@etinsys.com>
15 years agoboard/dave/common/flash.c: fix compile warning
Wolfgang Denk [Fri, 11 Sep 2009 09:28:21 +0000 (11:28 +0200)]
board/dave/common/flash.c: fix compile warning

Fix warning: ../common/flash.c:668: warning: dereferencing type-punned
pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andrea Marson <andrea.marson@dave-tech.it>
15 years agoboard/esd/cpci750/ide.c: fix compile warning
Wolfgang Denk [Fri, 11 Sep 2009 09:15:31 +0000 (11:15 +0200)]
board/esd/cpci750/ide.c: fix compile warning

Fix warning: ide.c:54: warning: dereferencing type-punned pointer will
break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>