Hans de Goede [Sat, 3 Oct 2015 14:13:19 +0000 (16:13 +0200)]
sunxi: power: Drop protection against multiple calls from axp221 axp_init()
The only thing axp221.c's axp_init() does which needs protection
against multiple calls is calling pmic_bus_init, and pmic_bus_init()
itself is already protected against being called multiple times.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 3 Oct 2015 13:21:53 +0000 (15:21 +0200)]
sunxi: power: Change A23/A33 VDD-SYS default from 1.2V to 1.1V
Change the axp223 dcdc2 / VDD-SYS default from 1.2V to 1.1V, 1.1V is the
value recommended by Allwinner and is what most fex files specify.
This has been tested on a number of A23/A33 tablets including on an
A23 Ippo-q8h-v1.2 PCB tablet which has a fex file which specifies 1.2V
(which is where our original 1.2V default comes from).
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 3 Oct 2015 13:18:33 +0000 (15:18 +0200)]
sunxi: power: Unify axp pmic function names
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 30 Sep 2015 13:22:42 +0000 (15:22 +0200)]
sunxi: power: Make all voltages configurable through Kconfig
On boards with axp221/223 pmic-s we already allow configuring most
voltages. Make the Kconfig options for these also apply to boards with
axp152 / axp209 pmic-s and extend them to configure all voltages.
The Kconfig defaults are chosen so that this commit does not introduce any
functional changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 30 Sep 2015 13:12:30 +0000 (15:12 +0200)]
sunxi: Kconfig-ify CONFIG_AXP152_POWER and _AXP209_POWER
Kconfig-ify CONFIG_AXP152_POWER and _AXP209_POWER settings, removing
them from CONFIG_SYS_EXTRA_OPTIONS.
Note that sun5i boards can have either an AXP209 or an AXP152 pmic, the
Kconfig default is AXP209, boards with an AXP152 must explicitly select
this. Likewise boards without a pmic must explicitly select SUNXI_NO_PMIC
in their defconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 29 Sep 2015 13:06:26 +0000 (15:06 +0200)]
sunxi: Remove board defconfig-s for specific Q8 tablet PCB-s
We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.
Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.
The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.
This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 13 Sep 2015 10:31:24 +0000 (12:31 +0200)]
sunxi: Switch to using malloc_simple for the spl
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
Hans de Goede [Sun, 13 Sep 2015 11:02:48 +0000 (13:02 +0200)]
sunxi: Enable CONFIG_SPL_STACK_R
Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.
Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Hans de Goede [Sun, 13 Sep 2015 13:04:17 +0000 (15:04 +0200)]
malloc_simple: Add support for switching to DRAM heap
malloc_simple uses a part of the stack as heap, initially it uses
SYS_MALLOC_F_LEN bytes which typically is quite small as the initial
stacks sits in SRAM and we do not have that much SRAM to work with.
When DRAM becomes available we may switch the stack from SRAM to DRAM
to give use more room. This commit adds support for also switching to
a new bigger malloc_simple heap located in the new stack.
Note that this requires spl_init to be called before spl_relocate_stack_gd
which in practice means that spl_init must be called from board_init_f.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
Hans de Goede [Sun, 13 Sep 2015 12:45:15 +0000 (14:45 +0200)]
malloc_simple: Add Kconfig option for using only malloc_simple in the SPL
common/dlmalloc.c is quite big, both in .text and .data usage, therefor
on some boards the SPL is build to use only malloc_simple.c and not the
dlmalloc.c code. This is done in various include/configs/foo.h with the
following construct:
Hans de Goede [Sun, 13 Sep 2015 13:36:18 +0000 (15:36 +0200)]
spl: spl_relocate_stack_gd: Do not unnecessarily clear bss
spl_relocate_stack_gd only gets called from arch/arm/lib/crt0.S which
clears the bss directly after calling it, so there is no need to clear
it from spl_relocate_stack_gd.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:31 +0000 (16:40 -0400)]
sbc8641d: increase monitor size from 256k to 384k
Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure. A bisect led to commit 6eed3786c68c8a49d
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:
u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144
i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.
We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:28 +0000 (16:40 -0400)]
sbc8641d: set proper environment sector size.
When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k. But the device sector
size is 1/2 that, as can be seen from "fli" output:
Paul Gortmaker [Sat, 17 Oct 2015 20:40:27 +0000 (16:40 -0400)]
sbc8641d: increase malloc pool size to a sane default
Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:
Unable to save the rest of sector (253952)
Allow for 1M malloc pool, the same as used on the sbc8548 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function] Signed-off-by: Tom Rini <trini@konsulko.com>
The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.
For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.
In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.
Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math] Signed-off-by: Tom Rini <trini@konsulko.com>
dfu: dfu_sf: Use the erase sector size for erase operations
SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.
To illustrate the problem:
Copying data from PC to DFU device
Download [=========================] 100% 478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!
In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.
478208 = 7 entire sectors of 64kiB + 19456 bytes.
Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.
Fix the issue by always erasing with the erase sector size.
Tom Rini [Mon, 19 Oct 2015 15:20:54 +0000 (11:20 -0400)]
Revert "arm: Remove d2net_v2 defconfig file"
Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config. To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.
Lubomir Rintel [Wed, 14 Oct 2015 15:17:54 +0000 (17:17 +0200)]
ARM: rpi: add another revision of Raspberry Pi A+
Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Eric Cooper [Mon, 12 Oct 2015 23:18:52 +0000 (19:18 -0400)]
ARM: dockstar: move start of environment area
The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device. This patch moves the environment to a higher address to avoid
that.
Lokesh Vutla [Thu, 8 Oct 2015 06:01:47 +0000 (11:31 +0530)]
ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Tom Rini [Sat, 17 Oct 2015 12:04:11 +0000 (08:04 -0400)]
arch/powerpc/config.mk: Pass -fno-ira-hoist-pressure when possible
There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.
Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Tom Rini <trini@konsulko.com>
Dinh Nguyen [Thu, 15 Oct 2015 15:13:36 +0000 (10:13 -0500)]
arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Anthony Felice [Fri, 9 Oct 2015 20:38:39 +0000 (16:38 -0400)]
vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).
Signed-off-by: Anthony Felice <tony.felice@timesys.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Thierry Reding [Thu, 20 Aug 2015 09:52:15 +0000 (11:52 +0200)]
armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Stefan Agner [Wed, 14 Oct 2015 17:58:43 +0000 (10:58 -0700)]
arm: vf610twr: improve memory layout
Currently, the device tree relocation is disabled, likely to
keep some DDR3 RAM at the end for Cortex-M4 firmwares. This
can be archived using bootm_size, which limits the image
processing range of the boot commands.
Move the device tree standard load address to a higher address
which aligns better with what we are doing on other boards.
Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Stefan Agner [Wed, 14 Oct 2015 05:11:42 +0000 (22:11 -0700)]
mtd: nand: vf610_nfc: resync with upstream Linux version
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678
Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
If flipped bits are below threshold, also return an empty
OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
to reflect better what they really representing.
The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Scott Wood <scottwood@freescale.com>
Fabio Estevam [Sat, 3 Oct 2015 17:21:00 +0000 (14:21 -0300)]
ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com> Tested-by: Sinan Akman <sinan@writeme.com> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Ludger Dreier [Mon, 12 Oct 2015 11:34:24 +0000 (13:34 +0200)]
env_eeprom.c: Correct using saved environment
The changes in ed6a5d4 unintentionally broke support for reading the
environment saved to eeprom back. To correct this the crc-check and
decision on which environment to use is now moved to env_relocate_spec.
This is done for both the "redundant env" and the "single env" case.
MTD partitioning in current pcm052 configuration is inconsistent.
Fix it across MTDPARTS_DEFAULT, CONFIG_EXTRA_ENV_SETTINGS, and
CONFIG_ENV_OFFSET[_REDUND].
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tom Rini [Sun, 11 Oct 2015 20:48:36 +0000 (16:48 -0400)]
test/fs/fs-test.sh: Update expected results and TC10 logic
With the changes in 7a3e70c we now get read(2) behavior so trying to
read 2MB with 1MB left in the file results in 1MB read and a warning.
We update the test logic here to make sure we read back 1MB as expected.
This change however changes the overall summary as while EXT4 continues
to not have offset support the test now fails when expected to pass
rather than fails when expected to fail (and we report that as pass).
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config
According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.
The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.
Fix variation in timestamps caused by timezone differences.
When building with SOURCE_DATE_EPOCH set, avoid use of mktime in
default_image.c, which converts the timestamp into localtime. This
causes variation based on timezone when building u-boot.img and
u-boot-sunxi-with-spl.bin targets.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Paul Kocialkowski <contact@paulk.fr>
Tom Rini [Thu, 27 Aug 2015 19:42:41 +0000 (15:42 -0400)]
common/image.c: Make boot_get_ramdisk() perform a check for Android images
In 2dd4632 the check for where a ramdisk is found on an Android image
was got moved into the "normal" loop here, causing people to have to
pass the kernel address in the ramdisk address location in order to have
Android boot still. This changed previous behavior so perform a check
early in the function to see if we have an Android image and if so use
that as where to look for the ramdisk (which is what the rest of the
code here expects). We allow for this to still be overridden with an
explicit ramdisk address to be passed as normal.
Cc: Rob Herring <robh@kernel.org> Reported-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Tom Rini <trini@konsulko.com>
Ian Campbell [Tue, 29 Sep 2015 09:27:09 +0000 (10:27 +0100)]
arndale: Apply Cortex-A15 errata #773022 and #774769
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.
However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.
Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.
This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.
The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.
Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.
I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.
Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Rob Herring [Mon, 5 Oct 2015 19:37:07 +0000 (14:37 -0500)]
image: fix support for Android boot images with no ramdisk
If an Android boot image does not contain a ramdisk, make sure rd_len
and rd_data are returned to indicate no ramdisk rather than just relying
on returning an error.
Julius Werner [Wed, 7 Oct 2015 03:03:53 +0000 (20:03 -0700)]
Add support for LZ4 decompression algorithm
This patch adds support for LZ4-compressed FIT image contents. This
algorithm has a slightly worse compression ration than LZO while being
nearly twice as fast to decompress. When loading images from a fast
storage medium this usually results in a boot time win.
Sandbox-tested only since I don't have a U-Boot development system set
up right now. The code was imported unchanged from coreboot where it's
proven to work, though. I'm mostly interested in getting this recognized
by mkImage for use in a downstream project.
Signed-off-by: Julius Werner <jwerner@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
Overwriting an empty file not created by U-Boot did not work, and it
could even corrupt the FAT. Moreover, creating empty files or emptying
existing files allocated a cluster, which is not standard.
Fix this by always keeping empty files clusterless as specified by
Microsoft (the start cluster must be set to 0 in the directory entry in
that case), and by supporting overwriting such files.
set_contents() had uselessly split calls to set_cluster(). Merge these
calls, which removes some cases of set_cluster() being called with a
size of zero.
set_cluster() was using a temporary buffer without enforcing its
alignment for DMA and cache. Moreover, it did not check the alignment of
the passed buffer, which can come directly from applicative code or from
the user.
This could cause random data corruption, which has been observed on
i.MX25 writing to an SD card.
Fix this by only passing ARCH_DMA_MINALIGN-aligned buffers to
disk_write(), which requires the introduction of a buffer bouncing
mechanism for the misaligned buffers passed to set_cluster().
By the way, improve the handling of the corresponding return values from
disk_write():
- print them with debug() in case of error,
- consider that there is an error is disk_write() returns a smaller
block count than the requested one, not only if its return value is
negative.
After this change, set_cluster() and get_cluster() are almost
symmetrical.
Ryan Harkin [Fri, 9 Oct 2015 16:18:08 +0000 (17:18 +0100)]
vexpress64: juno: use /dev/sda2
This patch changes the default "root=" parameter to "/dev/sda2".
Many linux based distros use /dev/sda1 for their boot partition; this is
often not a rootfs that can be used by the "root=" parameter.
Linaro images use /dev/sda1 as a boot partition, although this of a
different nature to a distro image. Linaro uses /dev/sda2 for the rootfs
partition.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:07 +0000 (17:18 +0100)]
vexpress64: juno: add alternate kernel and device tree filenames
The latest Juno firmware stores the files in NOR flash as "norkern" for
kernel binary, "board.dtb" for the device tree binary.
The "old" firmware used the name "Image" for the kernel binary and
"juno" for the device tree binary.
Rather than just change the default U-Boot configuration to use the new
names, breaking users with the old firmware, attempt to load the default
filename first. If that fails, attempt to load the alternate filename.
I've echo'd that we are loading the alternate file to counter the
output from "afs load" shown if the first load attempt fails. For
example, I see output like this on my Juno board when it's configured
the with the "old" firmware:
image "norkern" not found in flash
Loading Image instead of norkern
loaded region 0 from 08500000 to 80000000, 00AB6318 bytes
image "board.dtb" not found in flash
Loading juno instead of board.dtb
loaded region 0 from 0A000000 to 83000000, 00003188 bytes
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:02 +0000 (17:18 +0100)]
vexpress64: fvp dram: add DRAM configuration
Create an additional FVP configuration to boot images pre-loaded into
DRAM.
Sometimes it's preferential to boot the model by loading the files
directly into DRAM via model parameters, rather than using
SemiHosting.
An example of model parmaters that are used to pre-load the files
into DRAM:
--data cluster0.cpu0=Image@0x80080000 \
--data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
--data cluster0.cpu0=uInitrd@0x84000000
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Update board/armltd/vexpress64/Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
Ryan Harkin [Fri, 9 Oct 2015 16:18:00 +0000 (17:18 +0100)]
vexpress64: Kconfig: tidy up
The FVP and Juno settings were identical, but duplicated, so I removed
the duplication with this patch.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Adjust logic to keep if/endif in the file] Signed-off-by: Tom Rini <trini@konsulko.com>
Jagan Teki [Mon, 7 Sep 2015 20:08:50 +0000 (01:38 +0530)]
spi: zynq_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
projects / u-boot / log