Mike Frysinger [Fri, 24 Dec 2010 17:57:23 +0000 (12:57 -0500)]
asm-offsets: generate bd_t size
Some ports set up the board info structure at the same time as the global
data structure, and largely keep them together. So generate a define for
the board info struct too.
Mike Frysinger [Thu, 23 Dec 2010 20:40:12 +0000 (15:40 -0500)]
miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Mike Frysinger [Tue, 21 Dec 2010 19:08:27 +0000 (14:08 -0500)]
load_addr: move to common env code
Rather than keep the load_addr definition with the bootm code (which
just happens to use this), move it to the common env code. This way
we can disable bootm support completely while retaining load_addr
usage with many other commands.
Mike Frysinger [Mon, 20 Dec 2010 23:57:09 +0000 (18:57 -0500)]
config_cmd_defaults.h: new header for common u-boot command defaults
We have config_defaults.h which are random configuration settings that
everyone gets by default. We also have config_cmd_default.h which is a
recommended list of defaults but boards have to opt into. Now we have
config_cmd_defaults.h which is a list of defaults that everyone gets
and has to actively opt out of.
For now, we populate it with the bootm command which previously was
unable to be disabled.
Dirk Behme [Sat, 18 Dec 2010 06:40:28 +0000 (07:40 +0100)]
OMAP3: EVM: Convert omap3_evm_version to u32
Convert the variable omap3_evm_version to u32 to work around
some broken linkers from older tool chains. E.g. CodeSourcery's
2009q1-203 ld 2.19.51.20090205. Without this, these linkers
stop linking 'omap3_evm' or at least issue a warning. Like
Li Yang [Thu, 25 Nov 2010 17:06:09 +0000 (17:06 +0000)]
fsl_esdhc: Fix the voltage validation process
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
Signed-off-by: Li Yang <leoli@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang [Thu, 25 Nov 2010 17:06:07 +0000 (17:06 +0000)]
fsl_esdhc: Use mmc_set_clock to set initial speed
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Li Yang [Thu, 25 Nov 2010 17:06:09 +0000 (17:06 +0000)]
fsl_esdhc: Fix the voltage validation process
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
Signed-off-by: Li Yang <leoli@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang [Thu, 25 Nov 2010 17:06:07 +0000 (17:06 +0000)]
fsl_esdhc: Use mmc_set_clock to set initial speed
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Reinhard Meyer [Thu, 18 Nov 2010 03:14:26 +0000 (03:14 +0000)]
MTD/NAND: fix nand_base.c to use get_timer() correctly
This is part of the timer cleanup effort.
In the future we only use get_timer() in its intended way to
program timeout loops.
reset_timer() shall not be used anymore.
Mike Frysinger [Wed, 15 Dec 2010 12:17:31 +0000 (07:17 -0500)]
config.mk: unify duplicated flag setting
Multiple rules are using the expanded AFLAGS/CFLAGS settings and some are
getting so long that the rules need to be line wrapped. So unify them in
one variable, use that variable in the rule, and then unwrap things. This
makes the actual `make` output nicer as it doesn't have line continuations
in it anymore.
Mike Frysinger [Wed, 8 Dec 2010 11:26:04 +0000 (06:26 -0500)]
hashtable: drop all non-reentrant versions
The non-reentrant versions of the hashtable functions operate on a single
shared hashtable. So if two different people try using these funcs for
two different purposes, they'll cause problems for the other.
Avoid this by converting all existing hashtable consumers over to the
reentrant versions and then punting the non-reentrant ones.
missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset()
functions which resulted in build errors such as:
cpu.c:128: error: conflicting types for 'do_reset'
include/command.h:102: error: previous declaration of 'do_reset' was here
PowerPC, nand_spl: Add relocation support for -fpic
By rearranging the linker script we get support for
relocation of -fpic for free.
Move __got2_entries outside _GOT2_TABLE_ defining scope
matching the rest of PowerPC
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
Priyanka Jain [Tue, 26 Oct 2010 09:22:19 +0000 (14:52 +0530)]
RTC driver for PT7C4338 chip.
PT7C4338 chip is being manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Timur Tabi <timur@freescale.com>
Stefan Roese [Mon, 25 Oct 2010 16:31:48 +0000 (18:31 +0200)]
cfi_flash: Add optional config register write to cfi-detection
This patch adds the possibility to (optinally) write to the
flash configuration register. The Intel style CFI chips support
such a register that can be used to configure the operation
mode to a non-default value.
This method will be used by the t3corp board, which needs to
configure the DS617 Xilinx flash for async read mode.
Stefan Roese [Mon, 25 Oct 2010 16:31:39 +0000 (18:31 +0200)]
cfi_flash: Use flash_read32() in sector_erased()
The function sector_erased() is modified to not use pointer
access, but to use the correct accessor functions. This fixes a
problem on the t3corp board with the Xilinx DS617 flash chips. Here
a board specific accessor function is needed to read from flash
in 32bit mode. This patch enables such an operation mode.
Stefan Roese [Mon, 25 Oct 2010 16:31:29 +0000 (18:31 +0200)]
cfi_flash: Fix problems with status/id read mode
This patch adds some calls to set the flash chip in the read-status-
register- or read-id-mode before the corresponding register is
read back. This problem was detected while porting the common CFI
driver to support the Xilinx DS617 flash chips.
Stefan Roese [Fri, 26 Nov 2010 18:17:40 +0000 (19:17 +0100)]
ppc4xx/POST: Change ethernet test loop count to a default of 10
This patch changes the PPC4xx ethernet POST loop test count from
currently 192 (256 - 64) to a default of 10. While doing this the max
frame size is increased. Each loop run uses a different frame size,
starting with a max of 1514 bytes, down to 64. The default loop
count of 10 can be overriden using CONFIG_SYS_POST_ETH_LOOPS in the
board config header.
The TEST_NUM loop has been removed as it was never used.
The main reason for this change is to reduce the boot time on boards
using this POST test, like the lwmon5 board. This change reduces the
boot time by about 600ms on the lwmon5 board.
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
Stefan Roese [Fri, 26 Nov 2010 14:45:48 +0000 (15:45 +0100)]
ppc4xx: Update lwmon5 board support
This patch includes the following changes for the lwmon5 board support:
- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
(CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support
Stefan Roese [Mon, 25 Oct 2010 16:32:08 +0000 (18:32 +0200)]
ppc4xx: t3corp: Add support for the Xilinx DS617 flash chip
The t3corp board has an Xilinx DS617 flash chip connected to the
onboard FPGA. This patch adds support for these chips. Board
specific flash accessor functions are needed, since the chips
can only be read correctly in 16bit mode.
Additionally the FPGA chip-selects are configured for device-paced
transfers (ready is enabled).
Scott Wood [Fri, 10 Dec 2010 21:13:39 +0000 (15:13 -0600)]
powerpc/nand spl: link libgcc
Recent GCC (4.4+) performs out-of-line epilogues in some cases, when
optimizing for size. It causes a link error for _restgpr_30_x (and similar)
if libgcc is not linked.
It actually increases size with very small binaries, due to the fixed size
of the out-of-line code, and not having any functions that actually need to
restore more than 2 or 3 registers. But I don't see a way to turn it off,
other than asking GCC to optimize for speed -- which may also increase
size for some boards.
Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
Armada100: Add Board Support for Marvell Aspenite-DB
Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with
* Processor upto 1.2GHz
* Parallel 1Gb x8 DDR2-1066 MHz
* 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR
* Footprints for eMMC/eSD NAND & MMC x8 card
* 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket
* SEAF memory board, subset of PISMO2
With Peripherals:
* 4.3” WVGA 24-bit LCD
* Audio codecs (AC97 & I2S), TSI
* VGA camera
* Video in via 3 RCA jacks, and HDMI type C out
* Marvell 88W8688 802.11bg/BT module
* GPS RF IC
* Dual analog mics & speakers, headset jack, LED, ambient light sensor
* USB2.0 HS host (A), OTG (micro AB)
* FE PHY, PCIE Mini Card slot
* GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR
This patch adds basic board support with DRAM and UART functionality
The patch is tested for boot from DRAM using XDB
arm: Add Support for Marvell ARMADA 100 Familiy SoCs
ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100
Scott Wood [Fri, 10 Dec 2010 21:13:39 +0000 (15:13 -0600)]
powerpc/nand spl: link libgcc
Recent GCC (4.4+) performs out-of-line epilogues in some cases, when
optimizing for size. It causes a link error for _restgpr_30_x (and similar)
if libgcc is not linked.
It actually increases size with very small binaries, due to the fixed size
of the out-of-line code, and not having any functions that actually need to
restore more than 2 or 3 registers. But I don't see a way to turn it off,
other than asking GCC to optimize for speed -- which may also increase
size for some boards.
Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
Stefan Roese [Tue, 14 Dec 2010 16:49:52 +0000 (17:49 +0100)]
ppc4xx: Fix missing linker scripts for partial linking
This patch fixes the acadia_nand and kilauea_nand linker scripts
which have been missing in commit ee8028b7 [ppc4xx: Cleanup for
partial linking and --gc-sections]
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bernhard Weirich <Bernhard.Weirich@riedel.net>
Baidu Boy [Mon, 29 Nov 2010 13:10:45 +0000 (21:10 +0800)]
mpc83xx: fix pcie enumeration
This patch fix a problem for the pcie enumeration for mpc83xx cpus. Without
this we will not get correct value in hose->regions[...].
The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed.
Because we will use this pointer as a parameter to call function
mpc83xx_pcie_register_hose().
Signed-off-by: Baidu Boy <liucai.lfn@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Fri, 3 Dec 2010 19:03:45 +0000 (13:03 -0600)]
p1022ds: fix switching of DIU/LBC signals
On the P1022, the pins which drive the video display (DIU) are muxed with the
local bus controller (LBC), so if the DIU is active, the pins need to be
temporarily muxed to LBC whenever accessing NOR flash.
The code which handled this transition is checking and changing the wrong
bits in PMUXCR.
Also add a follow-up read after a write to NOR flash if we're going to
mux back to DIU after the write, as described in the P1022 RM.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P.V.Suresh [Sat, 4 Dec 2010 05:07:23 +0000 (10:37 +0530)]
fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller
eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.
Signed-off-by: P.V.Suresh <pala@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
John Schmoller [Thu, 2 Dec 2010 17:43:10 +0000 (11:43 -0600)]
fsl_upm: Add MxMR/MDR synchronization
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):
"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."
The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode
Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.
Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.
This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card. We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.
Additionally, we clean up the code a bit to remove an unnecessary second
define.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com>
Dirk Behme [Sat, 11 Dec 2010 16:01:00 +0000 (11:01 -0500)]
OMAP3: SPI driver
CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Balaji T K [Thu, 25 Nov 2010 10:52:04 +0000 (16:22 +0530)]
ARMV7: OMAP4: twl6030 add battery charging support
Add battery charging support twl6030 driver.
Add support for battery voltage and current measurements.
Add command to get battery status and start/stop battery charging from USB.
Signed-off-by: Balaji T K <balajitk@ti.com> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Nick Thompson [Sat, 11 Dec 2010 15:46:46 +0000 (10:46 -0500)]
davinci: Rewrite timer.c to use tbl/tbu emulation variables in gd
This change allows the davinci timer functions to be used before
relocation since it avoids using static variables prior to BSS being
made available.
The code is based on that used in the at91 timers, modified to use
a davinci specific hardware timer. It also maintains reset_timer()
to allow deprecated timer usage to continue to work (for example,
in nand_base.c)
Signed-off-by: Nick Thompson <nick.thompson@ge.com> Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Tested-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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