]> git.sur5r.net Git - u-boot/log
u-boot
7 years agox86: minnowmax: Enable USB xHCI support
Bin Meng [Wed, 19 Jul 2017 13:50:10 +0000 (21:50 +0800)]
x86: minnowmax: Enable USB xHCI support

BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: minnowmax: Add a environment variable for USB power-on delay
Bin Meng [Wed, 19 Jul 2017 13:50:09 +0000 (21:50 +0800)]
x86: minnowmax: Add a environment variable for USB power-on delay

Occasionally it was observed that on Intel MinnowMax board, with a
USB 2.0 device connected to the bottom port, when doing 'usb start'
on the xHCI controller:

  scanning bus 0 for devices... cannot reset port 3!?

But neither of the two USB ports is routed to xHCI root port 3.
Adding some debug information shows that xHCI port 3 PORTSC register
mysteriously reports both CCS = 1 and CSC = 1.

This is not seen every time. After increasing the timeout to wait
for power to become stable, the issue is gone. So this indicates
current default USB power-on delay (20ms) might be at a critical
region where power is stable/unstable. U-Boot provides a mechanism
to have a environment variable to override the default one. Add
one for MinnowMax.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Convert CONFIG_USB_XHCI_PCI to Kconfig
Bin Meng [Wed, 19 Jul 2017 13:50:08 +0000 (21:50 +0800)]
usb: xhci: Convert CONFIG_USB_XHCI_PCI to Kconfig

Add CONFIG_USB_XHCI_PCI as a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: cmd: Print actual packet size for super speed devices
Bin Meng [Wed, 19 Jul 2017 13:50:07 +0000 (21:50 +0800)]
usb: cmd: Print actual packet size for super speed devices

USB 3.0 defines bMaxPacketSize0 field in the device descriptor as
the exponent of 2, so let's print the calculated actual size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agoconfigs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boards
Bin Meng [Wed, 19 Jul 2017 13:50:06 +0000 (21:50 +0800)]
configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boards

Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
Bin Meng [Wed, 19 Jul 2017 13:50:05 +0000 (21:50 +0800)]
usb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS

EHC reports supported maximum number of ports in the HCSPARAMS
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agoconfigs: Remove CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS in all boards
Bin Meng [Wed, 19 Jul 2017 13:50:04 +0000 (21:50 +0800)]
configs: Remove CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS in all boards

Now that xHCD does not use CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
Bin Meng [Wed, 19 Jul 2017 13:50:03 +0000 (21:50 +0800)]
usb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS

xHC reports supported maximum number of ports in the HCSPARAMS1
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Change MAX_HC_PORTS to 255
Bin Meng [Wed, 19 Jul 2017 13:50:02 +0000 (21:50 +0800)]
usb: xhci: Change MAX_HC_PORTS to 255

HCSPARAMS1:MaxPorts field specifies the maximum port number value,
and its valid values are in the range of 1 to 255.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: hub: Add 3.0 hub port status mask of 2.0 hub
Bin Meng [Wed, 19 Jul 2017 13:50:01 +0000 (21:50 +0800)]
usb: hub: Add 3.0 hub port status mask of 2.0 hub

USB 3.0 hub port status has different bit position regarding to
port power, port speed, etc. But others are the same as 2.0 hubs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: hub: Change USB hub descriptor to match USB 3.0 hubs
Bin Meng [Wed, 19 Jul 2017 13:50:00 +0000 (21:50 +0800)]
usb: hub: Change USB hub descriptor to match USB 3.0 hubs

USB 3.0 hubs have a slightly different hub descriptor than USB 2.0
hubs, with a fixed (rather than variable length) size. Change the
host controller drivers that access those last two fields
(DeviceRemovable and PortPowerCtrlMask) to use the union.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: hub: Revise wLength for 'get port status' request
Bin Meng [Wed, 19 Jul 2017 13:49:59 +0000 (21:49 +0800)]
usb: hub: Revise wLength for 'get port status' request

For accuracy, we should use 'sizeof(struct usb_port_status)' as the
wLength for 'get port status' request, although it happens to be
equal to 'sizeof(struct usb_hub_status)'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hub
Bin Meng [Wed, 19 Jul 2017 13:49:58 +0000 (21:49 +0800)]
usb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hub

Testing a USB 3.0 hub by connecting it to the xHCI port on Intel
MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI
reports a transfer event TRB with a completion code 6 which means
'Stall Error'.

In fact super speed USB hub descriptor type is 0x2a, not 0x29.
Sending correct SETUP packet to the hub makes it not stall anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: hub: Update handling connect status/change in usb_scan_port()
Bin Meng [Wed, 19 Jul 2017 13:49:57 +0000 (21:49 +0800)]
usb: hub: Update handling connect status/change in usb_scan_port()

It was observed that on Intel MinnowMax board, when xHCI is enabled
in the BayTrail SoC, with a USB 3.0 device connected to the bottom
USB 3.0 port (mapped to xHCI root port #7), its PORTSC register is
always 0x201203 (CCS = 1, CSC = 0). The root cause of such behavior
is unknown yet. Connect status change bit is set on the same port
with a USB 2.0 device (mapped to xHCI port #1, which is a different
port on the root hub).

With current logic in usb_scan_port(), the enumeration process will
abort if it does not detect a connect status change on a hub port.
However since a device connection status is correctly reported, the
enumeration process can still continue.

With this change, USB device connected to the bottom blue port on
MinnowMax board can be enumerated under either SS or HS mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
7 years agousb: xhci: Add input slot context in xhci_set_configuration()
Bin Meng [Wed, 19 Jul 2017 13:49:56 +0000 (21:49 +0800)]
usb: xhci: Add input slot context in xhci_set_configuration()

A valid input slot context for a 'configure endpoint' command requires
the 'Context Entries' field to be initialized to the index of the last
valid endpoint context that is defined by the target configuration. We
set up the 'Context Entries' field, but we forget to include the input
slot context in the input control context 'Add Context flags' bitmap.
So xHC will simply ignore input slot context and continue using its own
which contains old information of the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Initialize scratchpad buffer array and scratchpad buffers
Bin Meng [Wed, 19 Jul 2017 13:49:55 +0000 (21:49 +0800)]
usb: xhci: Initialize scratchpad buffer array and scratchpad buffers

The scratchpad buffer array is used to define the locations of
statically allocated memory pages that are available for the
private use of the xHC. The xHCI spec explicitly mentions that
system software shall allocate the scratchpad buffers before
placing the xHC in to Run mode (Run/Stop (R/S) = ‘1’), however
U-Boot is missing this part.

This causes xHC on Intel platform does not respond the very first
'enable slot' command that is given to xHC and the 'enable slot'
command completion event TRB is never generated and xHC seems to
hang forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Correct command TRB 4th dword initialization
Bin Meng [Wed, 19 Jul 2017 13:49:54 +0000 (21:49 +0800)]
usb: xhci: Correct command TRB 4th dword initialization

In xhci_queue_command(), when the command is not 'reset endpoint',
'stop endpoint' or 'set TR dequeue pointer', endpoint ID should not
be encoded in the TRB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: xhci: Remove incorrect comments for struct xhci_container_ctx
Bin Meng [Wed, 19 Jul 2017 13:49:53 +0000 (21:49 +0800)]
usb: xhci: Remove incorrect comments for struct xhci_container_ctx

There is no member called 'dma' in struct xhci_container_ctx. Remove
the comments that mentions it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
7 years agousb: host: ohci-generic: add generic PHY support
Patrice Chotard [Tue, 18 Jul 2017 09:57:14 +0000 (11:57 +0200)]
usb: host: ohci-generic: add generic PHY support

Extend ohci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: ohci-generic: add RESET support
Patrice Chotard [Tue, 18 Jul 2017 09:57:13 +0000 (11:57 +0200)]
usb: host: ohci-generic: add RESET support

use array to save deasserted resets reference in order to
assert them in case of error during probe() or during driver
removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: ohci-generic: add CLOCK support
Patrice Chotard [Tue, 18 Jul 2017 09:57:12 +0000 (11:57 +0200)]
usb: host: ohci-generic: add CLOCK support

use array to save enabled clocks reference in order to
disabled them in case of error during probe() or during
driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: ehci-generic: add generic PHY support
Patrice Chotard [Tue, 18 Jul 2017 09:57:11 +0000 (11:57 +0200)]
usb: host: ehci-generic: add generic PHY support

Extend ehci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: ehci-generic: add error path and .remove callback
Patrice Chotard [Tue, 18 Jul 2017 09:57:10 +0000 (11:57 +0200)]
usb: host: ehci-generic: add error path and .remove callback

Use an array to save enabled clocks reference and deasserted resets
in order to respectively disabled and asserted them in case of error
during probe() or during driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: ehci-generic: replace printf() by error()
Patrice Chotard [Tue, 18 Jul 2017 09:57:09 +0000 (11:57 +0200)]
usb: host: ehci-generic: replace printf() by error()

this allows to get file, line and function location
of the current error message.

Signed-off-by: patrice chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: core: add ofnode_count_phandle_with_args()
Patrice Chotard [Tue, 18 Jul 2017 09:57:08 +0000 (11:57 +0200)]
dm: core: add ofnode_count_phandle_with_args()

This function is usefull to get phandle number contained
in a property list.
For example,  this allows to allocate the right amount
of memory to keep clock's reference contained into the
"clocks" property.

To implement it, either of_count_phandle_with_args() or
fdtdec_parse_phandle_with_args() are used respectively
for live tree and flat tree.
By passing index = -1, these 2 functions returns the
number of phandle contained into the property list.

Add also the dev_count_phandle_with_args() based on
ofnode_count_phandle_with_args()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoclk: add clk_release_all()
Patrice Chotard [Tue, 18 Jul 2017 09:57:07 +0000 (11:57 +0200)]
clk: add clk_release_all()

Add clk_release_all() method which Disable/Free an
array of clocks that has been previously requested by
clk_request/get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoreset: add reset_release_all()
Patrice Chotard [Tue, 18 Jul 2017 09:57:06 +0000 (11:57 +0200)]
reset: add reset_release_all()

Add reset_release_all() method which Assert/Free an
array of resets signal that has been previously successfully
requested by reset_get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoreset: add reset_request()
Patrice Chotard [Tue, 18 Jul 2017 09:57:05 +0000 (11:57 +0200)]
reset: add reset_request()

This is needed in error path to assert previously deasserted
reset by using a saved reset_ctl reference.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: xhci-dwc3: Add generic PHY support
Patrice Chotard [Tue, 18 Jul 2017 09:38:44 +0000 (11:38 +0200)]
usb: host: xhci-dwc3: Add generic PHY support

Add support of generic PHY framework support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: phy: add generic_phy_valid() method
Patrice Chotard [Tue, 18 Jul 2017 09:38:43 +0000 (11:38 +0200)]
drivers: phy: add generic_phy_valid() method

This allow to check if a PHY has been correctly
initialised and avoid to get access to phy struct.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
7 years agodrivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails
Patrice Chotard [Tue, 18 Jul 2017 09:38:42 +0000 (11:38 +0200)]
drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails

phy->dev need to be set to NULL in case of generic_phy_get_by_index()
fails. Then phy->dev can be used to check if the phy is valid

Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: xhci-dwc3: Add dual role mode support from DT
Patrice Chotard [Tue, 18 Jul 2017 09:38:41 +0000 (11:38 +0200)]
usb: host: xhci-dwc3: Add dual role mode support from DT

DWC3 dual role mode is selected using DT "dr_mode"
property. If not found, DWC3 controller is configured
in HOST mode by default

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: host: xhci-dwc3: Convert driver to DM
Patrice Chotard [Tue, 18 Jul 2017 09:38:40 +0000 (11:38 +0200)]
usb: host: xhci-dwc3: Convert driver to DM

Add Driver Model support with use of generic DT
compatible string "snps,dwc3"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agousb: add static to local symbols
Masahiro Yamada [Thu, 22 Jun 2017 07:35:14 +0000 (16:35 +0900)]
usb: add static to local symbols

Sparse reports "... was not declared. Should it be static?"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agorockchip: puma-rk3399: remove duplicate code (merge artifact)
Kever Yang [Thu, 27 Jul 2017 11:59:03 +0000 (19:59 +0800)]
rockchip: puma-rk3399: remove duplicate code (merge artifact)

A few lines (defines and declarations) had been duplicated when the
puma-rk3399 board was initially merged.  This removes the duplicates
and changes the style to use local constants instead of pasted
literals.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[fixed up commit-message & converted to use 'const u32':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: add u-boot specific dts for rk3036 sdk
Andy Yan [Mon, 24 Jul 2017 09:52:24 +0000 (17:52 +0800)]
rockchip: add u-boot specific dts for rk3036 sdk

Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: use puts instead of printf when back to bootrom
Andy Yan [Mon, 24 Jul 2017 09:52:01 +0000 (17:52 +0800)]
rockchip: use puts instead of printf when back to bootrom

printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: enable SPL_LIBGENERIC for rk3036 based boards
Andy Yan [Mon, 24 Jul 2017 09:51:30 +0000 (17:51 +0800)]
rockchip: enable SPL_LIBGENERIC for rk3036 based boards

function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
Andy Yan [Mon, 24 Jul 2017 09:51:07 +0000 (17:51 +0800)]
rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036

RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based...
Andy Yan [Mon, 24 Jul 2017 09:50:46 +0000 (17:50 +0800)]
rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board

RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agosandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before...
Andy Yan [Mon, 24 Jul 2017 09:49:59 +0000 (17:49 +0800)]
sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation

SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.

Signed-off-by: Andy Yan <andyshrk@gmail.com>
Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/sandbox/cpu/start.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agomicroblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Andy Yan [Mon, 24 Jul 2017 09:49:01 +0000 (17:49 +0800)]
microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agopowerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Andy Yan [Mon, 24 Jul 2017 09:47:27 +0000 (17:47 +0800)]
powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agomips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Andy Yan [Mon, 24 Jul 2017 09:45:27 +0000 (17:45 +0800)]
mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agospl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
Andy Yan [Mon, 24 Jul 2017 09:43:34 +0000 (17:43 +0800)]
spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: firefly: Add "usb start" to auto-start USB device
Leo Wen [Tue, 25 Jul 2017 12:47:47 +0000 (20:47 +0800)]
rockchip: firefly: Add "usb start" to auto-start USB device

Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't
need to input "usb start" in command line of u-boot console,it
can auto-start the USB device,after that usb keyboard can work.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: firefly: Set the environment variable 'usbkbd' to the stdin
Leo Wen [Tue, 25 Jul 2017 12:47:46 +0000 (20:47 +0800)]
rockchip: firefly: Set the environment variable 'usbkbd' to the stdin

Add the 'usbkbd' environment variable to the 'stdin', the contents of
the keyboard input can be auto-displayed on the serial terminal,so
you don't need to manually set the environment variable 'stdin'.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: firefly: Add some macros to enable the usb keyboard
Leo Wen [Tue, 25 Jul 2017 12:47:45 +0000 (20:47 +0800)]
rockchip: firefly: Add some macros to enable the usb keyboard

Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the
firefly-rk3288_defconfig,can support usb keyboard device when these four
macros are enabled.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
Philipp Tomsich [Wed, 26 Jul 2017 10:29:01 +0000 (12:29 +0200)]
rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig

SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk3288: Add support for drive-strength in PINCTRL
Romain Perier [Tue, 25 Jul 2017 07:28:22 +0000 (09:28 +0200)]
rockchip: rk3288: Add support for drive-strength in PINCTRL

Currently, drive-strenght to 12ma are described and supposed to be used
on RK3288. However, the pinctrl driver for this SoC only handles muxing
and pull up/pull down via PU/PD control registers. So complex IPs like
GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.

This commit adds support for handling drive-strength of 12ma, when it's
defined in the DT.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: use UUID for root partitions
Kever Yang [Tue, 25 Jul 2017 04:00:05 +0000 (12:00 +0800)]
rockchip: use UUID for root partitions

We use to use /dev/mmcbl0p7 as root partition, and pass it
to kernel by cmdline, but the mmc number in kernel in not
fixed, we need to change the bootargs to adapt it from time
to time.
We can use the UUID to fix it, the ID is from:
https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/
ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3
ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: rk3399-puma: put EFI partition entries at 2MB
Philipp Tomsich [Wed, 19 Jul 2017 12:32:23 +0000 (14:32 +0200)]
rockchip: dts: rk3399-puma: put EFI partition entries at 2MB

When creating a EFI/GUID partition map for the RK3399-Q7 through
U-Boot, the partition entries should be places at a 1MB offset from
the start of the device to give us space for the environment (at 16KB
on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the
image payload (at 256KB on SD/MMC devices).

This change sets this up through the u-boot,efi-partition-entries-offset
/config property in the RK3399-Q7 DTSI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL
Philipp Tomsich [Wed, 19 Jul 2017 12:32:22 +0000 (14:32 +0200)]
rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL

As our SPL stage can grow quite large (80KB+ are not unusual) on the
RK3399-Q7, the default setting for the environment location (in
include/configs/rockchip-common.h) can overlap our SPL.

This change finally makes use of the 'u-boot,mmc-env-offset' DTS
property to override the environment location and put it at 16KB into
the device, which is right before the SPL (located at 32KB).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: rk3399: remove unused fields from priv-structures
Philipp Tomsich [Tue, 11 Jul 2017 18:49:44 +0000 (20:49 +0200)]
rockchip: clk: rk3399: remove unused fields from priv-structures

This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: remove unused fields from rk3368_clk_priv
Philipp Tomsich [Tue, 11 Jul 2017 18:49:43 +0000 (20:49 +0200)]
rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv

The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc
Philipp Tomsich [Tue, 11 Jul 2017 18:59:45 +0000 (20:59 +0200)]
rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc

The clk driver for the RK3368 picked the wrong data structure's size
for its auto-alloc size: the size was calculated on the structure
representing the CRU hardware block instead of the priv structure.
As the CRU's register file is much larger than the driver's priv,
this did not cause any pain (except wasting memory).

Fix this by using the correct data structure's size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spl: make boot0 hook TPL safe
Philipp Tomsich [Tue, 11 Jul 2017 19:04:45 +0000 (21:04 +0200)]
rockchip: spl: make boot0 hook TPL safe

When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word).  Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction).  To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.

To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.

This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pwm: add mask for config setting
Kever Yang [Wed, 19 Jul 2017 11:54:23 +0000 (19:54 +0800)]
rockchip: pwm: add mask for config setting

Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.

Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agopower: pwm_regulator: remove redundant code
Kever Yang [Wed, 19 Jul 2017 11:54:22 +0000 (19:54 +0800)]
power: pwm_regulator: remove redundant code

The regulator_enable() should be called from upper layer like
regulators_enable_boot_on(), remove it from pwm regulator driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up typo in commit message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agopower: pwm_regulator: fix the pwm_set_config parameter order
Kever Yang [Wed, 19 Jul 2017 11:54:21 +0000 (19:54 +0800)]
power: pwm_regulator: fix the pwm_set_config parameter order

The rkpwm reg order has fixed by below patch:
e3ef41d rockchip: pwm: fix the register layout for the PWM controller

We need to correct the parameter order for pwm_set_config() to make
the pwm regulator works correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: correct vdd_log setting for firefly-rk3399
Kever Yang [Wed, 19 Jul 2017 11:54:20 +0000 (19:54 +0800)]
rockchip: dts: correct vdd_log setting for firefly-rk3399

Add regulator-init-microvolt for driver to init the regulator,
and the min output value is not 800000mV for the PWM2 io domain has
changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to
correct it with the value measured when PWM2 output HIGH.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: firefly using ddr3 1600
Kever Yang [Tue, 18 Jul 2017 13:55:08 +0000 (21:55 +0800)]
rockchip: dts: firefly using ddr3 1600

According to my test, some of firefly-rk3399 hang after dram init
when using ddr3-1333 config, while using ddr3-1600 config works
for all the board I have test.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: phycore: Add ID page of M24C32-D EEPROM
Wadim Egorov [Tue, 18 Jul 2017 09:53:10 +0000 (11:53 +0200)]
rockchip: phycore: Add ID page of M24C32-D EEPROM

The Identification Page (32 byte) is an additional page which can be written
and (later) permanently locked in Read-only mode.

phyCORE-RK3288 SoMs are using this page to describe the module variant.
This page also contains a MAC.

Our boards can be equipped with a different amount of EEPROMs. To make
this more transparent let's add an alias for the eeprom which stores the
module variant.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
Romain Perier [Mon, 17 Jul 2017 09:00:23 +0000 (11:00 +0200)]
rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC

This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).

Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk3288: Remove phy reset GPIO pull up
Romain Perier [Mon, 17 Jul 2017 09:00:22 +0000 (11:00 +0200)]
rockchip: rk3288: Remove phy reset GPIO pull up

We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.

This commit removes pull up for GPIO4B0.

Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: efuse: dm: change to use dev_read_addr
Philipp Tomsich [Fri, 14 Jul 2017 16:09:51 +0000 (18:09 +0200)]
rockchip: efuse: dm: change to use dev_read_addr

This changes the rockchip-efuse driver to use dev_read_addr instead of
devfdt_get_addr.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: timer: make register sizes explicit
Philipp Tomsich [Fri, 14 Jul 2017 16:09:25 +0000 (18:09 +0200)]
rockchip: timer: make register sizes explicit

We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: rk3229: add dwc2 node for fastboot
Meng Dongyang [Thu, 13 Jul 2017 02:59:54 +0000 (10:59 +0800)]
rockchip: dts: rk3229: add dwc2 node for fastboot

Add dwc2 node for fastboot to init dwc2 controller.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agoMerge git://git.denx.de/u-boot-uniphier
Tom Rini [Wed, 26 Jul 2017 15:29:25 +0000 (11:29 -0400)]
Merge git://git.denx.de/u-boot-uniphier

7 years agoMerge git://git.denx.de/u-boot-mips
Tom Rini [Wed, 26 Jul 2017 15:29:20 +0000 (11:29 -0400)]
Merge git://git.denx.de/u-boot-mips

7 years agoMAINTAINERS: Update maintainer for x86
Bin Meng [Sun, 23 Jul 2017 14:36:33 +0000 (07:36 -0700)]
MAINTAINERS: Update maintainer for x86

This adds myself as one of the x86 maintainers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agoFIT: List kernel_noload in the list of types
Tom Rini [Tue, 18 Jul 2017 18:14:19 +0000 (14:14 -0400)]
FIT: List kernel_noload in the list of types

In the source_file_format.txt file we talk about how to construct a
valid FIT image.  While it already says to look at the source for the
full list, add kernel_noload to the explicit list of types.  This is
arguably the most important type to use as most often we are including a
kernel that will run from wherever it is loaded into memory and execute.

This for example, allows you to create a single FIT image for Linux that
can be used on both OMAP and i.MX devices as the kernel will not need to
be moved in memory.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoram: stm32: add stm32h7 support
Patrice Chotard [Tue, 18 Jul 2017 15:37:29 +0000 (17:37 +0200)]
ram: stm32: add stm32h7 support

STM32F7 and H7 shared the same SDRAM control block.
On STM32H7 few control bits has been added.
The current driver need some minor adaptation as FMC block
enable/disable for H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
7 years agoARM: DTS: stm32: remove useless mr-nbanks property
Patrice Chotard [Tue, 18 Jul 2017 15:37:28 +0000 (17:37 +0200)]
ARM: DTS: stm32: remove useless mr-nbanks property

FMC driver is now able to discover the bank number by
parsing bank subnodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoram: stm32: add second SDRAM bank management
Patrice Chotard [Tue, 18 Jul 2017 15:37:27 +0000 (17:37 +0200)]
ram: stm32: add second SDRAM bank management

FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoram: stm32: replace fdtdec_get by ofnode calls
Patrice Chotard [Tue, 18 Jul 2017 15:37:26 +0000 (17:37 +0200)]
ram: stm32: replace fdtdec_get by ofnode calls

Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoram: stm32: get base address from DT
Patrice Chotard [Tue, 18 Jul 2017 15:37:25 +0000 (17:37 +0200)]
ram: stm32: get base address from DT

Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC

For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.

These additionals registers will be used later.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
7 years agoram: stm32: migrate fmc defines in driver file
Patrice Chotard [Tue, 18 Jul 2017 15:37:24 +0000 (17:37 +0200)]
ram: stm32: migrate fmc defines in driver file

Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c

This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoclk: stm32f7: remove clock_get()
Patrice Chotard [Tue, 18 Jul 2017 07:29:10 +0000 (09:29 +0200)]
clk: stm32f7: remove clock_get()

All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agospi: stm32_qspi: add clk_get_rate() support
Patrice Chotard [Tue, 18 Jul 2017 07:29:09 +0000 (09:29 +0200)]
spi: stm32_qspi: add clk_get_rate() support

Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoserial: stm32x7: add clk_get_rate() support
Patrice Chotard [Tue, 18 Jul 2017 07:29:08 +0000 (09:29 +0200)]
serial: stm32x7: add clk_get_rate() support

Replace proprietary clock_get() by clk_get_rate()
The stm32x7 serial driver is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoserial: stm32x7: migrate serial struct to driver
Patrice Chotard [Tue, 18 Jul 2017 07:29:07 +0000 (09:29 +0200)]
serial: stm32x7: migrate serial struct to driver

This allow to remove include/dm/platform_data/serial_stm32x7.h
which was included in the past by stm32x7 driver and by
stm32f746-disco.c board file.
Since patch 42bf5e7c27 "serial: stm32f7: add device tree support"
this file is no more needed in board file.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoclk: stm32f7: cleanup clocks unused definitions
Patrice Chotard [Tue, 18 Jul 2017 07:29:06 +0000 (09:29 +0200)]
clk: stm32f7: cleanup clocks unused definitions

clean the code by removing unused enums, structs and
defines related to clocks

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoclk: stm32f7: add clock .get_rate() callback
Patrice Chotard [Tue, 18 Jul 2017 07:29:05 +0000 (09:29 +0200)]
clk: stm32f7: add clock .get_rate() callback

Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoclk: stm32f7: get RCC base address from DT
Patrice Chotard [Tue, 18 Jul 2017 07:29:04 +0000 (09:29 +0200)]
clk: stm32f7: get RCC base address from DT

Retrieve RCC base address from DT, this will prepare
the ground for future STM32 SoCs support.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoclk: stm32f7: add static for configure_clocks()
Patrice Chotard [Tue, 18 Jul 2017 07:29:03 +0000 (09:29 +0200)]
clk: stm32f7: add static for configure_clocks()

Also remove its declaration from stm32.h which
is no more needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoARM: DTS: stm32: align DT clock declaration with kernel
Patrice Chotard [Tue, 18 Jul 2017 07:29:02 +0000 (09:29 +0200)]
ARM: DTS: stm32: align DT clock declaration with kernel

Use the same clocks macro than the one used by kernel DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agoarm: mach-keystone: Fixes issue with return values in inline assembly
Srinivas, Madan [Mon, 17 Jul 2017 18:02:02 +0000 (13:02 -0500)]
arm: mach-keystone: Fixes issue with return values in inline assembly

The inline assembly functions in mon.c assume that the caller will
check for the return value in r0 according to regular ARM calling
conventions.

However, this assumption breaks down if the compiler inlines the
functions. The caller is then under no obligation to use r0 for the
result.

To fix this disconnect, we must explicitly move the return value
from the smc/bl call to the variable that the function returns.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: ti: armv7: Fixes bug in fit_loadaddr for ramfs boot
Madan Srinivas [Mon, 17 Jul 2017 18:01:36 +0000 (13:01 -0500)]
configs: ti: armv7: Fixes bug in fit_loadaddr for ramfs boot

The load address of ramdisk, rdaddr is 0x88080000 and fit_loadaddr
is defined as 0x88000000. This leaves only 512Kbytes for the
fit image. When the FIT images are larger than this, it will
overwite the ramdisk and cause the boot to fail.

For eg, The K2 HS fit images are a few MB and end up overwriting
the ramdsk. This patch moves the fit_loadaddr to 0x87000000,
leaving a 16MB window for the fit image. This memory can be
reclaimed once the kernel starts running.

Signed-off-by: Madan Srinivas <madans@ti.com>
7 years agoarm: mach-keystone: Updates mon_install for K2G HS
Madan Srinivas [Mon, 17 Jul 2017 17:59:15 +0000 (12:59 -0500)]
arm: mach-keystone: Updates mon_install for K2G HS

On early K2 devices (eg. K2HK) the secure ROM code does not support
loading secure code to firewall protected memory, before decrypting,
authenticating and executing it.

To load the boot monitor on these devices, it is necessary to first
authenticate and run a copy loop from non-secure memory that copies
the boot monitor behind firewall protected memory, before decrypting
and executing it.

On K2G, the secure ROM does not allow secure code executing from
unprotected memory. Further, ROM first copies the signed and encrypted
image into firewall protected memory, then decrypts, authenticates
and executes it.

As a result of this, we cannot use the copy loop for K2G. The
mon_install has to be modified to pass the address the signed and
encrypted secure boot monitor image to the authentication API.

For backward compatibility with other K2 devices and K2G GP,
the mon_install API still supports a single argument. In this case
the second argument is set to 0 by u-boot and is ignored by ROM

Signed-off-by: Thanh Tran <thanh-tran@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: k2x_evm: Reorder default boot command
Andrew F. Davis [Mon, 17 Jul 2017 17:59:14 +0000 (12:59 -0500)]
configs: k2x_evm: Reorder default boot command

We first split the CONFIG_BOOTCOMMAND into its components to improve
readability. We then make the following order changes:

 - Run findfdt first so the fdt name can be used in envboot like OMAP
 - Install the boot monitor before running the PMMC so we can make any
     needed secure changes before PMMC, do this on both HS and non-HS
 - Move set_name_pmmc to just before get_pmmc_${boot}

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: k2x_evm: Adds environment variables for secure devices
Madan Srinivas [Mon, 17 Jul 2017 17:59:13 +0000 (12:59 -0500)]
configs: k2x_evm: Adds environment variables for secure devices

Updates the default u-boot environment variables to support secure
boot. On secure devices, a secure boot monitor (sec-bm) needs to
be installed by u-boot.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: k2x_evm: Adds FIT loading environment variables
Andrew F. Davis [Mon, 17 Jul 2017 17:59:12 +0000 (12:59 -0500)]
configs: k2x_evm: Adds FIT loading environment variables

Updates the default u-boot environment variables to support FIT image
loading.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoboard: ti: x15: Add support for beagle_X15 revC
Lokesh Vutla [Sun, 16 Jul 2017 14:29:19 +0000 (19:59 +0530)]
board: ti: x15: Add support for beagle_X15 revC

BeagleBoard X15 revC board is similar to X15 revB1 except
with a SR2.0 where revB1 uses a SR1.1. Add board detection
support for revC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoboard: ti: am57xx: Fix detection of board version
Lokesh Vutla [Sun, 16 Jul 2017 14:29:18 +0000 (19:59 +0530)]
board: ti: am57xx: Fix detection of board version

board_is*("rev", board_ti_get_rev()) uses strncmp() for
revison detection and assumes it is success if return value
is <= 0. This will fail in case of multiple versions, as
revb will be true for board_is_*revb() and board_is_*reva().
Fix it by looking for exact match of the string.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoodroid-c2: enable GPIO
Beniamino Galvani [Sun, 9 Jul 2017 22:30:05 +0000 (00:30 +0200)]
odroid-c2: enable GPIO

GPIOs are now supported on Meson GXBB, enable driver and command in
the config.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopinctrl: meson: add GPIO support
Beniamino Galvani [Sun, 9 Jul 2017 22:30:04 +0000 (00:30 +0200)]
pinctrl: meson: add GPIO support

This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
7 years agoarm: dts: meson: import dts files from Linux 4.12
Beniamino Galvani [Sun, 9 Jul 2017 22:30:03 +0000 (00:30 +0200)]
arm: dts: meson: import dts files from Linux 4.12

Import Amlogic Meson DTS files from Linux kernel version 4.12

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: uniphier: enable CONFIG_CMD_FS_GENERIC
Masahiro Yamada [Thu, 13 Jul 2017 11:32:18 +0000 (20:32 +0900)]
ARM: uniphier: enable CONFIG_CMD_FS_GENERIC

Enable file system commands such as load, ls.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: remove part number info from the boot log
Masahiro Yamada [Thu, 13 Jul 2017 11:32:17 +0000 (20:32 +0900)]
ARM: uniphier: remove part number info from the boot log

As is often the case with SoC development, slightly different
products (i.e. different part number) are developed based on the
same silicon-die.  Such fine grained information is unmaintainable.

Also, "SoC:" is a better fit that "CPU:".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>