]> git.sur5r.net Git - u-boot/log
u-boot
7 years agodm: mmc: omap_hsmmc: Add pre-reloc flag to the driver
Lokesh Vutla [Wed, 26 Apr 2017 08:07:06 +0000 (13:37 +0530)]
dm: mmc: omap_hsmmc: Add pre-reloc flag to the driver

For platforms that don't use device tree in SPL the only
way to mark this driver as 'required by relocation' is
with the DM_FLAG_PRE_RELOC flag. Add this to ensure that
the driver is bound.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agodm: mmc: omap_hsmmc: Update to support of-platdata
Lokesh Vutla [Wed, 26 Apr 2017 08:07:05 +0000 (13:37 +0530)]
dm: mmc: omap_hsmmc: Update to support of-platdata

This is to aid platforms that uses OF_PLATDATA.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoserial: omap: Support debug UART
Lokesh Vutla [Sat, 22 Apr 2017 10:27:25 +0000 (15:57 +0530)]
serial: omap: Support debug UART

Add debug UART functions to permit omap specific ns16550 to
provide an early debug UART. This is mostly in common with
DEBUG_UART_NS16550 except for Mode definition register which
is required for selecting UART mode(16x auto-baud or 13x mode).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoAdd 16-bit single register pin controller support
James Balean [Wed, 19 Apr 2017 02:06:35 +0000 (21:06 -0500)]
Add 16-bit single register pin controller support

Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.

Signed-off-by: James Balean <james@balean.com.au>
Cc: Felix Brack <fb@ltec.ch>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Felix Brack <fb@ltec.ch>
Tested-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot
B, Ravi [Tue, 18 Apr 2017 11:57:27 +0000 (17:27 +0530)]
boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot

In single stage bootmode or falcon boot mode, the SPL shall update the
device tree that we load with the normal fixups done via
arch_fixup_fdt(), when possible (ie we have enough information in this
restricted environment to be able to do that still).  This will include
for example updating them memory nodes.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
[trini: Reword commit message]

7 years agospl: fdt: support for fdt fixup for falcon boot
B, Ravi [Tue, 18 Apr 2017 11:57:26 +0000 (17:27 +0530)]
spl: fdt: support for fdt fixup for falcon boot

Adding support for fdt fixup to update the
memory node in device tree for falcon boot.

This is needed for single stage or falcon
bootmode, to pass memory configuration to
kernel through DT memory node.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
7 years agoqspi: dra7xx: enable qspi-boot for dra7x paltform
B, Ravi [Tue, 18 Apr 2017 11:57:25 +0000 (17:27 +0530)]
qspi: dra7xx: enable qspi-boot for dra7x paltform

Enables qspi boot configuration for dra7xx platform.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
7 years agoarch: arm: omap: Declare size of ddr very early
Lokesh Vutla [Tue, 18 Apr 2017 11:57:24 +0000 (17:27 +0530)]
arch: arm: omap: Declare size of ddr very early

Declare the size of ddr very early in spl, so that this can be
used to enable cache.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
7 years agospl: reorder the assignment of board info to global data
Lokesh Vutla [Tue, 18 Apr 2017 11:57:23 +0000 (17:27 +0530)]
spl: reorder the assignment of board info to global data

Move the assignment of board info to global data a bit early which is
safe,
so that ram details can be used to enable caches.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agospl: Makefile: include /config in the (reduced) FDT used by the SPL stage
Philipp Tomsich [Mon, 17 Apr 2017 15:45:13 +0000 (17:45 +0200)]
spl: Makefile: include /config in the (reduced) FDT used by the SPL stage

When OF control is enabled for the SPL stage, nodes are removed from
the DTB to reduce its size. While /chosen is kept, /config is removed.

There's no reason why /chosen should be kept over /config (and as we
would like to put properties into /config that control the SPL stage),
we add '/config' to the list of nodes to be retained for the SPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodoc: document /config/u-boot, spl-payload-offset property
Philipp Tomsich [Mon, 17 Apr 2017 15:45:12 +0000 (17:45 +0200)]
doc: document /config/u-boot, spl-payload-offset property

This adds documentation on the u-boot,spl-payload-offset property
(which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
the SPL stage, if present).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agospl: spi: override CONFIG_SYS_SPI_U_BOOT_OFFS via /config-property
Philipp Tomsich [Mon, 17 Apr 2017 15:45:11 +0000 (17:45 +0200)]
spl: spi: override CONFIG_SYS_SPI_U_BOOT_OFFS via /config-property

For the RK3399-Q7, we need some flexibility (depending on the feature
set we include in the SPL stage and how large our SPI flash is) in
positioning the SPL payload (i.e. the FIT image containing U-Boot, ATF
and the M0 payload) in our SPI flash.

To avoid having to deal with this through different U-Boot images, we
introduce a the '/config/u-boot,spl-payload-offset' property node
allow it to override the default setting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agoarm: Support cache invalidate
Simon Glass [Wed, 5 Apr 2017 23:53:18 +0000 (17:53 -0600)]
arm: Support cache invalidate

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: Correct signature for get_ticks()
Simon Glass [Wed, 5 Apr 2017 23:53:17 +0000 (17:53 -0600)]
arm: Correct signature for get_ticks()

This should be uint64_t to match its definition in common.h. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodisk: Return the partition number in part_get_info_by_name()
Alex Deymo [Sun, 2 Apr 2017 08:49:50 +0000 (01:49 -0700)]
disk: Return the partition number in part_get_info_by_name()

Similar to what blk_get_device_part_str() does, this patch makes
part_get_info_by_name() return the partition number in case of a match.
This is useful when the partition number is needed and not just the
descriptor.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoimage: Update include/android_image.h
Alex Deymo [Sun, 2 Apr 2017 08:49:47 +0000 (01:49 -0700)]
image: Update include/android_image.h

Update the Android image header format to the latest version published
in AOSP. The original code moved to a new repository, so this patch also
updates the reference to that path.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: gadget: avoid variable name clipping in cb_getvar
nicolas.le.bayon@st.com [Tue, 9 May 2017 15:58:36 +0000 (15:58 +0000)]
usb: gadget: avoid variable name clipping in cb_getvar

Hi,

A kind reminder to look at this patch (already reviewed by Marek and acked by Lukasz), and if possible to put it in the next pull list, or the one after is timing is too short.

Thanks in advance for your time

Best Regards
Nicolas

-----Original Message-----
From: Nicolas LE BAYON
Sent: mardi 25 avril 2017 10:18
To: Nicolas LE BAYON <nicolas.le.bayon@st.com>; u-boot@lists.denx.de; lukma@denx.de; marex@denx.de
Cc: nlebayon@gmail.com; Patrice CHOTARD <patrice.chotard@st.com>; Jean-philippe ROMAIN <jean-philippe.romain@st.com>
Subject: [U-Boot][PATCH v7] usb: gadget: avoid variable name clipping in cb_getvar

From: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Instead of using a fixed-size array to store variable name, preferring a dynamic allocation treats correctly all variable name lengths.
Variable names are growing through releases and features. By this way, name clipping is prevented.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
7 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Wed, 10 May 2017 21:40:11 +0000 (17:40 -0400)]
Merge git://git.denx.de/u-boot-rockchip

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 10 May 2017 19:50:21 +0000 (15:50 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

7 years agorockchip: dts: evb_rk3288: Add mipi display support
Eric Gao [Tue, 2 May 2017 10:32:45 +0000 (18:32 +0800)]
rockchip: dts: evb_rk3288: Add mipi display support

Add mipi dsi configuration for evb-rk3288 device tree.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3288: grf: Add grf define for mipi dsi
Eric Gao [Tue, 2 May 2017 10:32:43 +0000 (18:32 +0800)]
rockchip: rk3288: grf: Add grf define for mipi dsi

Add grf register define for rk3288 mipi dsi

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: defconfigs: Add mipi dsi support for rk3399 evb board
Eric Gao [Tue, 2 May 2017 10:23:57 +0000 (18:23 +0800)]
rockchip: defconfigs: Add mipi dsi support for rk3399 evb board

Add mipi dsi configs for rk3399 evb board

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: Add mipi dsi support for rk3399
Eric Gao [Tue, 2 May 2017 10:23:56 +0000 (18:23 +0800)]
rockchip: dts: Add mipi dsi support for rk3399

Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight
Eric Gao [Tue, 2 May 2017 10:23:55 +0000 (18:23 +0800)]
rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight

Enable pwm0 for display of rk3399 evb board. The PWM do not have decicated
interrupt number in dts and can not get periph_id by pinctrl framework. So
init them here.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: vop: Reserve enough space for mipi dispaly
Eric Gao [Tue, 2 May 2017 10:23:54 +0000 (18:23 +0800)]
rockchip: video: vop: Reserve enough space for mipi dispaly

plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: vop: Set different bitwidth for different display mode
Eric Gao [Tue, 2 May 2017 10:23:53 +0000 (18:23 +0800)]
rockchip: video: vop: Set different bitwidth for different display mode

Because the bitwidth is different for different display mode, so we need
to set them according to demand.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: vop: Add mipi display mode for rk3399
Eric Gao [Tue, 2 May 2017 10:23:52 +0000 (18:23 +0800)]
rockchip: video: vop: Add mipi display mode for rk3399

Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: vop: Fix rk_display_init() return error
Eric Gao [Tue, 2 May 2017 10:23:51 +0000 (18:23 +0800)]
rockchip: video: vop: Fix rk_display_init() return error

It's caused by the difference of clk_set_rate function implement between
rk3288 andd rk3399.

clk_set_rate() of rk3288 return 0 in normal condition.
clk_set_rate() of rk3399 return input parameter in normal condition.

So check clk_set_rate's return value by IS_ERR_VALUE.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
7 years agorockchip: video: Add mipi driver support for rockchip soc
Eric Gao [Tue, 2 May 2017 10:23:50 +0000 (18:23 +0800)]
rockchip: video: Add mipi driver support for rockchip soc

Add basic driver for mipi display on rockchip soc platform.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: include: grf: Add GRF register declaration for mipi dsi
Eric Gao [Tue, 2 May 2017 10:23:49 +0000 (18:23 +0800)]
rockchip: include: grf: Add GRF register declaration for mipi dsi

Add GRF register declaration for mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agopower: rk808: rename to rk8xx
Jacob Chen [Tue, 2 May 2017 06:54:52 +0000 (14:54 +0800)]
power: rk808: rename to rk8xx

Since this driver can be used for rk8xx series pmic,
let's rename rk808 to rk8xx, to make it clear.

Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./`

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
7 years agopower: regulator: rk808: add rk818 support
Jacob Chen [Tue, 2 May 2017 06:54:51 +0000 (14:54 +0800)]
power: regulator: rk808: add rk818 support

Add support for the rk818 regulator. The regulator module consists
of 4 DCDCs, 9 LDOs, 1 switch and 1 BOOST converter which is used to
power OTG and HDMI5V.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopower: regulator: rk808: replace vsel_bits with vsel_mask
Jacob Chen [Tue, 2 May 2017 06:54:50 +0000 (14:54 +0800)]
power: regulator: rk808: replace vsel_bits with vsel_mask

Using mask is more flexible than bits.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopower: pmic: rk808: add RK818 support
Jacob Chen [Tue, 2 May 2017 06:54:49 +0000 (14:54 +0800)]
power: pmic: rk808: add RK818 support

The RK818 chip is a Power Management IC (PMIC) for multimedia and handheld
devices.

For boards use rk818, the input current should be set in the early stage, before
ddr initialization.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
7 years agopower: pmic: append rk818 regs to rk808
Jacob Chen [Tue, 2 May 2017 06:54:48 +0000 (14:54 +0800)]
power: pmic: append rk818 regs to rk808

Both RK808 and RK818 chips are using a similar register map,
so we can reuse them.

I have also add reg prefix to exist registers, to keep them same style.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: tinker: set ethaddr in late init
Jonas Karlman [Sat, 22 Apr 2017 08:57:54 +0000 (08:57 +0000)]
rockchip: tinker: set ethaddr in late init

Set ethernet mac address in late init for Tinker Board,
prevents getting a random mac address each boot.

Read mac address from eeprom, first 6 bytes from m24c08@50.
Same as /etc/init.d/rockchip.sh on Tinker OS.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoi2c_eeprom: add read and write functions
Jonas Karlman [Sat, 22 Apr 2017 08:57:41 +0000 (08:57 +0000)]
i2c_eeprom: add read and write functions

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add support for the HDMI I2C pins
Philipp Tomsich [Fri, 28 Apr 2017 16:33:58 +0000 (18:33 +0200)]
rockchip: pinctrl: rk3399: add support for the HDMI I2C pins

To add HDMI support for the RK3399, this commit provides the needed
pinctrl functionality to configure the HDMI I2C pins (used for reading
the screen's EDID).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: allow requests for HDMI clocks
Philipp Tomsich [Fri, 28 Apr 2017 16:33:57 +0000 (18:33 +0200)]
rockchip: clk: rk3399: allow requests for HDMI clocks

This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.

As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: ARM64: puma-rk3399: get DRAM size from DMC init
Philipp Tomsich [Fri, 28 Apr 2017 15:31:44 +0000 (17:31 +0200)]
rockchip: ARM64: puma-rk3399: get DRAM size from DMC init

With the RK3399 DRAM controller (DMC) driver providing all the
infrastructure, retrieve the DRAM size from the DMC init in the
board-specific code (instead of hard-coding) for the RK3399-Q7 (Puma).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS
Philipp Tomsich [Fri, 28 Apr 2017 15:11:55 +0000 (17:11 +0200)]
rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS

The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
To allow us to add a efuse-driver (and more importantly, to allow
probes of such a driver to succeed), we need need to accept requests
for PCLK_EFUSE1024NS and return a non-error result.

As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
implement any logic to manage this clock gate and simply assume that
the reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: add defconfig for firefly-rk3399
Kever Yang [Mon, 24 Apr 2017 03:58:30 +0000 (11:58 +0800)]
rockchip: add defconfig for firefly-rk3399

The file is from evb-rk3399_defconfig with changes:
- use rk3399-firefly dtb
- re-order by make savedefconfig

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: sandbox: pwm: add test for pwm_set_invert()
Kever Yang [Mon, 24 Apr 2017 02:27:52 +0000 (10:27 +0800)]
dm: sandbox: pwm: add test for pwm_set_invert()

Add test case for new interface set_invert().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix typo in subject and build error in sandbox_pwm_set_invert():
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodoc: dtbinding: add pwm binding file
Kever Yang [Mon, 24 Apr 2017 02:27:51 +0000 (10:27 +0800)]
doc: dtbinding: add pwm binding file

This is a copy from kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pwm: implement pwm_set_invert()
Kever Yang [Mon, 24 Apr 2017 02:27:50 +0000 (10:27 +0800)]
rockchip: pwm: implement pwm_set_invert()

Rockchip pwm need to init polarity, implement pwm_set_invert()
to do it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agopower: regulator: pwm: support pwm polarity setting
Kever Yang [Mon, 24 Apr 2017 02:27:49 +0000 (10:27 +0800)]
power: regulator: pwm: support pwm polarity setting

The latest kernel PWM drivers enable the polarity settings. When system
run from U-Boot to kerenl, if there are differences in polarity set or
duty cycle, the PMW will re-init:
  close -> set polarity and duty cycle -> enable the PWM.
The power supply controled by pwm regulator may have voltage shaking,
which lead to the system not stable.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: add rk3399-firefly dts
Kever Yang [Wed, 19 Apr 2017 10:17:32 +0000 (18:17 +0800)]
rockchip: dts: add rk3399-firefly dts

Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/

This patch add basic node for the board and make it able to bring
up.

Peripheral/interfaces on board:
- usb hub which connect to ehci controller;
- UART2 debug
- eMMC
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: rk3399: sync with kernel dts
Kever Yang [Wed, 19 Apr 2017 10:17:31 +0000 (18:17 +0800)]
rockchip: dts: rk3399: sync with kernel dts

The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodtoc: Handle nodes with phandles that depend on the same
Simon Glass [Sun, 23 Apr 2017 00:42:22 +0000 (18:42 -0600)]
dtoc: Handle nodes with phandles that depend on the same

At present dtoc assumes that nodes which are phandles do not themselves
reference other phandle nodes. Unfortunately this is not necessarilly
true. As a result we can currently output C code which does not compile
because a node declaration can be referenced before it is declared.

Adjust the code to explicitly output all phandle nodes needed by node
before the node itself is output.

This fixes building with the latest rk3399-firefly.dts from Linux, which
has reordered the nodes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agodtoc: Move the output code into its own function
Simon Glass [Sun, 23 Apr 2017 00:42:21 +0000 (18:42 -0600)]
dtoc: Move the output code into its own function

The code to generate the tables is quite long. Move the node-output code
into its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: mmc: handle deprecation of 'clock-freq-min-max'
Philipp Tomsich [Tue, 25 Apr 2017 07:52:07 +0000 (09:52 +0200)]
rockchip: mmc: handle deprecation of 'clock-freq-min-max'

The 'clock-freq-min-max' property was deprecated in the upstream
(i.e. Linux) DTS bindings in favor of the 'max-frequency' property.

With the latest RK3399 DTSI does no longer include the deprecated
property and the rockchip_dw_mmc driver requiring it to be present,
the driver doesn't bind to the node in the RK3399 DTSI any longer
(thus breaking access to the SD card on the RK3399-Q7 board).

To fix this, we implement a similar logic as in the Linux driver: if
the deprecated property is present, we issue a warning (if DEBUG is
enabled); if it is missing, we require 'max-frequency' to be set and
use it to create a min/max value-pair.

See https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b
for the deprecation/matching change in Linux.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS
Philipp Tomsich [Tue, 25 Apr 2017 07:52:06 +0000 (09:52 +0200)]
rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS

The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.

With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: reserve memory for rk3399 ATF data
Kever Yang [Thu, 20 Apr 2017 09:03:46 +0000 (17:03 +0800)]
rockchip: reserve memory for rk3399 ATF data

There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;

SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.

More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add gmac io strength support
Kever Yang [Thu, 20 Apr 2017 08:15:34 +0000 (16:15 +0800)]
rockchip: pinctrl: rk3399: add gmac io strength support

GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: evb-rk3399: add gmac support
Kever Yang [Mon, 1 May 2017 22:16:01 +0000 (16:16 -0600)]
rockchip: dts: evb-rk3399: add gmac support

Enable gmac for evb-rk3399.

Change-Id: I85e35667e08e22e38577e63eb0e65731fc9c69b6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3399: use actual dram size
Kever Yang [Wed, 19 Apr 2017 08:01:14 +0000 (16:01 +0800)]
rockchip: rk3399: use actual dram size

Since our sdram driver is ready, we can use the actual size
instead of hard code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: enable debug uart
Eddie Cai [Tue, 18 Apr 2017 11:17:27 +0000 (19:17 +0800)]
rockchip: enable debug uart

enable debug uart for rk3288 and print something to let people know
where we are

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: evb-rk3399: correct pwm3 polarity
Kever Yang [Tue, 18 Apr 2017 09:06:21 +0000 (17:06 +0800)]
rockchip: dts: evb-rk3399: correct pwm3 polarity

The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it work correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma
Philipp Tomsich [Mon, 17 Apr 2017 15:50:38 +0000 (17:50 +0200)]
rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma

With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop blank line at end of file:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi
Philipp Tomsich [Mon, 17 Apr 2017 15:50:37 +0000 (17:50 +0200)]
rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi

The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
left-over comments in them. This change cleans the file up.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: remove placeholder functions from rkimage
Philipp Tomsich [Mon, 17 Apr 2017 15:48:06 +0000 (17:48 +0200)]
rockchip: mkimage: remove placeholder functions from rkimage

The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.

This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool.  This is in
fact better than having verify just return 0 (which previously broke
dumpimage, as dumpimage assumed that we had handled the image and did
not continue to probe further).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: play nice with dumpimage
Philipp Tomsich [Mon, 17 Apr 2017 15:48:05 +0000 (17:48 +0200)]
rockchip: mkimage: play nice with dumpimage

Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: clarify header0 initialisation
Philipp Tomsich [Mon, 17 Apr 2017 15:48:04 +0000 (17:48 +0200)]
rockchip: mkimage: clarify header0 initialisation

This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.

As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rksd: pad SD/MMC images to a full blocksize
Philipp Tomsich [Mon, 17 Apr 2017 15:48:03 +0000 (17:48 +0200)]
rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: Update comments for header size
Philipp Tomsich [Mon, 17 Apr 2017 15:48:02 +0000 (17:48 +0200)]
rockchip: mkimage: Update comments for header size

The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).

This change brings the comment back in-sync with what the code is
doing.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images
Philipp Tomsich [Mon, 17 Apr 2017 15:48:01 +0000 (17:48 +0200)]
rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images

In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been.  This change rewrites the code (using new, common functions
in rkcommon.c) and adds verbose in-line comments to ensure that we
won't fall into the same pit in the future...

Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rkspi: include the header sector in the SPI size calculation
Philipp Tomsich [Mon, 17 Apr 2017 15:48:00 +0000 (17:48 +0200)]
rockchip: mkimage: rkspi: include the header sector in the SPI size calculation

Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.

This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
Philipp Tomsich [Thu, 20 Apr 2017 20:05:55 +0000 (22:05 +0200)]
rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL

To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: enable support for the rk_spi driver for the RK3399
Jakob Unterwurzacher [Thu, 20 Apr 2017 20:05:54 +0000 (22:05 +0200)]
rockchip: spi: enable support for the rk_spi driver for the RK3399

The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add support for the SPI5 controller
Philipp Tomsich [Thu, 20 Apr 2017 20:05:53 +0000 (22:05 +0200)]
rockchip: pinctrl: rk3399: add support for the SPI5 controller

This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
     in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
         PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
     through SPI5 to the appropriate pin-config
     function; implements the pin-configuration
     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
Philipp Tomsich [Thu, 20 Apr 2017 20:05:52 +0000 (22:05 +0200)]
rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting

The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator.  This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
   bitwise-AND generates rather random-looking (wildly varying)
   actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
   higher baudrate' with the actual error increasing as the dividers
   become very small. E.g., with a 99MHz input clock, a request
   for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
   (which amounts to a 23.75% error)... for a 34 MBit request this
   would be an actual outbout of 49.5 Mbit (i.e. a 45% error).

This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
   requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
   represented), the lowest representable baudrate is chosen.

Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: spi: rk_spi: dynamically select an module input rate
Philipp Tomsich [Thu, 20 Apr 2017 20:05:51 +0000 (22:05 +0200)]
rockchip: spi: rk_spi: dynamically select an module input rate

The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.

To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.

This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.

This replaces
  "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
  "rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
Philipp Tomsich [Thu, 20 Apr 2017 20:05:50 +0000 (22:05 +0200)]
rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate

For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
  1. calculates 'src_div := src_freq / target_freq'
  2. stores 'src_div - 1' into the register (the actual divider applied
     in hardware is biased by adding 1)
  3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
     expects the (decremented) divider from the hardware-register and
     implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')

This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.

To fix, we have two options:
 * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
   make for a particularily nice read
 * we simply call the i2c/spi_get_rate function (introducing additional
   overhead for the additional register-read), which reads the divider
   from the register and then passes it through the DIV_RATE macro

Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
Philipp Tomsich [Thu, 20 Apr 2017 20:05:49 +0000 (22:05 +0200)]
rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Makefile: Modify Makefile for rockchip video driver
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:24 +0000 (22:24 +0800)]
rockchip: video: Makefile: Modify Makefile for rockchip video driver

Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Kconfig: Add Kconfig for rockchip video driver
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:23 +0000 (22:24 +0800)]
rockchip: video: Kconfig: Add Kconfig for rockchip video driver

1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop indenting in Kconfig:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3399: correct memory region
Kever Yang [Mon, 17 Apr 2017 08:42:44 +0000 (16:42 +0800)]
rockchip: rk3399: correct memory region

RK3399 device memory region is 0xf8000000~0xffffffff.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
Xu Ziyuan [Sun, 16 Apr 2017 09:44:46 +0000 (17:44 +0800)]
rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:45 +0000 (17:44 +0800)]
rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:44 +0000 (17:44 +0800)]
rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:43 +0000 (17:44 +0800)]
rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agommc: dw_mmc: rockchip: select proper card clock
Xu Ziyuan [Sun, 16 Apr 2017 09:44:42 +0000 (17:44 +0800)]
mmc: dw_mmc: rockchip: select proper card clock

As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agomkimage: rockchip: add support for rk3328
Kever Yang [Fri, 14 Apr 2017 06:55:05 +0000 (14:55 +0800)]
mkimage: rockchip: add support for rk3328

Add support for rk3328 package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3399: use regulators_enable_boot_on() to init regulator
Kever Yang [Wed, 12 Apr 2017 04:00:06 +0000 (12:00 +0800)]
rockchip: rk3399: use regulators_enable_boot_on() to init regulator

Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:39 +0000 (20:28 +0200)]
mips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
7 years agomips: bmips: add bcm6328-power-domain driver support for BCM63268
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:38 +0000 (20:28 +0200)]
mips: bmips: add bcm6328-power-domain driver support for BCM63268

This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
7 years agomips: bmips: add bcm6328-power-domain driver support for BCM6328
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:37 +0000 (20:28 +0200)]
mips: bmips: add bcm6328-power-domain driver support for BCM6328

This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
7 years agodm: power: domain: add BCM6328 power domain driver
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:36 +0000 (20:28 +0200)]
dm: power: domain: add BCM6328 power domain driver

This allows controlling MISC IDDQ register on BCM6328 SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
7 years agomips: bmips: enable bcm6345-reset driver for all BMIPS boards
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:25 +0000 (15:10 +0200)]
mips: bmips: enable bcm6345-reset driver for all BMIPS boards

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-rst driver support for BCM63268
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:24 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM63268

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-rst driver support for BCM6328
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:23 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM6328

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-rst driver support for BCM6358
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:22 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM6358

This driver can control up to 32 resets.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: reset: add BCM6345 reset driver
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:21 +0000 (15:10 +0200)]
dm: reset: add BCM6345 reset driver

This is a simplified version of linux/arch/mips/bcm63xx/reset.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: enable bcm6345-clk driver for all BMIPS boards
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:05 +0000 (20:13 +0200)]
mips: bmips: enable bcm6345-clk driver for all BMIPS boards

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-clk driver support for BCM63268
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:04 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM63268

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-clk driver support for BCM6328
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:03 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM6328

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6345-clk driver support for BCM6358
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:02 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM6358

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: clk: add BCM6345 clock driver
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:01 +0000 (20:13 +0200)]
dm: clk: add BCM6345 clock driver

This is a simplified version of linux/arch/mips/bcm63xx/clk.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add NeufBox 4 (Sercomm) board
Álvaro Fernández Rojas [Sun, 7 May 2017 18:11:32 +0000 (20:11 +0200)]
mips: bmips: add NeufBox 4 (Sercomm) board

This serves as an example for bcm6358-leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomips: bmips: add bcm6358-led driver support for BCM6358
Álvaro Fernández Rojas [Sun, 7 May 2017 18:11:31 +0000 (20:11 +0200)]
mips: bmips: add bcm6358-led driver support for BCM6358

This driver can control up to 32 serial leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>