]> git.sur5r.net Git - u-boot/log
u-boot
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Wed, 29 Jul 2015 22:58:39 +0000 (18:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

9 years agoT210: Add support for 64-bit T210-based P2571 board
Tom Warren [Thu, 12 Feb 2015 22:01:49 +0000 (15:01 -0700)]
T210: Add support for 64-bit T210-based P2571 board

Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoP2571: dts: Add DT file for Tegra210 P2571 board
Tom Warren [Fri, 13 Feb 2015 21:39:53 +0000 (14:39 -0700)]
P2571: dts: Add DT file for Tegra210 P2571 board

Based on T124 Venice2. SDMMC1 is SD-card slot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: Tegra210: Add support to common Tegra source/config files
Tom Warren [Wed, 4 Mar 2015 23:36:00 +0000 (16:36 -0700)]
ARM: Tegra210: Add support to common Tegra source/config files

Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: Tegra210: Add SoC code/include files for T210
Tom Warren [Mon, 2 Feb 2015 20:22:29 +0000 (13:22 -0700)]
ARM: Tegra210: Add SoC code/include files for T210

All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoTegra: Rework KConfig options to allow 64-bit builds (T210)
Tom Warren [Fri, 17 Jul 2015 15:12:51 +0000 (08:12 -0700)]
Tegra: Rework KConfig options to allow 64-bit builds (T210)

Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.

T210 will be 64-bit only (no SPL) and will require a 32-bit
AVP/BPMP loader.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoTegra210: Fix 64-bit build warning about save_boot_params_ret()
Tom Warren [Wed, 8 Jul 2015 15:05:35 +0000 (08:05 -0700)]
Tegra210: Fix 64-bit build warning about save_boot_params_ret()

Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Use architected timer on ARMv8
Thierry Reding [Tue, 28 Jul 2015 09:35:54 +0000 (11:35 +0200)]
ARM: tegra: Use architected timer on ARMv8

ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Initialize timer earlier
Thierry Reding [Tue, 28 Jul 2015 09:35:53 +0000 (11:35 +0200)]
ARM: tegra: Initialize timer earlier

A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
resetting the debug UART, which happens very early. Make sure that
arch_timer_init() is called before that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Disable SPL and non-cached memory on 64-bit
Thierry Reding [Mon, 27 Jul 2015 17:45:26 +0000 (11:45 -0600)]
ARM: tegra: Disable SPL and non-cached memory on 64-bit

For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: tegra: Use standard cache enable for 64-bit
Thierry Reding [Mon, 27 Jul 2015 17:45:25 +0000 (11:45 -0600)]
ARM: tegra: Use standard cache enable for 64-bit

On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs
Thierry Reding [Mon, 27 Jul 2015 17:45:24 +0000 (11:45 -0600)]
ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs

Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agofdt: Fix fdtdec_get_addr_size() for 64-bit
Thierry Reding [Thu, 23 Jul 2015 16:51:30 +0000 (10:51 -0600)]
fdt: Fix fdtdec_get_addr_size() for 64-bit

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoarmv8/cache: Fix page table creation
Thierry Reding [Wed, 22 Jul 2015 23:10:11 +0000 (17:10 -0600)]
armv8/cache: Fix page table creation

While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.

Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.

swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agopatman: add distutils based installer
Chris Packham [Wed, 22 Jul 2015 09:21:46 +0000 (21:21 +1200)]
patman: add distutils based installer

To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with

  cd u-boot/tools/patman && python setup.py install

There are also the usual distutils options for creating source/binary
distributions of patman.

Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Reserve PCIe ECAM address range in the E820 table
Bin Meng [Wed, 22 Jul 2015 08:21:15 +0000 (01:21 -0700)]
x86: Reserve PCIe ECAM address range in the E820 table

We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Turn on PCIe ECAM address range decoding on Q35
Bin Meng [Wed, 22 Jul 2015 08:21:14 +0000 (01:21 -0700)]
x86: qemu: Turn on PCIe ECAM address range decoding on Q35

Turn on PCIe ECAM address range decoding on Q35.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Enable writing MP table
Bin Meng [Wed, 22 Jul 2015 08:21:13 +0000 (01:21 -0700)]
x86: qemu: Enable writing MP table

Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow cpu-x86 driver to be probed for UP
Bin Meng [Wed, 22 Jul 2015 08:21:12 +0000 (01:21 -0700)]
x86: Allow cpu-x86 driver to be probed for UP

Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Enable I/O APIC chip select on PIIX3
Bin Meng [Wed, 22 Jul 2015 08:21:11 +0000 (01:21 -0700)]
x86: qemu: Enable I/O APIC chip select on PIIX3

The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: mpspec: Move writing ISA interrupt entry after PCI
Bin Meng [Wed, 22 Jul 2015 08:21:10 +0000 (01:21 -0700)]
x86: mpspec: Move writing ISA interrupt entry after PCI

On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
Bin Meng [Wed, 22 Jul 2015 08:21:09 +0000 (01:21 -0700)]
x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC

Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Convert to use driver model pci on queensbay/crownbay
Bin Meng [Sat, 18 Jul 2015 16:20:07 +0000 (00:20 +0800)]
x86: Convert to use driver model pci on queensbay/crownbay

Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Support bridge device configuration correctly
Bin Meng [Sat, 18 Jul 2015 16:20:06 +0000 (00:20 +0800)]
dm: pci: Support bridge device configuration correctly

Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.

The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.

For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.

To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Pass only device/function to pci_bus_find_devfn()
Bin Meng [Sat, 18 Jul 2015 16:20:05 +0000 (00:20 +0800)]
dm: pci: Pass only device/function to pci_bus_find_devfn()

In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Use complete bdf in all pci config read/write routines
Bin Meng [Sat, 18 Jul 2015 16:20:04 +0000 (00:20 +0800)]
dm: pci: Use complete bdf in all pci config read/write routines

Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.

To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Correct primary/secondary/subordinate bus number assignment
Bin Meng [Sat, 18 Jul 2015 16:20:03 +0000 (00:20 +0800)]
dm: pci: Correct primary/secondary/subordinate bus number assignment

In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agoFix incorrect comments in linker_lists.h
Bin Meng [Sat, 18 Jul 2015 16:20:02 +0000 (00:20 +0800)]
Fix incorrect comments in linker_lists.h

This corrects several typos in the comment block as well as some
indentions and nits in the linker_lists.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agobuildman: Correct '--fetch-arch' command documentation
Bin Meng [Fri, 17 Jul 2015 02:43:46 +0000 (19:43 -0700)]
buildman: Correct '--fetch-arch' command documentation

The doc wrongly put sandbox in the '--fetch-arch' command. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Do not assign irq 0 to pci device
Bin Meng [Wed, 15 Jul 2015 08:23:41 +0000 (16:23 +0800)]
x86: pci: Do not assign irq 0 to pci device

IRQ 0 is reserved and should not be assigned to pci device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Assign pci irqs to all functions
Bin Meng [Wed, 15 Jul 2015 08:23:40 +0000 (16:23 +0800)]
x86: pci: Assign pci irqs to all functions

We need walk through all functions within a PCI device and assign
their IRQs accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable DM RTC support for all x86 boards
Bin Meng [Wed, 15 Jul 2015 08:23:39 +0000 (16:23 +0800)]
x86: Enable DM RTC support for all x86 boards

Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')

9 years agox86: Change pci option rom area MTRR setting to cacheable
Bin Meng [Wed, 15 Jul 2015 08:23:38 +0000 (16:23 +0800)]
x86: Change pci option rom area MTRR setting to cacheable

Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Simplify architecture defined exception handling in irq_llsr()
Bin Meng [Fri, 10 Jul 2015 02:51:23 +0000 (10:51 +0800)]
x86: Simplify architecture defined exception handling in irq_llsr()

Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.

With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Display correct CS/EIP/EFLAGS when there is an error code
Bin Meng [Fri, 10 Jul 2015 02:38:32 +0000 (10:38 +0800)]
x86: Display correct CS/EIP/EFLAGS when there is an error code

Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Tue, 28 Jul 2015 15:31:21 +0000 (11:31 -0400)]
Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

9 years agocmd_mp: Add support for showing all CPU status by one command
Michal Simek [Mon, 22 Jun 2015 08:46:40 +0000 (10:46 +0200)]
cmd_mp: Add support for showing all CPU status by one command

Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agospi: zynq_spi: Simplify debug macro
Michal Simek [Tue, 21 Jul 2015 05:54:11 +0000 (07:54 +0200)]
spi: zynq_spi: Simplify debug macro

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynq: Fix typo in Makefile about custom ps7_init file
Michal Simek [Tue, 21 Jul 2015 09:05:31 +0000 (11:05 +0200)]
zynq: Fix typo in Makefile about custom ps7_init file

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agonet: gem: Extend timeout value
Michal Simek [Tue, 16 Oct 2012 15:37:11 +0000 (17:37 +0200)]
net: gem: Extend timeout value

Extend time for MDIO. (Because of zed board)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Show EL level where U-Boot runs
Michal Simek [Mon, 22 Jun 2015 12:31:06 +0000 (14:31 +0200)]
zynqmp: Show EL level where U-Boot runs

Add one more print to make clear which EL level U-Boot runs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynqmp: Wire up SATA for the board
Michal Simek [Thu, 23 Jul 2015 11:27:40 +0000 (13:27 +0200)]
ARM: zynqmp: Wire up SATA for the board

Enable SATA for the ZynqMP targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynqmp: Wire up ethernet controllers
Michal Simek [Thu, 23 Jul 2015 10:03:55 +0000 (12:03 +0200)]
ARM: zynqmp: Wire up ethernet controllers

Wire up ethernet controllers and enable MII and BOOTP options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: Add support for zc770-xm011
Michal Simek [Wed, 22 Jul 2015 09:39:04 +0000 (11:39 +0200)]
ARM: zynq: Add support for zc770-xm011

Add xm011 DTS file and related configs and configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Update zc770 dtses
Michal Simek [Wed, 22 Jul 2015 09:36:32 +0000 (11:36 +0200)]
ARM: zynq: DT: Update zc770 dtses

Platform DTSes are missing content needed for platform to be able to use
OF binding and DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys
Michal Simek [Wed, 22 Jul 2015 09:41:11 +0000 (11:41 +0200)]
ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys

Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.

Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add missing interrupt for L2 pl310
Michal Simek [Wed, 22 Jul 2015 09:26:08 +0000 (11:26 +0200)]
ARM: zynq: DT: Add missing interrupt for L2 pl310

Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Get rid of ps-clk-frequency
Michal Simek [Wed, 22 Jul 2015 09:20:54 +0000 (11:20 +0200)]
ARM: zynq: DT: Get rid of ps-clk-frequency

ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Update years in copyright
Michal Simek [Wed, 22 Jul 2015 09:18:43 +0000 (11:18 +0200)]
ARM: zynq: DT: Update years in copyright

Trivial.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel
Michal Simek [Wed, 22 Jul 2015 09:12:10 +0000 (11:12 +0200)]
ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel

Syncup with the latest DT from the Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add reference to bus node
Michal Simek [Wed, 22 Jul 2015 09:08:40 +0000 (11:08 +0200)]
ARM: zynq: DT: Add reference to bus node

For adding OCM memory in platform DTS is necessary to have reference to
amba bus.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add pinctrl node
Michal Simek [Wed, 22 Jul 2015 09:07:49 +0000 (11:07 +0200)]
ARM: zynq: DT: Add pinctrl node

Add pinctrl node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Cleanup address-cells and size-cells
Michal Simek [Wed, 22 Jul 2015 09:03:36 +0000 (11:03 +0200)]
ARM: zynq: DT: Cleanup address-cells and size-cells

Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Clean up timer device tree nodes
Michal Simek [Wed, 22 Jul 2015 08:57:51 +0000 (10:57 +0200)]
ARM: zynq: DT: Clean up timer device tree nodes

Separate IRQ cells from each other for easier reading.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Use the zynq binding with macb
Michal Simek [Wed, 22 Jul 2015 08:51:16 +0000 (10:51 +0200)]
ARM: zynq: DT: Use the zynq binding with macb

Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Fix GEM register area size
Michal Simek [Wed, 22 Jul 2015 08:50:02 +0000 (10:50 +0200)]
ARM: zynq: DT: Fix GEM register area size

The size of the GEM's register area is only 0x1000 bytes.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agospi: Fix zynq SPI binding
Michal Simek [Wed, 22 Jul 2015 08:47:33 +0000 (10:47 +0200)]
spi: Fix zynq SPI binding

Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Remove 222 MHz OPP
Michal Simek [Wed, 22 Jul 2015 08:42:51 +0000 (10:42 +0200)]
ARM: zynq: DT: Remove 222 MHz OPP

Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Migrate UART to Cadence binding
Michal Simek [Wed, 22 Jul 2015 08:40:51 +0000 (10:40 +0200)]
ARM: zynq: DT: Migrate UART to Cadence binding

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add a fixed regulator for CPU voltage
Michal Simek [Wed, 22 Jul 2015 08:38:45 +0000 (10:38 +0200)]
ARM: zynq: DT: Add a fixed regulator for CPU voltage

To silence the warning
   cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Add missing nodes to DTSI
Michal Simek [Wed, 22 Jul 2015 08:32:05 +0000 (10:32 +0200)]
ARM: zynq: DT: Add missing nodes to DTSI

Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynq: DT: Use the right names for nodes
Michal Simek [Wed, 22 Jul 2015 08:28:48 +0000 (10:28 +0200)]
ARM: zynq: DT: Use the right names for nodes

Based on SPEC you right names with addresses.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Add support for IP detection via SLCR
Michal Simek [Wed, 22 Jul 2015 07:27:11 +0000 (09:27 +0200)]
zynqmp: Add support for IP detection via SLCR

SLCR can be used for IP configuration setting.
Add SLCR skeleton to enable run time checking.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: mp: Simplify set_r5_start handling
Michal Simek [Fri, 22 May 2015 11:26:33 +0000 (13:26 +0200)]
zynqmp: mp: Simplify set_r5_start handling

Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000).
No reason to use magic values 0 and 1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Provide option to enable uart dcc support for zynqmp
Siva Durga Prasad Paladugu [Wed, 10 Jun 2015 10:20:59 +0000 (15:50 +0530)]
zynqmp: Provide option to enable uart dcc support for zynqmp

Provide option to enable uart dcc support for zynqmp
This config can be enabled as per board config file.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoKconfig: zynqmp: Move CONFIG_SYS_TEXT_BASE to defconfig
Siva Durga Prasad Paladugu [Wed, 10 Jun 2015 10:20:58 +0000 (15:50 +0530)]
Kconfig: zynqmp: Move CONFIG_SYS_TEXT_BASE to defconfig

Move CONFIG_SYS_TEXT_BASE of ZynqMP_ep to its
respective defconfig

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Define ep config for ZynqMP
Siva Durga Prasad Paladugu [Wed, 10 Jun 2015 10:20:57 +0000 (15:50 +0530)]
zynqmp: Define ep config for ZynqMP

Define a new config "zynqmp_ep" for ZynqMP instead
of xilinx_zynqmp. This defconfig supports all emulation
platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP
to ARCH_ZYNQMP.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Kconfig: Move zynqmp Kconfig
Siva Durga Prasad Paladugu [Wed, 10 Jun 2015 10:20:56 +0000 (15:50 +0530)]
zynqmp: Kconfig: Move zynqmp Kconfig

Move the zynqmp Kconfig from board to arch
as there may be different boards under same
architecture.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynq: gem: Setting up WRAP bit for one TX bd
Michal Simek [Tue, 26 May 2015 10:01:12 +0000 (12:01 +0200)]
zynq: gem: Setting up WRAP bit for one TX bd

Setting up WRAP bit to indicate that this is the last TX BD in the
chain.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynq: gem: Increase the Rx buffer descriptors to 32
Siva Durga Prasad Paladugu [Wed, 15 Apr 2015 06:45:01 +0000 (12:15 +0530)]
zynq: gem: Increase the Rx buffer descriptors to 32

Increase the Rx Buffer descriptors to 32. This will avoid
Rx buffer descriptors overflow if more packets were received
at one shot before we process the received ones.
This fixes the issue of intermittent timeouts during tftp
on a 1Gb connection with tftp server running on windows.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: gem: Flush the rx buffers while transmitting
Siva Durga Prasad Paladugu [Sat, 6 Dec 2014 07:27:53 +0000 (12:57 +0530)]
zynqmp: gem: Flush the rx buffers while transmitting

Flush and invalidate the rx buffers while sending the
tx packet it self as armv8 does flush also while doing
invalidation.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: gem: Set data bus width to 64bit for arm64
Siva Durga Prasad Paladugu [Tue, 8 Jul 2014 10:01:03 +0000 (15:31 +0530)]
zynqmp: gem: Set data bus width to 64bit for arm64

Set the data bus width to 64-bit AMBA Databus width in config register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agoarm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values
Thierry Reding [Wed, 22 Jul 2015 22:44:32 +0000 (16:44 -0600)]
arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values

The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agoARM: tegra: Build warning fixes for 64-bit
Thierry Reding [Wed, 22 Jul 2015 21:58:05 +0000 (15:58 -0600)]
ARM: tegra: Build warning fixes for 64-bit

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, stripped out changes not strictly related to warnings]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agommc: tegra: Build warning fixes for 64-bit
Thierry Reding [Wed, 22 Jul 2015 21:34:33 +0000 (15:34 -0600)]
mmc: tegra: Build warning fixes for 64-bit

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agoi2c: tegra: Build warning fixes for 64-bit
Thierry Reding [Wed, 22 Jul 2015 21:33:22 +0000 (15:33 -0600)]
i2c: tegra: Build warning fixes for 64-bit

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agodfu: fix 64-bit compile warnings
Stephen Warren [Wed, 22 Jul 2015 20:54:04 +0000 (14:54 -0600)]
dfu: fix 64-bit compile warnings

Use %p to print pointers.

The max value of (i_buf - i_buf_start) should be dfu_buf_size, which is
an unsigned long, so cast the pointer difference to that type to print.

Change-Id: Iee242df9f8eb091aecfe0cea4c282b28b547acfe
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agopxe: add AArch64 image support
Stephen Warren [Tue, 21 Jul 2015 23:49:41 +0000 (17:49 -0600)]
pxe: add AArch64 image support

The sysboot and pxe commands currently support either U-Boot formats or
raw zImages. Add support for the AArch64 Linux port's native image format
too.

As with zImage support, there is no auto-detection of the native image
format. Rather, if the image is auto-detected as a U-Boot format, U-Boot
will try to interpret it as such. Otherwise, U-Boot will fall back to a
raw/native image format, if one is enabled.

My belief is that CONFIG_CMD_BOOTZ won't ever be enabled for any AArch64
port, hence there's never a need to differentiate between CONFIG_CMD_
_BOOTI and _BOOTZ at run-time; compile-time will do. Even if this isn't
true, we want to prefer _BOOTI over _BOOTZ when defined, since _BOOTI is
definitely the native format for AArch64.

Change-Id: I83c5cc7566032afd72516de46f4e5eb7a780284a
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agotegra124: Expand SPL space by 8KB
Simon Glass [Wed, 13 May 2015 13:02:31 +0000 (07:02 -0600)]
tegra124: Expand SPL space by 8KB

We are getting very close to running out of space in SPL, and with the
currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agotegra: nyan-big: Allow TPM on I2C
Simon Glass [Wed, 13 May 2015 13:02:30 +0000 (07:02 -0600)]
tegra: nyan-big: Allow TPM on I2C

Enable the I2C3 pins so that the TPM can be used.

Note: There is an DP change also, caused by running board-to-uboot.py
script in the latest tegra-pinmux-script tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agotegra124: Implement spl_was_boot_source()
Simon Glass [Wed, 13 May 2015 13:02:29 +0000 (07:02 -0600)]
tegra124: Implement spl_was_boot_source()

Add an implementation of this function for Tegra.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoam3517_evm: add FIT support
Yegor Yefremov [Mon, 27 Jul 2015 09:10:58 +0000 (11:10 +0200)]
am3517_evm: add FIT support

Enable DTS support (CONFIG_OF_LIBFDT) and select
CONFIG_FIT in defconfig.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agoReproducible U-Boot build support, using SOURCE_DATE_EPOCH
Paul Kocialkowski [Sun, 26 Jul 2015 16:48:15 +0000 (18:48 +0200)]
Reproducible U-Boot build support, using SOURCE_DATE_EPOCH

In order to achieve reproducible builds in U-Boot, timestamps that are defined
at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
variable allows setting a fixed value for those timestamps.

Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
built reproducibly. This is the case for e.g. sunxi devices.

However, some other devices might need some more tweaks, especially regarding
the image generation tools.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
9 years agotools: remove mpc86x_clk tool
Masahiro Yamada [Sat, 25 Jul 2015 18:40:35 +0000 (03:40 +0900)]
tools: remove mpc86x_clk tool

This is commented out in the Makefile for more than 10 years.
I assume it is proof that this tool is unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
9 years agoconfigs: k2*_evm: rename skernel binary names to generated file names
Nishanth Menon [Wed, 22 Jul 2015 23:05:48 +0000 (18:05 -0500)]
configs: k2*_evm: rename skernel binary names to generated file names

using http://git.ti.com/keystone-linux/boot-monitor/trees/master as
reference (tag K2_BM_15.07) the generated files do not have evm
extensions by default. So dont use -evm extension.

Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agoconfigs: ti_armv7_keystone2: switch to using kernel zImage
Nishanth Menon [Wed, 22 Jul 2015 23:05:47 +0000 (18:05 -0500)]
configs: ti_armv7_keystone2: switch to using kernel zImage

Switch to using zImage instead of uImage. and while at it, start using
bootz as default. While at it, get rid of BOOTIMAGE define and start
using Linux upstream dtb file names.

Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agoconfigs: ti_armv7_keystone2: switch addresses to generic addresses
Nishanth Menon [Wed, 22 Jul 2015 23:05:46 +0000 (18:05 -0500)]
configs: ti_armv7_keystone2: switch addresses to generic addresses

Use the defaults defined in DEFAULT_LINUX_BOOT_ENV

Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agoconfigs: ti_armv7_keystone2: start using armv7_common
Nishanth Menon [Wed, 22 Jul 2015 23:05:45 +0000 (18:05 -0500)]
configs: ti_armv7_keystone2: start using armv7_common

Try to maintain as much commonality by conditionally including stuff
in armv7_common as necessary and removing the common defines from
keystone2 header.

Note: as part of this change, all keystone2 platforms will now start
using the generic u-boot prompt instead of the custom prompt.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agoconfigs: rename ks2_evm into ti_armv7_keystone2
Nishanth Menon [Wed, 22 Jul 2015 23:05:44 +0000 (18:05 -0500)]
configs: rename ks2_evm into ti_armv7_keystone2

rename the keystone2 common header into an keystone2 architecture
specific header which can then reuse the common ti_armv7 config headers.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agoboard: ks2_evm: get rid of bogus CONFIG_LINUX_BOOT_PARAM_ADDR
Nishanth Menon [Wed, 22 Jul 2015 23:05:43 +0000 (18:05 -0500)]
board: ks2_evm: get rid of bogus CONFIG_LINUX_BOOT_PARAM_ADDR

CONFIG_LINUX_BOOT_PARAM_ADDR is not a valid configuration option. Do
just like what the rest of the world does.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agoconfigs: ti: armv7_common: enable Thumb mode for all
Nishanth Menon [Wed, 22 Jul 2015 23:05:42 +0000 (18:05 -0500)]
configs: ti: armv7_common: enable Thumb mode for all

Commit bd2c4522c26d5 ("ti: armv7: enable EXT support in SPL (using
ti_armv7_common.h)") enabled thumb mode only for SPL builds, however,
All TI armv7 platforms do support thumb, and there is no reason why the
space savings cannot be exploited for u-boot as well.

Reported-by: Murali Karicheri <m-karicheri2@ti.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agoconfigs: split ti_armv7_common into a omap generic header
Nishanth Menon [Wed, 22 Jul 2015 23:05:41 +0000 (18:05 -0500)]
configs: split ti_armv7_common into a omap generic header

TI armv7 based SoCs are based on two architectures - one based on OMAP
generation architecture and others based on Keystone architecture.

Many of the options are architecture specific, however a lot are common
with v7 architecture. So, step 1 will be to move out OMAP specific stuff
from ti_armv7_common into a ti_armv7_omap.h header which is then used
by all the relevant architecture headers.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
9 years agonokia_rx51: Typo in CONFIG_MUSB_HCD fixup
Paul Kocialkowski [Tue, 21 Jul 2015 18:10:35 +0000 (20:10 +0200)]
nokia_rx51: Typo in CONFIG_MUSB_HCD fixup

CONFIG_MUSB_HDC should be CONFIG_MUSB_HCD to have any effect.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
9 years agoUpdate the rootfs type to ext4 for Overo and Pepper
Adam YH Lee [Mon, 20 Jul 2015 18:50:40 +0000 (11:50 -0700)]
Update the rootfs type to ext4 for Overo and Pepper

Gumstix is migrating from ext3 to ext4 file system.

Signed-off-by: Adam YH Lee <adam.yh.lee@gmail.com>
Acked-by: Ash Charles <ashcharles@gmail.com>
9 years agostm32f429: use 180 MHz system clock
Antonio Borneo [Sun, 19 Jul 2015 14:19:48 +0000 (22:19 +0800)]
stm32f429: use 180 MHz system clock

Mainline Linux kernel commit
338a6aaabc02fa63b70441dd0e1b70aea64673c6 (ARM: dts: Introduce
STM32F429 MCU) in arch/arm/boot/dts/stm32f429.dtsi
requires U-Boot to set system clock to 180 MHz.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
9 years agostm32f4: add cpu clock option for 180 MHz
Antonio Borneo [Sun, 19 Jul 2015 14:19:47 +0000 (22:19 +0800)]
stm32f4: add cpu clock option for 180 MHz

While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz.
Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
9 years agostm32f429: pass the device unique ID in DTB
Antonio Borneo [Sun, 19 Jul 2015 14:19:46 +0000 (22:19 +0800)]
stm32f429: pass the device unique ID in DTB

Read device unique ID and set environment variable "serial#".
Value would then be passed to kernel through DTB.

To read ID from DTB, kernel is required to have commit:
3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show
the serial number from devicetree in cpuinfo)
This commit is already mainline since v4.1-rc1.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
9 years agoKill unneeded #include <linux/kconfig.h>
Masahiro Yamada [Fri, 17 Jul 2015 11:30:28 +0000 (20:30 +0900)]
Kill unneeded #include <linux/kconfig.h>

Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.

By the way, there are exceptions for the statement above; host
programs.  In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not.  So, some
files still include <linux/config.h> to work around build errors
on host tools.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoboard: ks2: README: fix typos
Nishanth Menon [Thu, 16 Jul 2015 15:14:49 +0000 (10:14 -0500)]
board: ks2: README: fix typos

Fix up a few typos in documentation.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
9 years agoam33xx: Unused get_board_rev function removal
Paul Kocialkowski [Thu, 16 Jul 2015 13:36:41 +0000 (15:36 +0200)]
am33xx: Unused get_board_rev function removal

All am33xx device tree are using device-tree, so get_board_rev is never actually
called. Thus, we can get rid of it to make the code easier to maintain.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>