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8 years agoigep00x0: remove useless setup_net_chip declaration
Ladislav Michl [Tue, 12 Jul 2016 18:28:29 +0000 (20:28 +0200)]
igep00x0: remove useless setup_net_chip declaration

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agoigep00x0: reorder lan9221 code to remove ifdefs
Ladislav Michl [Tue, 12 Jul 2016 18:28:28 +0000 (20:28 +0200)]
igep00x0: reorder lan9221 code to remove ifdefs

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agoigep00x0: move sysinfo into C file
Ladislav Michl [Tue, 12 Jul 2016 18:28:27 +0000 (20:28 +0200)]
igep00x0: move sysinfo into C file

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agocmd: mtdparts: support runtime generated mtdparts
Ladislav Michl [Tue, 12 Jul 2016 18:28:26 +0000 (20:28 +0200)]
cmd: mtdparts: support runtime generated mtdparts

Some CPUs contains boot ROM code capable reading first few blocks
(where SPL resides) of NAND flash and executing it. It is wise to
create separate partition here for SPL. As block size depends on
NAND chip used, we could either use worst case (biggest) partition
size or base its size on actual block size. This patch adds support
for the latter option.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agocmd: mtdparts: use defaults by default
Ladislav Michl [Tue, 12 Jul 2016 18:28:25 +0000 (20:28 +0200)]
cmd: mtdparts: use defaults by default

Boards which are defining default mtdparts often need them early
in boot process (to load environment from UBI volume, for example).
This is currently solved by adding mtdparts and mtdids variable
definitions also to default environment. With this change, default
partitions are used by default unless explicitely deleted or
redefined.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agocmd: mtdparts: consolidate mtdparts reading from env
Ladislav Michl [Tue, 12 Jul 2016 18:28:24 +0000 (20:28 +0200)]
cmd: mtdparts: consolidate mtdparts reading from env

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agocmd: mtdparts: fix null pointer dereference in parse_mtdparts
Ladislav Michl [Tue, 12 Jul 2016 18:28:23 +0000 (20:28 +0200)]
cmd: mtdparts: fix null pointer dereference in parse_mtdparts

In case there is no mtdparts variable in relocated environment,
NULL is assigned to p, which is later fed to strncpy.
Also function parameter mtdparts is completely ignored, so use it
in case mtdparts variable is not found in environment. This
parameter is checked not to be NULL in caller.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agocmd: mtdparts: fix mtdparts variable presence confusion in mtdparts_init
Ladislav Michl [Tue, 12 Jul 2016 18:28:22 +0000 (20:28 +0200)]
cmd: mtdparts: fix mtdparts variable presence confusion in mtdparts_init

A private buffer is used to read mtdparts variable from non-relocated
environment. A pointer to that buffer is returned unconditionally,
confusing later test for variable presence in the environment.
Fix it by returning NULL when getenv_f fails.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agomtd: OneNAND: initialize mtd->writebufsize to let UBI work
Ladislav Michl [Tue, 12 Jul 2016 18:28:21 +0000 (20:28 +0200)]
mtd: OneNAND: initialize mtd->writebufsize to let UBI work

io_init checks this value and fails with "bad write buffer size 0 for
2048 min. I/O unit"

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agomtd: OneNAND: allow board init function fail
Ladislav Michl [Tue, 12 Jul 2016 18:28:20 +0000 (20:28 +0200)]
mtd: OneNAND: allow board init function fail

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agomtd: OneNAND: add timeout to wait ready loops
Ladislav Michl [Tue, 12 Jul 2016 18:28:19 +0000 (20:28 +0200)]
mtd: OneNAND: add timeout to wait ready loops

Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agoarmv7: simplify identify_nand_chip
Ladislav Michl [Tue, 12 Jul 2016 18:28:18 +0000 (20:28 +0200)]
armv7: simplify identify_nand_chip

Use newly introduced function

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agoarmv7: armv7: introduce set_gpmc_cs0
Ladislav Michl [Tue, 12 Jul 2016 18:28:17 +0000 (20:28 +0200)]
armv7: armv7: introduce set_gpmc_cs0

Allow boards to runtime detect flash type.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agoarmv7: make gpmc_cfg const
Ladislav Michl [Tue, 12 Jul 2016 18:28:16 +0000 (20:28 +0200)]
armv7: make gpmc_cfg const

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoarmv7: add reset timeout to identify_nand_chip
Ladislav Michl [Tue, 12 Jul 2016 18:28:15 +0000 (20:28 +0200)]
armv7: add reset timeout to identify_nand_chip

identify_nand_chip hangs forever in loop when NAND is not present.
As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout
to let function fail gracefully allowing caller to know NAND is
not present. On NAND equipped board, reset succeeds on first read,
so 1000 loops seems to be safe timeout.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agospl: zImage support in Falcon mode
Ladislav Michl [Tue, 12 Jul 2016 18:28:14 +0000 (20:28 +0200)]
spl: zImage support in Falcon mode

Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
8 years agospl: support loading from UBI volumes
Ladislav Michl [Tue, 12 Jul 2016 18:28:13 +0000 (20:28 +0200)]
spl: support loading from UBI volumes

Add support for loading from UBI volumes on the top of NAND
and OneNAND.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
8 years agospl: Lightweight UBI and UBI fastmap support
Thomas Gleixner [Tue, 12 Jul 2016 18:28:12 +0000 (20:28 +0200)]
spl: Lightweight UBI and UBI fastmap support

Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.

The upstream UBI + UBI fastmap implementation which is about to
brought to u-boot is too heavy weight for SPLs as it provides way more
functionality than needed for a SPL and does not even fit into the
restricted SPL areas which are loaded from the SoC boot ROM.

So this provides a fast and lightweight implementation of UBI scanning
and UBI fastmap attach. The scan and logical to physical block mapping
code is developed from scratch, while the fastmap implementation is
lifted from the linux kernel source and stripped down to fit the SPL
needs.

The text foot print on the board which I used for development is:

6854 0 0 6854 1abd
drivers/mtd/ubispl/built-in.o

Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are
reserved for the SPL) takes:

In full scan mode:      1172ms
In fastmap mode:          95ms

The code requires quite some storage. The largest and unknown part of
it is the number of fastmap blocks to read. Therefor the data
structure is not put into the BSS. The code requires a pointer to free
memory handed in which is initialized by the UBI attach code itself.

See doc/README.ubispl for further information on how to use it.

This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi
There is no way to share the fastmap code, as UBISPL only utilizes the
slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap()
from the original kernel ubi fastmap implementation.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoonenand_spl_simple: Add a simple OneNAND read function
Ladislav Michl [Tue, 12 Jul 2016 18:28:11 +0000 (20:28 +0200)]
onenand_spl_simple: Add a simple OneNAND read function

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
8 years agonand_spl_simple: Add a simple NAND read function
Thomas Gleixner [Tue, 12 Jul 2016 18:28:10 +0000 (20:28 +0200)]
nand_spl_simple: Add a simple NAND read function

To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
8 years agomtd: Sort subsystem directories aplhabeticaly in Makefile
Ladislav Michl [Tue, 12 Jul 2016 18:28:09 +0000 (20:28 +0200)]
mtd: Sort subsystem directories aplhabeticaly in Makefile

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
8 years agoi2c_eeprom: Add reading support
mario.six@gdsys.cc [Wed, 22 Jun 2016 13:14:16 +0000 (15:14 +0200)]
i2c_eeprom: Add reading support

This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.

Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.

Compatibility strings for a range of at24c* chips are added.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Fri, 22 Jul 2016 13:22:26 +0000 (09:22 -0400)]
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

8 years agozynq: defconfig: Remove unnecessary board specific config files
Siva Durga Prasad Paladugu [Tue, 19 Jul 2016 05:13:43 +0000 (10:43 +0530)]
zynq: defconfig: Remove unnecessary board specific config files

Remove unnecessary board specifc config files for
zynq boards(microzed, picozed, ZC770(all), zed) and point
to zynq common config file.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agozynq: config: Enable CONFIG_SYS_NO_FLASH through defconfig
Siva Durga Prasad Paladugu [Tue, 19 Jul 2016 05:13:42 +0000 (10:43 +0530)]
zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfig

Enable config CONFIG_SYS_NO_FLASH through defconfig
for all zynq boards.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoKconfig: Move option CONFIG_SYS_NO_FLASH to Kconfig
Siva Durga Prasad Paladugu [Tue, 19 Jul 2016 05:12:22 +0000 (10:42 +0530)]
Kconfig: Move option CONFIG_SYS_NO_FLASH to Kconfig

Move config option CONFIG_SYS_NO_FLASH as Kconfig
option. All the boards which needs to enable this
option can be done through defconfigs

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agousb: zynq: Define config USB_STORAGE through defconfig
Siva Durga Prasad Paladugu [Fri, 22 Jul 2016 09:30:26 +0000 (15:00 +0530)]
usb: zynq: Define config USB_STORAGE through defconfig

Define config USB_STORAGE through defconfig for all
respective zynq boards

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agousb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQ
Siva Durga Prasad Paladugu [Fri, 22 Jul 2016 09:21:51 +0000 (14:51 +0530)]
usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQ

Add Kconfig entry config option for USB_EHCI_ZYNQ
and update the same to enable for all zynq boards
which supports USB

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable AHCI on EP platform
Alexander Graf [Wed, 20 Jul 2016 23:34:00 +0000 (01:34 +0200)]
ARM64: zynqmp: Enable AHCI on EP platform

The EP platform also has working AHCI emulation, so I see little reason
not to implement the plumbing for it that enables us to boot from AHCI.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Remove empty ifdef around caches
Michal Simek [Thu, 21 Jul 2016 11:47:52 +0000 (13:47 +0200)]
microblaze: Remove empty ifdef around caches

Code around was removed because of move to Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agodm: clk: Remove simple version of clk_get_by_index/name()
Michal Simek [Thu, 14 Jul 2016 11:11:37 +0000 (13:11 +0200)]
dm: clk: Remove simple version of clk_get_by_index/name()

Simple version of clk_get_by_index() added by:
"dm: clk: Add a simple version of clk_get_by_index()"
(sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44)
is only working for #clock-cells=<1> but not for
any other values. Fixed clocks is using #clock-cells=<0>
which requires full implementation.

Remove simplified versions of clk_get_by_index() and use full version.
Also remove empty clk_get_by_name() which is failing when it is called
which is useless.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agoARM64: zynqmp: Remove get_uart_clk()
Michal Simek [Thu, 14 Jul 2016 12:41:28 +0000 (14:41 +0200)]
ARM64: zynqmp: Remove get_uart_clk()

ZynqMP will use reading clock freq directly from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoserial: zynq: Read information about clock from DT
Michal Simek [Thu, 14 Jul 2016 12:40:03 +0000 (14:40 +0200)]
serial: zynq: Read information about clock from DT

Read information about clock frequency from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
8 years agoARM64: zynqmp: Enable SPL for all zynqmp boards
Michal Simek [Fri, 15 Jul 2016 06:41:46 +0000 (08:41 +0200)]
ARM64: zynqmp: Enable SPL for all zynqmp boards

Compile SPL for all boards even psu_init.c/h files are not in the tree
yet. But this change enables covering SPL issues in mainline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable CLK and SPL_CLK by default
Michal Simek [Thu, 14 Jul 2016 13:07:54 +0000 (15:07 +0200)]
ARM64: zynqmp: Enable CLK and SPL_CLK by default

Serial driver starts to use clk framework that's why
enable it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agospl: Fix compilation warnings for arm64
Michal Simek [Wed, 27 Apr 2016 14:07:20 +0000 (16:07 +0200)]
spl: Fix compilation warnings for arm64

Make code 64bit aware.

Warnings:
+../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’:
+../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
+../common/spl/spl_fat.c: In function ‘spl_load_image_fat’:
+../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agommc: sdhci: Disable internal clock enable bit
Siva Durga Prasad Paladugu [Thu, 25 Feb 2016 07:21:50 +0000 (12:51 +0530)]
mmc: sdhci: Disable internal clock enable bit

Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoapi: Disable api_net when DM is used
Michal Simek [Mon, 6 Jun 2016 08:58:40 +0000 (10:58 +0200)]
api: Disable api_net when DM is used

When CONFIG_API is selected with DM_ETH this
error is present:
api/api_net.c: In function 'dev_enum_net':
api/api_net.c:61:35: warning: initialization from incompatible pointer
type
  struct eth_device *eth_current = eth_get_dev();
                                   ^
api/api_net.c:68:39: error: dereferencing pointer to incomplete type
  memcpy(di->di_net.hwaddr, eth_current->enetaddr, 6);
                                       ^
Disable api_net functions when ETH_DM is selected.

Signed-off-by: Chris Johns <chrisj@rtems.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: zynq/zynqmp: Use the default CONFIG_BOOTDELAY=2
Michal Simek [Tue, 21 Jun 2016 12:39:11 +0000 (14:39 +0200)]
ARM: zynq/zynqmp: Use the default CONFIG_BOOTDELAY=2

Based on:
"ARM: uniphier: use the default CONFIG_BOOTDELAY=2"
(sha1: 7c8ef0feb97586d35b0296b48903daef8c06ab21)

"I do not insist on CONFIG_BOOTDELAY=3. The default value in Kconfig,
CONFIG_BOOTDELAY=2, is just fine for these boards."

Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoMerge git://git.denx.de/u-boot-mpc85xx
Tom Rini [Fri, 22 Jul 2016 00:20:00 +0000 (20:20 -0400)]
Merge git://git.denx.de/u-boot-mpc85xx

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Thu, 21 Jul 2016 22:54:58 +0000 (18:54 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

8 years agoRevert "stm32: Change USART port to USART6 for stm32f746 discovery board"
Tom Rini [Thu, 21 Jul 2016 19:38:13 +0000 (15:38 -0400)]
Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"

Per Vikas' request, the problem this commit is supposed to be solving is
something he doesn't see and further this introduces additional hardware
requirements.

This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agopowerpc/85xx: Increase fdt address
Scott Wood [Tue, 19 Jul 2016 22:52:06 +0000 (17:52 -0500)]
powerpc/85xx: Increase fdt address

Loading the fdt at 0xc00000 fails if the uncompressed kernel image is
greater than 12 MiB, which is quite common with modern kernels and
multiplatform defconfigs.  Move fdtaddr to 0x1e00000 which is just under
the ramdiskaddr on most targets.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodoc: SPL: Add README for secure boot support
Sumit Garg [Thu, 14 Jul 2016 16:27:53 +0000 (12:27 -0400)]
doc: SPL: Add README for secure boot support

Adds information regarding SPL handling validation process of main u-boot
image on power/mpc85xx and arm/layerscape platforms.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopowerpc/mpc85xx: T104x: Add nand secure boot target
Sumit Garg [Thu, 14 Jul 2016 16:27:52 +0000 (12:27 -0400)]
powerpc/mpc85xx: T104x: Add nand secure boot target

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopowerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
Sumit Garg [Thu, 14 Jul 2016 16:27:51 +0000 (12:27 -0400)]
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL

As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agompc83xx: make it bootable with the latest kernel
Kevin Hao [Fri, 8 Jul 2016 03:25:15 +0000 (11:25 +0800)]
mpc83xx: make it bootable with the latest kernel

Due to the blow up of the latest kernel size, the default gnuzip
size (8M) seems too small. The yocto kernel size I built for
mpc8315erdb board is 5294393, and it can't be boot by using the
latest u-boot. So expand gnuzip buffer for all the mpc83xx boards
to fix this issue.

Robert P. J. Day also pointed that the kernel partition on the NAND
flash is also too small, fix it at the same time.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agompc83xx: fix the corruption of u-boot when saveenv
Kevin Hao [Fri, 8 Jul 2016 03:25:14 +0000 (11:25 +0800)]
mpc83xx: fix the corruption of u-boot when saveenv

Robert P. J. Day has pointed that the value of SYS_MONITOR_LEN in
MPC8315ERDB.h is smaller than the u-boot.bin. This will cause the
overlap between the code of u-boot and the environment variable.
So when executing saveenv, it will corrupt the code of u-boot and
causes the board not boot. Fix this for all the mpc83xx boards by
reserving a 512K area.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoARM: tegra: pick up actual memory size
Stephen Warren [Mon, 18 Jul 2016 23:01:51 +0000 (17:01 -0600)]
ARM: tegra: pick up actual memory size

On Tegra186, U-Boot is booted by the binary firmware as if it were a
Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address
of that DTB, and parse the /memory/reg property to determine the actual
RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use.

Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion
that U-Boot use that DTB as its control DTB. I don't believe that would
work well, so I do not plan to put any effort into this. By default the
FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT
bindings. U-Boot aims to use only upstreamed DT bindings, or as close as
it can get. Replacing this DTB with a DTB using upstream bindings is
physically quite easy; simply replace the content of one of the GPT
partitions on the eMMC. However, the binary FW at least partially relies
on the existence/content of some nodes in the DTB, and that requires the
DTB to be written according to downstream bindings. Equally, if U-Boot
continues to use appended DTBs built from its own source tree, as it does
for all other Tegra platforms, development and deployment is much easier.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: Add save_boot_params for ARMv8
Stephen Warren [Mon, 18 Jul 2016 23:01:50 +0000 (17:01 -0600)]
ARM: Add save_boot_params for ARMv8

Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: tegra: p2371-2180: A03 board PMIC config update
Stephen Warren [Mon, 18 Jul 2016 19:02:11 +0000 (13:02 -0600)]
ARM: tegra: p2371-2180: A03 board PMIC config update

Rev A03 of P2180 requires some PMIC programming adjustments, yet the
PMIC's own OTP has not been updated. Consequently, U-Boot must make
these changes itself.

NVIDIA's syseng team has confirmed that these changes can be enabled on
all board revisions without issue.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: tegra: add IVC protocol implementation
Stephen Warren [Mon, 18 Jul 2016 18:17:11 +0000 (12:17 -0600)]
ARM: tegra: add IVC protocol implementation

IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
Processor Communication) framework. Within the context of U-Boot, it is
typically used for communication between the main CPU and various
auxiliary processors. In particular, it will be used to communicate with
the BPMP (Boot and Power Management Processor) on Tegra186 in order to
manipulate clocks and reset signals.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: tegra: unify Tegra186 Makefile a bit
Stephen Warren [Mon, 18 Jul 2016 18:15:05 +0000 (12:15 -0600)]
ARM: tegra: unify Tegra186 Makefile a bit

Many files in arch/arm/mach-tegra are compiled conditionally based on
Kconfig variables, or applicable to all platforms. We can let the main
Tegra Makefile handle compiling (or not) those files to avoid each SoC-
specific Makefile needing to duplicate entries for those files. This
leaves the SoC-specific Makefiles to compile truly SoC-specific code.

In the future, we'll hopefully add Kconfig variables for all the other
files, and refactor those files, and so reduce the need for SoC-specific
Makefiles and/or ifdefs in the Makefiles.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: tegra: split p2771-0000 build
Stephen Warren [Mon, 18 Jul 2016 18:15:04 +0000 (12:15 -0600)]
ARM: tegra: split p2771-0000 build

There are multiple versions of p2771-0000 board. There are SW visible
incompatible differences between the versions, and they are relevant to
U-Boot. Create separate "A02" and "B00" defconfigs (named after the first
and/or only board rev the defconfig supports) so that users can select
which build they want.

With the minimal set of HW currently enabled in U-Boot, the differences
are irrelevant, hence the DT files aren't different. However, that will
change in a future patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoARM: tegra: fix Tegra186 DT GPIO binding header
Stephen Warren [Mon, 18 Jul 2016 18:15:03 +0000 (12:15 -0600)]
ARM: tegra: fix Tegra186 DT GPIO binding header

Tegra186 uses different GPIO port IDs compared to previous chips. Make
sure the SoC DT file includes the correct GPIO binding header.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoimage: fix IH_ARCH_... values for uImage compatibility
Masahiro Yamada [Thu, 21 Jul 2016 06:16:00 +0000 (15:16 +0900)]
image: fix IH_ARCH_... values for uImage compatibility

Commit 555f45d8f916 ("image: Convert the IH_... values to enums")
accidentally changed some IH_ARCH_... values.

Prior to that commit, there existed a gap between IH_ARCH_M68K and
IH_ARCH_MICROBLAZE, like follows.

  #define IH_ARCH_SPARC64         11      /* Sparc 64 Bit */
  #define IH_ARCH_M68K            12      /* M68K         */
  #define IH_ARCH_MICROBLAZE      14      /* MicroBlaze   */
  #define IH_ARCH_NIOS2           15      /* Nios-II      */

The enum conversion broke the compatibility with existing uImage
files.  Reverting 555f45d8f916 will cause build error unfortunately,
so here is a more easy fix.

I dug the git history and figured out the gap was introduced by
commit 1117cbf2adac ("nios: remove nios-32 arch").  So, I revived
IH_ARCH_NIOS just for filling the gap.

I added comments to each enum block.  Once we assign a value to
IH_... it is not allowed to change it.

Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Thu, 21 Jul 2016 14:40:35 +0000 (10:40 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

8 years agopowerpc: MPC8544DS: revert typo in I2C offset value
Benjamin Kamath [Wed, 29 Jun 2016 23:44:38 +0000 (16:44 -0700)]
powerpc: MPC8544DS: revert typo in I2C offset value

I2C offset was changed by commit 00f792e0 (added multibus support)
from 0x3100 to 0x3000. This typo leads to error when reading SPD
from DDR DIMMs.

Signed-off-by: Benjamin Kamath <bkamath@spaceflight.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agomtd: cfi_flash: fix polling for bit XSR.7 on Intel chips
Daniel Schwierzeck [Mon, 18 Jul 2016 12:10:37 +0000 (14:10 +0200)]
mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips

flash_full_status_check() checks bit XSR.7 on Intel chips. This
should be done by only checking bit 7 and not by comparing the
whole status byte or word with 0x80.

This fixes the non-working block erase in the pflash emulation
of Qemu when used with the MIPS Malta board. MIPS Malta uses x32
mode to access the pflash device. In x32 mode Qemu mirrors the
lower 16 bits of the status word into the upper 16 bits. Thus
the CFI driver gets a status word of 0x8080 in x32 mode. If
flash_full_status_check() uses flash_isequal(), then it polls for
XSR.7 by comparing 0x8080 with 0x80 which never becomes true.

Reported-by: Alon Bar-Lev <alon.barlev@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
8 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 19 Jul 2016 20:38:57 +0000 (16:38 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
arch/arm/cpu/armv8/Makefile
arch/arm/lib/bootm-fdt.c

8 years agoARMv8/ls1043ardb: Integrate FSL PPA
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:17 +0000 (20:18 +0800)]
ARMv8/ls1043ardb: Integrate FSL PPA

The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoARMv8/PSCI: Fixup the device tree for PSCI
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:16 +0000 (20:18 +0800)]
ARMv8/PSCI: Fixup the device tree for PSCI

Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoARMv8/Layerscape: switch SMP method accordingly
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:15 +0000 (20:18 +0800)]
ARMv8/Layerscape: switch SMP method accordingly

If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoARMv8/layerscape: Add FSL PPA support
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:14 +0000 (20:18 +0800)]
ARMv8/layerscape: Add FSL PPA support

The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.

Use the secure firmware framework to integrate FSL PPA into U-Boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoARMv8: add the secure monitor firmware framework
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:13 +0000 (20:18 +0800)]
ARMv8: add the secure monitor firmware framework

This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.

So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: add i/d-cache enable function to enable_caches
Hou Zhiqiang [Tue, 28 Jun 2016 12:18:12 +0000 (20:18 +0800)]
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches

This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.

Define the function mmu_setup() for fsl-layerscape to cover the weak
one.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: layerscape: Convert to use common MMU framework
York Sun [Fri, 24 Jun 2016 23:46:23 +0000 (16:46 -0700)]
armv8: layerscape: Convert to use common MMU framework

Drop platform code to create static MMU tables. Use common framework
to create MMU tables on the run. Tested on LS2080ARDB with secure and
non-secure ram scenarios.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agotest: Adjust the of-platdata test run condition
Simon Glass [Sun, 17 Jul 2016 00:36:44 +0000 (18:36 -0600)]
test: Adjust the of-platdata test run condition

This should be spl_of_platdata, since otherwise it will try to run on boards
that don't support of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoVarious, unrelated tree-wide typo fixes.
Robert P. J. Day [Fri, 15 Jul 2016 17:44:45 +0000 (13:44 -0400)]
Various, unrelated tree-wide typo fixes.

    Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
8 years agoconfigs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entries
Tom Rini [Fri, 15 Jul 2016 19:30:33 +0000 (15:30 -0400)]
configs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entries

The code had assumed 4 CPUS before and now we have this configurable.
For now, set this to the previous default.

Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
8 years agoarmv8: mmu: Add support of non-identical mapping
York Sun [Fri, 24 Jun 2016 23:46:22 +0000 (16:46 -0700)]
armv8: mmu: Add support of non-identical mapping

Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: mmu: split block if necessary
York Sun [Fri, 24 Jun 2016 23:46:21 +0000 (16:46 -0700)]
armv8: mmu: split block if necessary

When page tables are created, allow later table to be created on
previous block entry. Splitting block feature is already working
with current code. This patch only rearranges the code order and
adds one condition to call split_block().

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: mmu: house cleaning
York Sun [Fri, 24 Jun 2016 23:46:20 +0000 (16:46 -0700)]
armv8: mmu: house cleaning

Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: Add tlb_allocated to arch global data
York Sun [Fri, 24 Jun 2016 23:46:19 +0000 (16:46 -0700)]
armv8: Add tlb_allocated to arch global data

When secure ram is used, MMU tables have to be put into secure ram.
To use common MMU code, gd->arch.tlb_addr will be used to host TLB
entry pointer. To save allocated memory for later use, tlb_allocated
variable is added to global data structure.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: Move secure_ram variable out of generic global data
York Sun [Fri, 24 Jun 2016 23:46:18 +0000 (16:46 -0700)]
armv8: Move secure_ram variable out of generic global data

Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoMerge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini [Fri, 15 Jul 2016 14:44:01 +0000 (10:44 -0400)]
Merge branch 'master' of http://git.denx.de/u-boot-sunxi

8 years agoARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:45 +0000 (12:38 +0800)]
ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S

Now that we have a secure data section for storing variables, there
should be no need for platform code to get the stack address.

Make psci_get_cpu_stack_top a local function, as it should only be
used in armv7/psci.S and only by psci_stack_setup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Switch to per-CPU target PC storage in secure data section
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:44 +0000 (12:38 +0800)]
ARM: PSCI: Switch to per-CPU target PC storage in secure data section

Now that we have a secure data section and space to store per-CPU target
PC address, switch to it instead of storing the target PC on the stack.

Also save clobbered r4-r7 registers on the stack and restore them on
return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Add helper functions to access per-CPU target PC storage
Chen-Yu Tsai [Tue, 5 Jul 2016 13:45:07 +0000 (21:45 +0800)]
ARM: PSCI: Add helper functions to access per-CPU target PC storage

Now that we have a data section, add helper functions to save and fetch
per-CPU target PC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: Add secure section for initialized data
Chen-Yu Tsai [Tue, 5 Jul 2016 13:45:06 +0000 (21:45 +0800)]
ARM: Add secure section for initialized data

The secure monitor may need to store global or static values within the
secure section of memory, such as target PC or CPU power status.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: Move __secure definition to common asm/secure.h
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:41 +0000 (12:38 +0800)]
ARM: Move __secure definition to common asm/secure.h

sunxi and i.mx7 both define the __secure modifier to put functions in
the secure section. Move this to a common place.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7i
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:40 +0000 (12:38 +0800)]
sunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7i

Both sun6i and sun7i have 64 KB of secure SRAM.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure section
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:39 +0000 (12:38 +0800)]
ARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure section

As the PSCI implementation grows, we might exceed the size of the secure
memory that holds the firmware.

Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define
how much secure memory is available. The linker then checks the size of
the whole secure section against this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Remove unused psci_text_end symbol
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:38 +0000 (12:38 +0800)]
ARM: PSCI: Remove unused psci_text_end symbol

psci_text_end was used to calculate the PSCI stack address following the
secure monitor text. Now that we have an explicit secure stack section,
this is no longer used.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Allocate PSCI stack in secure stack section
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:37 +0000 (12:38 +0800)]
ARM: PSCI: Allocate PSCI stack in secure stack section

Now that we have a secure stack section that guarantees usable memory,
allocate the PSCI stacks in that section.

Also add a diagram detailing how the stacks are placed in memory.

Reserved space for the target PC remains unchanged. This should be
moved to global variables within a secure data section in the future.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: Add an empty secure stack section
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:36 +0000 (12:38 +0800)]
ARM: Add an empty secure stack section

Until now we've been using memory beyond psci_text_end as stack space
for the secure monitor or PSCI implementation, even if space was not
allocated for it.

This was partially fixed in ("ARM: allocate extra space for PSCI stack
in secure section during link phase"). However, calculating stack space
from psci_text_end in one place, while allocating the space in another
is error prone.

This patch adds a separate empty secure stack section, with space for
CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also
__secure_stack_start and __secure_stack_end symbols. The linker script
handles calculating the correct VMAs for the stack section. For
platforms that relocate/copy the secure monitor before using it, the
space is not allocated in the executable, saving space.

For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page
of stack space for 4 CPUs is allocated, matching the previous behavior.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled platforms
Chen-Yu Tsai [Tue, 5 Jul 2016 13:45:05 +0000 (21:45 +0800)]
ARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled platforms

The original PSCI implementation assumed CONFIG_ARMV7_PSCI_NR_CPUS=4.
Add this to platforms that have not defined it, using CONFIG_MAX_CPUS if
it is defined, or the actual number of cores for the given platform.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: Page align secure section only when it is executed in situ
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:34 +0000 (12:38 +0800)]
ARM: Page align secure section only when it is executed in situ

Targets that define CONFIG_ARMV7_SECURE_BASE will copy the secure section
to another address before execution.

Since the secure section in the u-boot image is only storage, there's
no reason to page align it and increase the binary image size.

Page align the secure section only when CONFIG_ARMV7_SECURE_BASE is not
defined. And instead of just aligning the __secure_start symbol, align
the whole .__secure_start section. This also makes the section empty,
so we need to add KEEP() to the input entry to prevent the section from
being garbage collected.

Also use ld constant "COMMONPAGESIZE" instead of hardcoded page size.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for sun7i
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:33 +0000 (12:38 +0800)]
sunxi: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for sun7i

sun7i has 2 CPUs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Move remaining PSCI assembly code to C
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:32 +0000 (12:38 +0800)]
sunxi: Move remaining PSCI assembly code to C

This patch finishes the rewrite of sunxi specific PSCI parts into C
code.

The assembly-only stack setup code has been factored out into a common
function for ARMv7. The GIC setup code can be renamed as psci_arch_init.
And we can use an empty stub function for psci_text_end.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: PSCI: Split out common stack setup code from psci_arch_init
Chen-Yu Tsai [Sun, 19 Jun 2016 04:38:31 +0000 (12:38 +0800)]
ARM: PSCI: Split out common stack setup code from psci_arch_init

Every platform has the same stack setup code in assembly as part of
psci_arch_init.

Move this out into a common separate function, psci_stack_setup, for
all platforms. This will allow us to move the remaining parts of
psci_arch_init into C code, or drop it entirely.

Also provide a stub no-op psci_arch_init for platforms that don't need
their own specific setup code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add defconfig and dts file for the Orange Pi Lite SBC
Hans de Goede [Sat, 9 Jul 2016 20:20:00 +0000 (22:20 +0200)]
sunxi: Add defconfig and dts file for the Orange Pi Lite SBC

The Orange Pi Lite SBC is a small H3 based SBC, with 512MB RAM,
micro-sd slot, HDMI out, 2 USB-A connectors, 1 micro-USB connector,
sdio attached rtl8189ftv wifi and an ir receiver.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Sync sun8i-h3-orangepi-plus.dts with upstream
Hans de Goede [Sat, 9 Jul 2016 15:31:14 +0000 (17:31 +0200)]
sunxi: Sync sun8i-h3-orangepi-plus.dts with upstream

This enables extra USB controllers which enable use of the 3rd USB
port on the new Orange Pi Plus 2E variant.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: orangepi_pc: Add support for eMMC found on the Orange Pi PC Plus
Hans de Goede [Sat, 9 Jul 2016 13:15:12 +0000 (15:15 +0200)]
sunxi: orangepi_pc: Add support for eMMC found on the Orange Pi PC Plus

The Plus variant of the Orange Pi PC has an eMMC, add support for this.

Note we are using the same u-boot defconfig / dts for both the regular
Orange Pi PC as well as the Orange Pi PC Plus.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Use BROM stored boot_media value to determine our boot-source
Hans de Goede [Sat, 9 Jul 2016 13:31:47 +0000 (15:31 +0200)]
sunxi: Use BROM stored boot_media value to determine our boot-source

Now that we know that the BROM stores a value indicating the boot-source
at the beginning of SRAM, use that instead of trying to recreate the
BROM's boot probing.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Remove some unnecessary #ifdefs
Hans de Goede [Sat, 9 Jul 2016 07:56:56 +0000 (09:56 +0200)]
sunxi: Remove some unnecessary #ifdefs

We always define CONFIG_MISC_INIT_R on sunxi and misc_init_r is never
called in the spl, so the linker will optimize it and parse_spl_header(),
of which it is the only caller, away.

On the tests I've done (Orange Pi PC build) the SPL actually becomes
8 bytes smaller with this patch.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Add support for multiple ethadrr-esses
Hans de Goede [Sun, 26 Jun 2016 11:34:42 +0000 (13:34 +0200)]
sunxi: Add support for multiple ethadrr-esses

Currently we fill ethaddr with a fixed unique address based on the SoCs
serial (from the sid) to make sure that boards which use the integrated
emac / gmac get a fixed mac rather then a random one.

On some boards the wifi does not come with a fixed mac either, so we need
to also set eth1addr.

This commit changes the ethaddr setting code to check for ethernet%d
aliases (as fdt_fixup_ethernet does) and set an ethaddr variable for
all present aliases.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-samsung
Tom Rini [Fri, 15 Jul 2016 12:06:42 +0000 (08:06 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-samsung

8 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 15 Jul 2016 12:06:22 +0000 (08:06 -0400)]
Merge git://git.denx.de/u-boot-dm

8 years agonet: Add EMAC driver for H3/A83T/A64 SoCs.
Amit Singh Tomar [Wed, 6 Jul 2016 12:29:44 +0000 (17:59 +0530)]
net: Add EMAC driver for H3/A83T/A64 SoCs.

This patch add EMAC driver support for H3/A83T/A64 SoCs.
Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY).

BIG Thanks to Andre for providing some of the DT code.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>