Andy Fleming [Wed, 21 Oct 2015 23:59:06 +0000 (18:59 -0500)]
rtc: Add MCP79411 support to DS1307 rtc driver
The code is from Adrian Cox, and is patterned after similar
support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
chip is used on the Cyrus board from Varisys.
Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
Simon Glass [Sun, 18 Oct 2015 01:41:24 +0000 (19:41 -0600)]
arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Sun, 18 Oct 2015 01:41:19 +0000 (19:41 -0600)]
dm: spl: Support device tree when BSS is in a different section
At present in SPL we place the device tree immediately after BSS. This
avoids needing to copy it out of the way before BSS can be used. However on
some boards BSS is not placed with the image - e.g. it can be in RAM if
available.
Add an option to tell U-Boot that the device tree should be placed at the
end of the image binary (_image_binary_end) instead of at the end of BSS.
Note: A common reason to place BSS in RAM is to support the FAT filesystem.
We should update the code so that it does not use so much BSS.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Sun, 18 Oct 2015 01:41:15 +0000 (19:41 -0600)]
fdt: Correct handling of alias regions
At present the last four bytes of the alias region are dropped in
the case where the last alias is included. This results in a corrupted
device tree. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq-common: Define CONFIG_SYS_I2C_ZYNQ based on board config
Enable CONFIG_SYS_I2C_ZYNQ only if it has either I2C0 or I2C1
enabled in a board config.This fixes the issue of i2c error
during board init if board specific doesnt have either I2C0
or I2C1.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 30 Oct 2015 15:21:30 +0000 (16:21 +0100)]
usb: udc: Fix warnings on 64-bit builds
Cast u32 bit value to 64bit before recasting to 64bit pointer to avoid
pointer from integer cast size mismatch warnings.
Warning log:
+../drivers/usb/gadget/udc/udc-core.c: In function
‘usb_gadget_unmap_request’:
+../drivers/usb/gadget/udc/udc-core.c:68:19: warning: cast to pointer
from integer of different size [-Wint-to-pointer-cast]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 30 Oct 2015 15:19:43 +0000 (16:19 +0100)]
usb: lthor: Specify correct parameter for sizeof type
This patch removes this warning:
CC drivers/usb/gadget/f_thor.o
drivers/usb/gadget/f_thor.c: In function ‘thor_tx_data’:
drivers/usb/gadget/f_thor.c:572:2: warning: format ‘%d’ expects argument
of type ‘int’, but argument 4 has type ‘long unsigned int’ [-Wformat=]
debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__,
^
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vignesh R [Tue, 20 Oct 2015 09:52:00 +0000 (15:22 +0530)]
dfu: dfu_sf: Pass duplicate devstr to parse_dev
parse_dev() alters the string pointed by devstr parameter. Due to this
subsequent parsing of sf entities will fail, as string pointed by devstr
is no longer valid sf dev arguments.
Fix this by passing pointer to the copy of the string to parse_dev
instead of pointer to the actual devstr.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Hans de Goede [Tue, 20 Oct 2015 16:39:29 +0000 (18:39 +0200)]
ohci: Add missing cache-flush for hcca area
We need to cache-flush the hcca area after the initial memset, otherwise
on the first hc_interrupt we might see an old $random value as done_head and
try to interpret that as the address for a completed td (followed by chaos).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tom Rini [Sun, 11 Oct 2015 11:26:27 +0000 (07:26 -0400)]
common/usb_storage.c: Clean up usb_storage_probe()
We have the protocol and subclass variables which are used only in
disabled debug code. This code dates back to the initial git import and
seemingly dead code so remove it.
Wenyou Yang [Mon, 2 Nov 2015 02:57:09 +0000 (10:57 +0800)]
mmc: atmel: Add atmel sdhci support
The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia
Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC)
Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO
V3.0 specification. It is compliant with the SD Host Controller Standard
V3.0 specification.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Fri, 30 Oct 2015 01:47:02 +0000 (09:47 +0800)]
arm: at91: clock: Add the generated clock support
Some peripherals may need a second clock source that may be different
from the system clock. This second clock is the generated clock (GCK)
and is managed by the PMC via PMC_PCR.
For simplicity, the clock source of the GCK is fixed to PLLA_CLK.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 22 Sep 2015 06:59:25 +0000 (14:59 +0800)]
mmc: sdhci: Fix the SD clock stop sequence
According to the SDHC specification, stopping the SD Clock is by setting
the SD Clock Enable bit in the Clock Control register at 0, instead of
setting all bits at 0.
Before stopping the SD clock, we need to make sure all SD transactions
to complete, so add checking the CMD and DAT bits in the Presen State
register, before stopping the SD clock.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
T104xD4RDB: Fix PHY address for PHY connected to FM1@DTSEC3
On T1040D4RDB board, u-boot fails to connect port FM1@DTSEC3 to
the Ethernet PHY because the wrong PHY address is used. Also,
T1040D4RDB supports SGMII on one port only.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Yangbo Lu [Thu, 17 Sep 2015 02:27:48 +0000 (10:27 +0800)]
mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card
When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
There are 8 pins for SD card in Exynos, but the MUX was configured
only for 7, since the one was used for card detection.
This caused the pin's pull wrong configuration.
This commit fixes this and the card detect can work properly,
after call this function.
This commit adds implementation of Sandbox ADC device emulation.
The device provides:
- single and multi-channel conversion
- 4 channels with predefined conversion output data
- 16-bit resolution
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
exynos5-dt-types: add board detection for Odroid XU3/XU3L/XU4.
This commit adds additional file with implementation of board
detection code for Odroid-XU3/XU4.
The detection depends on compatible found in fdt:
- "samsung,exynos5" - uses Exynos5 generic code
- "samsung,odroidxu3" - try detect XU3 revision
There are few revisions of Odroid XU3/XU4, each can be detected
by checking the value of channel 9 of built-in ADC:
Rev ADC Board
0.1 0 XU3 0.1
0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT
0.3 1280 XU4 0.1
The detection code depends on the ADC+10% value.
Implementation of functions:
- set_board_type() - read ADC and set type
- get_board_rev() - returns board revision: 1..3
- get_board_type() - returns board type string
Additional functions with return values of bool:
- board_is_generic() - true if found compatible "samsung,exynos5"
but not "samsung,odroidxu3"
- board_is_odroidxu3() - true if found compatible "samsung,odroidxu3"
and one of XU3 revision.
- board_is_odroidxu4() - true if found compatible "samsung,odroidxu3"
and XU4 revision.
After I2C controller init, the get_board_type() can check
if the XU3 board is a "Lite" variant, by probing chip
0x40 on I2C0 (INA231 - exists only on non-lite).
This is useful for setting fdt file name at misc_init_r().
Odroid-XU3: dts: enable ADC, with request for pre-reloc bind
This ADC is required for Odroid's board revision detection.
The pre-reloc request is enabled, since board detection will
be done in one of early function call.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds common ADC node, which is disabled as default.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds driver for Exynos54xx ADC subsystem.
The driver is implemented using driver model, amd provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
The basic parameters of ADC conversion, are:
- sample rate: 600KSPS
- output the data as average of 8 time conversion
This commit adds:
- new uclass id: UCLASS_ADC
- new uclass driver: drivers/adc/adc-uclass.c
The new uclass's API allows for ADC operation on:
* single-channel with channel selection by a number
* multti-channel with channel selection by bit mask
ADC uclass's functions:
* single-channel:
- adc_start_channel() - start channel conversion
- adc_channel_data() - get conversion data
- adc_channel_single_shot() - start/get conversion data
* multi-channel:
- adc_start_channels() - start selected channels conversion
- adc_channels_data() - get conversion data
- adc_channels_single_shot() - start/get conversion data for channels
selected by bit mask
* general:
- adc_stop() - stop the conversion
- adc_vdd_value() - positive reference Voltage value with polarity [uV]
- adc_vss_value() - negative reference Voltage value with polarity [uV]
- adc_data_mask() - conversion data bit mask
The device tree can provide below constraints/properties:
- vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1)
- vss-polarity-negative: if true: Vss = vss-microvolts * (-1)
- vdd-supply: phandle to Vdd regulator's node
- vss-supply: phandle to Vss regulator's node
And optional, checked only if the above corresponding, doesn't exist:
- vdd-microvolts: positive reference Voltage [uV]
- vss-microvolts: negative reference Voltage [uV]
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
dm: regulator: add function device_get_supply_regulator()
Some devices are supplied by configurable regulator's output.
But there was no function for getting it. This commit adds
function, that allows for getting the supply device by it's phandle.
The returned regulator device can be used with regulator uclass's API.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.
Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).
For such case, the CPU name should be defined in device tree.
This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Josh Wu [Tue, 27 Oct 2015 05:31:33 +0000 (13:31 +0800)]
ARM: at91: sama5: change the environment address to 0x6000
As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5
boards is bigger than 16k (0x4000). That will overlap the U-Boot
environment. So I move environment to 0x6000. And reduce its size as
well.
Following shows the size of the spl binaries (v2015.04 vs v2015.07):
Marek Vasut [Fri, 23 Oct 2015 18:46:31 +0000 (20:46 +0200)]
mmc: atmel: Zap global 'initialized' variable
Global variables are bad. Get rid of this particular one, so we can
correctly instantiate multiple atmel mci interfaces, without having
them interfere with one another.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Fri, 23 Oct 2015 18:46:30 +0000 (20:46 +0200)]
mmc: atmel: Implement proper private data
Instead of passing just the register area as a private data, introduce
a proper struct atmel_mci_priv structure instead. This will become useful
in the subsequent patch, where we eliminate the global variable from this
driver.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix free()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Fri, 23 Oct 2015 18:46:29 +0000 (20:46 +0200)]
mmc: atmel: Fix clock configuration
After silencing the prints which were generated when reconfiguring the
clock of the SD/MMC bus, surprisingly, the driver stopped working such
that every attempt to use the SD/MMC bus caused the CPU to get totally
stuck hard. It turns out that the prints generated a short delay, which
was necessary for the CPU to reconfigure the clock without getting stuck.
Thus, this patch adds a short delay after the clock configuration instead.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Fri, 23 Oct 2015 18:46:28 +0000 (20:46 +0200)]
mmc: atmel: Silence debug output
This driver generates clearly debugging prints when changing clock
speed, so silence those. Furthermore, the driver generates further
prints in case a command fails to complete. The later case woud be
useful, but for eMMC, command 8 can fail and it's not an error but
a part of the specification. Thus, make this debug() as well.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Alison Wang [Fri, 30 Oct 2015 14:45:38 +0000 (22:45 +0800)]
ls102xa: Adjust some macros for SD boot on LS1021A QDS board
As more features are added for SD boot on LS1021A QDS board,
the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
needs to be adjusted to a suitable value.
Starting address of the malloc pool used in SPL needs to be
adjusted too, or it will occupy the address u-boot loads.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>