Simon Glass [Fri, 22 May 2015 21:42:17 +0000 (15:42 -0600)]
sandbox: dts: Add the real-time-clock test nodes back in
These were lost when the PMIC series was applied. Add them back so that the
tests pass again.
Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Fri, 22 May 2015 21:42:14 +0000 (15:42 -0600)]
dm: Sort the uclass IDs after the tegra/PMIC addition
Tidy up the sort order again.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Mon, 11 May 2015 03:08:06 +0000 (21:08 -0600)]
dm: pci: Allow PCI bus numbering aliases
Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed
the default uclass behaviour to not support bus numbering. This is incorrect
for PCI and that commit should have enabled the flag for PCI.
Enable it so that PCI buses can be found and the 'pci' command works again.
Also add a test for this.
Simon Glass [Mon, 11 May 2015 03:07:27 +0000 (21:07 -0600)]
sandbox: Tidy up terminal restore
For some reason 'u-boot -D' does not restore the terminal correctly when
the 'reset' command is used. Call the terminal restore function explicitly
in this case.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Andrew Bradford [Wed, 3 Jun 2015 16:37:39 +0000 (12:37 -0400)]
x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up. There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 3 Jun 2015 01:20:06 +0000 (09:20 +0800)]
x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 3 Jun 2015 01:20:05 +0000 (09:20 +0800)]
x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 3 Jun 2015 01:20:04 +0000 (09:20 +0800)]
x86: qemu: Create separate i440fx and q35 device trees
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 25 May 2015 14:36:27 +0000 (22:36 +0800)]
x86: qemu: Adjust VGA initialization
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.
Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 25 May 2015 14:36:26 +0000 (22:36 +0800)]
x86: qemu: Enable legacy IDE I/O ports decode
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 23 May 2015 16:12:33 +0000 (00:12 +0800)]
x86: qemu: Turn on legacy segments decode
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 23 May 2015 16:12:32 +0000 (00:12 +0800)]
x86: qemu: Make host bridge (b.d.f=0.0.0) visible
The default weak version of pci_skip_dev() in drivers/pci/pci_common.c
skips the host bridge (b.d.f = 0.0.0) which is actually the i440fx/q35
chipset for QEMU targets. Define CONFIG_PCI_CONFIG_HOST_BRIDGE to make
it visible in the PCI configuration space.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 25 May 2015 14:35:07 +0000 (22:35 +0800)]
x86: Do sanity test on pirq table before writing
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 25 May 2015 14:35:06 +0000 (22:35 +0800)]
x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 25 May 2015 14:35:04 +0000 (22:35 +0800)]
x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 10 May 2015 23:36:29 +0000 (07:36 +0800)]
x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video Kconfig
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 7 May 2015 13:34:08 +0000 (21:34 +0800)]
x86: Support QEMU x86 targets
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
https://patchwork.ozlabs.org/patch/479745/
Masahiro Yamada [Tue, 26 May 2015 03:42:13 +0000 (12:42 +0900)]
blackfin: fix build error on bct-brettl2 board
Commit 76ec988b062e (net: Remove all calls to net_random_ethaddr())
accidentally deleted CONFIG_TARGET_BCT_BRETTL2=y, and since then
bct-brettl2 would not build.
Since commit a26cd04920dc (arch: Make board selection choices
optional), Kconfig actually allows such a .config file in which no
board is selected, but the build never succeeds.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
arm: rmobile: alt: Add ethernet function B support
Ethernet function of Alt board can select normal and B by DIP switch
on board. But user need to set not only DIP switch but also pin function.
This adds pin function of Ethernet function B. This can select from Kconfig.
Masahiro Yamada [Fri, 29 May 2015 08:30:07 +0000 (17:30 +0900)]
ARM: UniPhier: enable CONFIG_NET_RANDOM_ETHADDR
Since commit 92ac52082140 (net: Remove all references to
CONFIG_ETHADDR and friends), the ethernet device on UniPhier boards
is not working because of the incorrect (all-zero) MAC address.
Enable CONFIG_NET_RANDOM_ETHADDR to generate the random one.
Masahiro Yamada [Fri, 29 May 2015 08:30:06 +0000 (17:30 +0900)]
ARM: UniPhier: set MACH_PH1_PRO4 as default SoC
One disadvantage of commit a26cd04920dc (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the
"optional" again in favor of PH1-Pro4 as the default SoC.
This file is only built for SPL. These ifdef conditionals are
unnecessary because UniPhier platform now supports UART on SPL.
Show appropriate messages on error.
sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi/nand: change BLOCK_SIZE in mksunxiboot to match NAND block size
This change is necessary to calculate correct checksum for NAND
boot. Works both for MMC and NAND. Without it BROM rejects boot image
as invalid (bad checksum). (Changes block size from 0x200 to 0x2000).
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Wed, 20 May 2015 13:27:16 +0000 (15:27 +0200)]
sunxi: Update sunxi-common.h to deal with different A1-SRAM base addr on sun9i
The A1 SRAM Base differs between sun9i and the others, update sunxi-common.h
to deal with this, so that we do not set the initial stack pointer to point
to the BROM.
This avoids the need for the weird undocumented register write I previously
took from the allwiner u-boot sources and which needed #ifdef-ery in start.S
as it needed to be done really early on.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 19 May 2015 21:34:00 +0000 (23:34 +0200)]
sunxi: Use axp221 sid on a33
Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again,
but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221
sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 19 May 2015 20:51:03 +0000 (22:51 +0200)]
usb: kbd: Fix key repeat not always working
The usb-kbd key repeat code assumes that reports get repeated every 40 ms,
this is never true when using CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP, and
does not always works for CONFIG_SYS_USB_EVENT_POLL and
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE since not all usb keyboards honor
the usb_set_idle() command.
For CONFIG_SYS_USB_EVENT_POLL we must use usb_set_idle() since we do a
blocking wait for the hid report, so if we do not tell the keyboard to send
a hid report every 40ms even if nothing changes then we will block u-boot
for 1s (the default u-boot usb interrupt packet timeout). Note that in this
case on keyboards which do not support usb_set_idle() we loose and we actually
get 1s latencies on other u-boot activities.
For the other poll-methods this commit stops using usb_set_idle() and instead
repeats the last received hid-report every 40 ms as long as no new hid-report
is received. This fixes key-repeat not working at all with
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP and fixes it not working with
keyboards which do not implement usb_set_idle() when using
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Peter Griffin [Tue, 12 May 2015 13:38:27 +0000 (14:38 +0100)]
usb: dwc2: Add support for v3 snpsid value
This has been tested to the extent that I can enumerate
a asix usb networking adapter and boot a kernel over usb
on the 96boards hikey u-boot port I'm currently doing.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
ci_udc: Update the ci_udc driver to support bulk transfers
Update the ci_udc driver to support bulk transfer
and also added capability of having multiple dtds
if requested data is more than 16K.
These changes are tested for both the DFU and lthor.
Heiko Schocher [Thu, 28 May 2015 05:27:36 +0000 (07:27 +0200)]
am33xx, spl, siemens: enable debug uart output again
a6b541b090: TI ARMv7: Don't use GD before crt0.S has set it
moves the init of the debug uart at the very end of SPL code.
Enable it for the siemens board earlier, as they print
ddr settings ... all debug output before board_init_r()
is here currently useless. Maybe we must rework this
globally?
Tang Yuantian [Wed, 6 May 2015 03:21:33 +0000 (11:21 +0800)]
fsl/sata: Replace sprintf() with snprintf()
Function 'sprintf' does not check buffer boundaries but outputs
to the buffer of fixed size which could potentially cause buffer
overflow. Use a safer function to replace it.
Matt Porter [Tue, 5 May 2015 19:00:23 +0000 (15:00 -0400)]
common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
projects / u-boot / log