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u-boot
8 years agoarm: omap-common: add secure rom call API for secure devices
Andreas Dannenberg [Mon, 27 Jun 2016 14:19:18 +0000 (09:19 -0500)]
arm: omap-common: add secure rom call API for secure devices

Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
simply calls the omap_smc_sec routine.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: omap-common: add secure smc entry
Daniel Allred [Mon, 27 Jun 2016 14:19:17 +0000 (09:19 -0500)]
arm: omap-common: add secure smc entry

Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: cache: add missing dummy functions for when dcache disabled
Daniel Allred [Mon, 27 Jun 2016 14:19:16 +0000 (09:19 -0500)]
arm: cache: add missing dummy functions for when dcache disabled

Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm64: add better and more generic spin-table support
Masahiro Yamada [Mon, 27 Jun 2016 10:31:05 +0000 (19:31 +0900)]
arm64: add better and more generic spin-table support

There are two enable methods supported by ARM64 Linux; psci and
spin-table.  The latter is simpler and helpful for quick SoC bring
up.  My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.

Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:

  - We must hard-code CPU_RELEASE_ADDR so that it matches the
    "cpu-release-addr" property in the DT that comes from the
    kernel tree.

  - The Documentation/arm64/booting.txt in Linux requires that
    the release address must be zero-initialized, but it is not
    cared by the common code in U-Boot.  We must do it in a board
    function.

  - There is no systematic way to protect the spin-table code from
    the kernel.  We are supposed to do it in a board specific manner,
    but it is difficult to predict where the spin-table code will be
    located after the relocation.  So, it also makes difficult to
    hard-code /memreserve/ in the DT of the kernel.

So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoRevert "armv8: Enable CPUECTLR.SMPEN for coherency"
Tom Rini [Thu, 14 Jul 2016 21:36:18 +0000 (17:36 -0400)]
Revert "armv8: Enable CPUECTLR.SMPEN for coherency"

Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.

This reverts commit d73718f3236c520a92efa401084c658e6cc067f3.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Tue, 12 Jul 2016 12:15:17 +0000 (08:15 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

8 years agox86: link: Correct a failure in DRAM init
Simon Glass [Mon, 11 Jul 2016 15:30:55 +0000 (09:30 -0600)]
x86: link: Correct a failure in DRAM init

With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.

Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add Advantech SOM-DB5800/SOM-6867 support
George McCollister [Tue, 21 Jun 2016 17:07:33 +0000 (12:07 -0500)]
x86: Add Advantech SOM-DB5800/SOM-6867 support

Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: baytrail: acpi: Hide internal UART per GNVS setting
Bin Meng [Fri, 17 Jun 2016 09:13:17 +0000 (02:13 -0700)]
x86: baytrail: acpi: Hide internal UART per GNVS setting

If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: acpi: Pack global NVS into ACPI table
Bin Meng [Fri, 17 Jun 2016 09:13:16 +0000 (02:13 -0700)]
x86: acpi: Pack global NVS into ACPI table

Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: quark: Introduce ACPI global NVS
Bin Meng [Fri, 17 Jun 2016 09:13:15 +0000 (02:13 -0700)]
x86: quark: Introduce ACPI global NVS

This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: baytrail: Introduce ACPI global NVS
Bin Meng [Fri, 17 Jun 2016 09:13:14 +0000 (02:13 -0700)]
x86: baytrail: Introduce ACPI global NVS

This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: conga-qeval20-qa3: Add support for internal UART
Stefan Roese [Wed, 15 Jun 2016 12:15:25 +0000 (14:15 +0200)]
x86: conga-qeval20-qa3: Add support for internal UART

This patch adds support to enable and use the internal BayTrail UART
instead of the one integrated in the Super IO Winbond chip. For this,
a 2nd defconfig file is added.

This is useful for tests done for the congatec SoM used on baseboards
without such a Super IO chip.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UART
Bin Meng [Wed, 15 Jun 2016 04:33:24 +0000 (21:33 -0700)]
x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UART

For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: baytrail: Introduce a Kconfig option for the internal UART
Bin Meng [Wed, 15 Jun 2016 04:33:23 +0000 (21:33 -0700)]
x86: baytrail: Introduce a Kconfig option for the internal UART

There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.

So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agopci: Add board_ prefix to should_load_oprom() and make it weak
Bin Meng [Tue, 14 Jun 2016 09:02:40 +0000 (02:02 -0700)]
pci: Add board_ prefix to should_load_oprom() and make it weak

For consistency with board_should_run_oprom(), do the same to
should_load_oprom(). Board support codes can provide this one
to override the default weak one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agopci: Make load_oprom and run_oprom independent
Bin Meng [Tue, 14 Jun 2016 09:02:39 +0000 (02:02 -0700)]
pci: Make load_oprom and run_oprom independent

At present should_load_oprom() calls board_should_run_oprom() to
determine whether oprom should be loaded. But sometimes we just
want to load oprom without running. Make them independent.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agopci: Remove CONFIG_ALWAYS_LOAD_OPROM
Bin Meng [Tue, 14 Jun 2016 09:02:38 +0000 (02:02 -0700)]
pci: Remove CONFIG_ALWAYS_LOAD_OPROM

This option is defined at nowhere. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Mon, 11 Jul 2016 22:50:29 +0000 (18:50 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

8 years agotools: patman: Handle missing 'END' in non-last commit of a series
Bin Meng [Mon, 27 Jun 2016 06:24:32 +0000 (23:24 -0700)]
tools: patman: Handle missing 'END' in non-last commit of a series

The following python error:

Traceback (most recent call last):
  File "./tools/patman/patman", line 144, in <module>
    series = patchstream.FixPatches(series, args)
  File "./tools/patman/patchstream.py", line 477, in FixPatches
    commit = series.commits[count]
IndexError: list index out of range

is seen when:

- 'END' is missing in those tags
- those tags are put in the last part in a commit message
- the commit is not the last commit of the series

Add testing logic to see if a new commit starts.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agotools: patman: Handle missing blank line for 'Series-changes'
Bin Meng [Mon, 27 Jun 2016 06:24:31 +0000 (23:24 -0700)]
tools: patman: Handle missing blank line for 'Series-changes'

'Series-changes' uses blank line to indicate its end. If that is
missing, series internal state variable 'in_change' may be wrong.
Correct its state.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agotools: patman: Generate cover letter correctly when 'END' is missing
Bin Meng [Mon, 27 Jun 2016 06:24:30 +0000 (23:24 -0700)]
tools: patman: Generate cover letter correctly when 'END' is missing

If 'END' is missing in a 'Cover-letter' section, and that section
happens to show up at the very end of the commit message, and the
commit is the last commit of the series, patman fails to generate
cover letter for us. Handle this in CloseCommit of patchstream.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agotools: patman: Handle tag sections without an 'END'
Bin Meng [Mon, 27 Jun 2016 06:24:29 +0000 (23:24 -0700)]
tools: patman: Handle tag sections without an 'END'

'Cover-letter', 'Series-notes' and 'Commit-notes' tags require an
'END' to be put at the end of its section. If we forget to put an
'END' in those sections, and these sections are followed by another
patman tag, patman generates incorrect patches. This adds codes to
handle such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agotools: patman: Use cover_match for 'Cover-letter'
Bin Meng [Mon, 27 Jun 2016 06:24:28 +0000 (23:24 -0700)]
tools: patman: Use cover_match for 'Cover-letter'

Like other patman tags, use a new variable cover_match to indicate
a match for 'Cover-letter'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: Sort the uclass id in alphabetical order
Bin Meng [Wed, 22 Jun 2016 09:29:47 +0000 (02:29 -0700)]
dm: Sort the uclass id in alphabetical order

Some uclass ids are out of order. Per the comments, sort them
in alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agosandbox: Find keyboard driver using driver model
Simon Glass [Sun, 19 Jun 2016 23:33:15 +0000 (17:33 -0600)]
sandbox: Find keyboard driver using driver model

The cros-ec keyboard is always a child of the cros-ec node. Rather than
searching the device tree, looking at the children. Remove the compat string
which is now unused.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agofdt: x86: Tidy up a few COMPAT string definitions
Simon Glass [Sun, 19 Jun 2016 23:33:14 +0000 (17:33 -0600)]
fdt: x86: Tidy up a few COMPAT string definitions

The 'COMPAT_' part should appear only once so drop the duplicate part. It is
ignored anyway, but let's keep things consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agofdt: Add a note to avoid adding new compatible strings
Simon Glass [Sun, 19 Jun 2016 23:33:13 +0000 (17:33 -0600)]
fdt: Add a note to avoid adding new compatible strings

The list is shrinking and we should avoid adding new things. Instead, a
proper driver should be created with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agofdt: Drop unused exynos compatible strings
Simon Glass [Sun, 19 Jun 2016 23:33:12 +0000 (17:33 -0600)]
fdt: Drop unused exynos compatible strings

A few drivers have moved to driver model, so we can drop these strings.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
8 years agox86: fdt: Drop the unused compatible strings in fdtdec
Simon Glass [Sun, 19 Jun 2016 23:33:11 +0000 (17:33 -0600)]
x86: fdt: Drop the unused compatible strings in fdtdec

We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agocommon: block: fix compiler error with CONFIG_FASTBOOT_FLASH_MMC_DEV
Xu Ziyuan [Wed, 15 Jun 2016 08:56:18 +0000 (16:56 +0800)]
common: block: fix compiler error with CONFIG_FASTBOOT_FLASH_MMC_DEV

This fixes the following compiler error:

common/fb_mmc.c: In function ‘fb_mmc_erase’:
common/fb_mmc.c:209:17: error: ‘struct blk_desc’ has no member named
‘block_erase’

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: gpio: MPC85XX GPIO platform data support
Hamish Martin [Mon, 13 Jun 2016 22:17:05 +0000 (10:17 +1200)]
dm: gpio: MPC85XX GPIO platform data support

Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
         {
                 .addr = 0x130000,
                 .ngpios = 32,
         },
         {
                 .addr = 0x131000,
                 .ngpios = 32,
         },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
         { "gpio_mpc85xx", &gpio_blocks[0] },
         { "gpio_mpc85xx", &gpio_blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: dfu: mmc: Support CONFIG_BLK in DFU for MMC
Simon Glass [Mon, 13 Jun 2016 05:30:33 +0000 (23:30 -0600)]
dm: dfu: mmc: Support CONFIG_BLK in DFU for MMC

Update the method of accessing the block device so that it works with
CONFIG_BLK enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: spl: mmc: Support CONFIG_BLK in SPL MMC
Simon Glass [Mon, 13 Jun 2016 05:30:32 +0000 (23:30 -0600)]
dm: spl: mmc: Support CONFIG_BLK in SPL MMC

Update the method of accessing the block device so that it works with
CONFIG_BLK enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: msmsdhic: Drop old MMC code
Simon Glass [Mon, 13 Jun 2016 05:30:31 +0000 (23:30 -0600)]
dm: mmc: msmsdhic: Drop old MMC code

Now that we have fully moved to driver model, drop the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: Move dragonboard410c to use CONFIG_BLK and CONFIG_DM_MMC_OPS
Simon Glass [Mon, 13 Jun 2016 05:30:30 +0000 (23:30 -0600)]
dm: mmc: Move dragonboard410c to use CONFIG_BLK and CONFIG_DM_MMC_OPS

Update this board to use driver model for block devices and MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: msm_sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS
Simon Glass [Mon, 13 Jun 2016 05:30:29 +0000 (23:30 -0600)]
dm: mmc: msm_sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS

Add support for using driver model for block devices and MMC operations in
this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS
Simon Glass [Mon, 13 Jun 2016 05:30:28 +0000 (23:30 -0600)]
dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS

Add support for using driver model for block devices and MMC operations in
this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: sdhci: Refactor configuration setup to support DM
Simon Glass [Mon, 13 Jun 2016 05:30:27 +0000 (23:30 -0600)]
dm: mmc: sdhci: Refactor configuration setup to support DM

Move the configuration setting into a separate function which can be used by
the driver-model code.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: sandbox: Convert to use CONFIG_CMD_MMC_OPS
Simon Glass [Mon, 13 Jun 2016 05:30:26 +0000 (23:30 -0600)]
dm: sandbox: Convert to use CONFIG_CMD_MMC_OPS

Update the sandbox MMC emulation to use driver model for MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Add MAINTAINER files for kylin_rk3036, evb_rk3036
Simon Glass [Mon, 13 Jun 2016 05:30:25 +0000 (23:30 -0600)]
rockchip: Add MAINTAINER files for kylin_rk3036, evb_rk3036

These boards should have maintainer entries. Add them.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boards
Simon Glass [Mon, 13 Jun 2016 05:30:24 +0000 (23:30 -0600)]
dm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boards

Enable this option to move rockchip over to use driver model for MMC
operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: dwmmc: Support CONFIG_DM_MMC_OPS
Simon Glass [Mon, 13 Jun 2016 05:30:23 +0000 (23:30 -0600)]
dm: mmc: dwmmc: Support CONFIG_DM_MMC_OPS

Add support to dwmmc for using driver model for MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: Add a way to use driver model for MMC operations
Simon Glass [Mon, 13 Jun 2016 05:30:22 +0000 (23:30 -0600)]
dm: mmc: Add a way to use driver model for MMC operations

The driver model conversion for MMC has moved in small steps. The first step
was to have an MMC device (CONFIG_DM_MMC). The second was to use a child
block device (CONFIG_BLK). The final one is to use driver model for MMC
operations (CONFIG_DM_MMC_OP). Add support for this.

The immediate priority is to make all boards that use DM_MMC also use those
other two options. This will allow them to be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Disable CONFIG_SDHCI
Simon Glass [Mon, 13 Jun 2016 05:30:21 +0000 (23:30 -0600)]
rockchip: Disable CONFIG_SDHCI

This option is not actually needed for rockchip boards. Drop it, since it
will not support driver-model MMC operation support.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agommc: Move tracing code into separate functions
Simon Glass [Mon, 13 Jun 2016 05:30:20 +0000 (23:30 -0600)]
mmc: Move tracing code into separate functions

Move this code into separate functions so that it can be used from the uclass
also. Add static inline versions for when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: rockchip: Support only CONFIG_BLK
Simon Glass [Mon, 13 Jun 2016 05:30:19 +0000 (23:30 -0600)]
dm: mmc: rockchip: Support only CONFIG_BLK

Since all Rockchip boards use CONFIG_BLK, we can remove this old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agommc: Move MMC boot code into its own file
Simon Glass [Mon, 13 Jun 2016 05:30:18 +0000 (23:30 -0600)]
mmc: Move MMC boot code into its own file

Rather than having an #ifdef in the main mmc.c file, control this feature
from the Makefile by moving the code into its own file.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: Move non-CONFIG_BLK code into mmc_legacy.c
Simon Glass [Mon, 13 Jun 2016 05:30:17 +0000 (23:30 -0600)]
dm: mmc: Move non-CONFIG_BLK code into mmc_legacy.c

Rather than having #ifdef in mmc.c, move this code into the legacy file.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: Move CONFIG_BLK code into the mmc uclass
Simon Glass [Mon, 13 Jun 2016 05:30:16 +0000 (23:30 -0600)]
dm: mmc: Move CONFIG_BLK code into the mmc uclass

Rather than having #ifdef in mmc.c, move this code into the uclass file.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agommc: Add function declarations for mmc_bread() and mmc_switch_part()
Simon Glass [Mon, 13 Jun 2016 05:30:15 +0000 (23:30 -0600)]
mmc: Add function declarations for mmc_bread() and mmc_switch_part()

These private functions are used both in the driver-model implementation and
in the legacy code. Add them to the header.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Use 'select' instead of defaults in Kconfig
Simon Glass [Mon, 13 Jun 2016 05:30:14 +0000 (23:30 -0600)]
rockchip: Use 'select' instead of defaults in Kconfig

Rockchip uses driver model for all subsystems. Specify this in the arm
Kconfig rather than as defaults in the Rockchip Kconfig. This means that
boards cannot turn these options off, which seems correct.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: mmc: dwmmc: Add comments to the dwmmc setup functions
Simon Glass [Mon, 13 Jun 2016 05:30:13 +0000 (23:30 -0600)]
dm: mmc: dwmmc: Add comments to the dwmmc setup functions

These comments were missed when the original code was written. Add them to
help people port their drivers over.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoPrepare v2016.07 v2016.07
Tom Rini [Mon, 11 Jul 2016 19:01:01 +0000 (15:01 -0400)]
Prepare v2016.07

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agodoc: ARMv8: add README.pine64
Andre Przywara [Fri, 8 Jul 2016 14:25:23 +0000 (15:25 +0100)]
doc: ARMv8: add README.pine64

Since we lack information about the DRAM initialization for the
Allwinner A64 SoC, booting any A64 based board like the Pine64 is a bit
involved at the moment.
Add a README file to explain the process.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to board/sunxi/ from doc/]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agomkimage -l is broken for images after gpimage
Stefano Babic [Mon, 11 Jul 2016 14:09:48 +0000 (16:09 +0200)]
mkimage -l is broken for images after gpimage

Because a gpimage cannot be detected, a false
GP header is printed instead of checking
for further image types.

Move gpimage as last to be linked, letting check
all other image types and printing a GP header just
in case no image is detected.

Signed-off-by: Stefano Babic <sbabic@denx.de>
8 years agogit-mailrc: add rockchip alias
jk.kernel@gmail.com [Sat, 9 Jul 2016 13:12:04 +0000 (21:12 +0800)]
git-mailrc: add rockchip alias

It's easier to Cc rockchip maintainers on rockchip-releated patches.

Signed-off-by: jk <jk.kernel@gmail.com>
8 years agodm: spi: Read default speed and mode values from DT
Vignesh R [Wed, 6 Jul 2016 04:34:28 +0000 (10:04 +0530)]
dm: spi: Read default speed and mode values from DT

In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
Vignesh R [Wed, 6 Jul 2016 04:56:03 +0000 (10:26 +0530)]
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodefconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
Vignesh R [Wed, 6 Jul 2016 04:50:58 +0000 (10:20 +0530)]
defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller

Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also
enable Spansion flash support to access s25fl512s flash present on K2G
QSPI bus.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: K2G: Add support for QSPI controller
Vignesh R [Wed, 6 Jul 2016 04:50:57 +0000 (10:20 +0530)]
ARM: dts: K2G: Add support for QSPI controller

K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: cadence_quadspi: Enable QUAD mode based on DT data
Vignesh R [Wed, 6 Jul 2016 04:50:56 +0000 (10:20 +0530)]
spi: cadence_quadspi: Enable QUAD mode based on DT data

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: cadence_qspi_apb: Support 32 bit AHB address
Vignesh R [Wed, 6 Jul 2016 04:50:55 +0000 (10:20 +0530)]
spi: cadence_qspi_apb: Support 32 bit AHB address

AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodefconfig: k2g_evm_defconfig: enable SPI driver model
Vignesh R [Wed, 6 Jul 2016 04:29:06 +0000 (09:59 +0530)]
defconfig: k2g_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2G SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: k2g: add support for Davinci SPI controller
Vignesh R [Wed, 6 Jul 2016 04:29:05 +0000 (09:59 +0530)]
ARM: dts: k2g: add support for Davinci SPI controller

K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodefconfig: k2l_evm_defconfig: enable SPI driver model
Vignesh R [Wed, 6 Jul 2016 04:29:04 +0000 (09:59 +0530)]
defconfig: k2l_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2L SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: k2l: Enable Davinci SPI controller
Vignesh R [Wed, 6 Jul 2016 04:29:03 +0000 (09:59 +0530)]
ARM: dts: k2l: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodefconfig: k2e_evm_defconfig: enable SPI driver model
Vignesh R [Wed, 6 Jul 2016 04:29:02 +0000 (09:59 +0530)]
defconfig: k2e_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2E SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: k2e: Enable Davinci SPI controller
Vignesh R [Wed, 6 Jul 2016 04:29:01 +0000 (09:59 +0530)]
ARM: dts: k2e: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodefconfig: k2hk_evm_defconfig: enable SPI driver model
Vignesh R [Wed, 6 Jul 2016 04:29:00 +0000 (09:59 +0530)]
defconfig: k2hk_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2HK SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: k2hk: Enable Davinci SPI controller
Vignesh R [Wed, 6 Jul 2016 04:28:59 +0000 (09:58 +0530)]
ARM: dts: k2hk: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: keystone2: add SPI aliases for davinci SPI nodes
Vignesh R [Wed, 6 Jul 2016 04:28:58 +0000 (09:58 +0530)]
ARM: dts: keystone2: add SPI aliases for davinci SPI nodes

Add aliases for SPI nodes in order for it to be probed by the DM
framework.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agokeystone2: spi: do not define DM_SPI and DM_SPI_FLASH for SPL build
Vignesh R [Wed, 6 Jul 2016 04:28:57 +0000 (09:58 +0530)]
keystone2: spi: do not define DM_SPI and DM_SPI_FLASH for SPL build

Since Keystone2 devices do not have support DM in SPL, do not define
DM_SPI and DM_SPI_FLASH for SPL build.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: davinci_spi: Convert to driver to adapt to DM
Vignesh R [Wed, 6 Jul 2016 04:28:56 +0000 (09:58 +0530)]
spi: davinci_spi: Convert to driver to adapt to DM

Convert davinci_spi driver so that it complies with SPI DM framework.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agodm: core: implement dev_map_physmem()
Vignesh R [Wed, 6 Jul 2016 04:28:55 +0000 (09:58 +0530)]
dm: core: implement dev_map_physmem()

This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agoarmv8: Enable CPUECTLR.SMPEN for coherency
Mingkai Hu [Thu, 7 Jul 2016 04:22:12 +0000 (12:22 +0800)]
armv8: Enable CPUECTLR.SMPEN for coherency

For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agotest/py: support 'memstart =' in u_boot_utils.find_ram_base()
Daniel Schwierzeck [Wed, 6 Jul 2016 10:44:22 +0000 (12:44 +0200)]
test/py: support 'memstart =' in u_boot_utils.find_ram_base()

Some archs like MIPS or PPC have a different 'bdinfo' output
than ARM regarding the memory configuration. Also support
'memstart = 0x*' in u_boot_utils.find_ram_base() to make
all tests requiring the RAM base working on those archs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agotest/py: strip VT100 codes from match buffer
Stephen Warren [Wed, 6 Jul 2016 16:34:30 +0000 (10:34 -0600)]
test/py: strip VT100 codes from match buffer

Prior to this patch, any VT100 codes emitted by U-Boot are considered part
of a command's output, which often causes tests to fail. For example,
test_env_echo_exists executes printenv, and then considers any text on a
line before an = sign as a valid U-Boot environment variable name. This
includes any VT100 codes emitted. When the test later attempts to use that
variable, the name would be invalid since it includes the VT100 codes.
Solve this by stripping VT100 codes from the match buffer, so they are
never seen by higher level test code.

The codes are still logged unmodified, so that users can expect U-Boot's
exact output without interference. This does clutter the log file a bit.
However, it allows users to see exactly what U-Boot emitted rather than a
modified version, which hopefully is better for debugging. It's also much
simpler to implement, since logging happens as soon as text is received,
and so stripping the VT100 codes from the log would require handling
reception and stripping of partial VT100 codes.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agoarm: Fix setjmp (again)
Alexander Graf [Tue, 5 Jul 2016 18:37:17 +0000 (20:37 +0200)]
arm: Fix setjmp (again)

Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp
code path with thumv1. Unfortunately it missed a constraint that the adr
instruction can only refer to 4 byte aligned offsets.

So this patch adds the required alignment hooks to make compilation
work again even when setjmp doesn't happen to be 4 byte aligned.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Tom Rini <trini@konsulko.com>
8 years agoSPL: tiny-printf: avoid any BSS usage
Andre Przywara [Fri, 8 Jul 2016 14:18:35 +0000 (15:18 +0100)]
SPL: tiny-printf: avoid any BSS usage

As printf calls may be executed quite early, we should avoid using any
BSS stored variables, since some boards put BSS in DRAM, which may not
have been initialised yet.
Explicitly mark those "static global" variables as belonging to the
.data section, to keep tiny-printf clear of any BSS usage.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
8 years agotest/py: fix CONFIG_ tests
Stephen Warren [Wed, 6 Jul 2016 15:04:08 +0000 (09:04 -0600)]
test/py: fix CONFIG_ tests

Some CONFIG_ variables were recently renamed, but test/py wasn't updated
to match. This causes some tests to be skipped. Fix test/py so the tests
are run.

Fixes: 11636258981a ("Rename reset to sysreset")
Fixes: f1f9d4fac527 ("hush: complete renaming CONFIG_SYS_HUSH_PARSER to CONFIG_HUSH_PARSER")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agommc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()
Mateusz Kulikowski [Sun, 26 Jun 2016 20:43:55 +0000 (22:43 +0200)]
mmc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()

MMC core expects (now) valid mmc->dev pointer.
During conversion in commit cffe5d86 not every driver was updated.

This patch fixes crash while accessing MMC on
boards using Qualcomm SDHCI controller.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 7 Jul 2016 13:58:41 +0000 (09:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

8 years agopowerpc: mpc85xx: kmp204x: Fix compiling error for usb errata
York Sun [Wed, 6 Jul 2016 23:39:51 +0000 (16:39 -0700)]
powerpc: mpc85xx: kmp204x: Fix compiling error for usb errata

Commit 9262367 moves USB errata workaround into a C file. This
causes compiling error for kmcoge4 and kmlion1. To enable the
errata workaround, define CONFIG_USB_EHCI_FSL in common header.

Signed-off-by: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ed Swarthout <Ed.Swarthout@nxp.com>
Cc: Sriram Dash <sriram.dash@nxp.com>
Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Wed, 6 Jul 2016 19:55:36 +0000 (15:55 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Wed, 6 Jul 2016 19:55:21 +0000 (15:55 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net

8 years agonet: rtl8169: Fix return value for rtl_send_common
Oleksandr Tymoshenko [Fri, 1 Jul 2016 20:22:00 +0000 (13:22 -0700)]
net: rtl8169: Fix return value for rtl_send_common

Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.

Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.

Cc: Stephen Warren <swarren@nvidia.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: Fix incorrect RPC packets on 64-bit systems
Ralf Hubert [Fri, 1 Jul 2016 11:19:51 +0000 (13:19 +0200)]
net: Fix incorrect RPC packets on 64-bit systems

This patch fixes incorrect RPC packet layout caused by
'long' type size difference on 64 and 32-bit architectures.

Signed-off-by: Ralf Hubert <r.hubert@technisat.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodriver: net: phylib: add support for aquantia AQR106/107 PHY
Mingkai Hu [Fri, 1 Jul 2016 11:03:23 +0000 (19:03 +0800)]
driver: net: phylib: add support for aquantia AQR106/107 PHY

This patch adds support for aquantia AQR106/107 PHY.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: designware: Make driver independent from DM_GPIO again
Alexey Brodkin [Mon, 27 Jun 2016 10:17:51 +0000 (13:17 +0300)]
net: designware: Make driver independent from DM_GPIO again

Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
 * dm_gpio_XXX()
 * gpio_request_by_name()

But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agocommon: Always include errno.h in common.h
Joe Hershberger [Mon, 4 Apr 2016 09:07:33 +0000 (04:07 -0500)]
common: Always include errno.h in common.h

We want people using errnos for errors instead of -1, so make it easy
by always including the definition of all the errnos.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agospi: spi-uclass: fix typo in debug output
Anatolij Gustschin [Thu, 21 Apr 2016 07:28:02 +0000 (09:28 +0200)]
spi: spi-uclass: fix typo in debug output

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agofdt: Drop some unused compatible strings
Simon Glass [Sun, 8 May 2016 22:55:22 +0000 (16:55 -0600)]
fdt: Drop some unused compatible strings

We have driver-model drivers for some of these now, so drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agotegra: video: Always use write-through cache on LCD
Simon Glass [Sun, 8 May 2016 22:55:21 +0000 (16:55 -0600)]
tegra: video: Always use write-through cache on LCD

This seems to give the best performance, so let's use it always.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agovideo: tegra: Move to using simple-panel and pwm-backlight
Simon Glass [Sun, 8 May 2016 22:55:20 +0000 (16:55 -0600)]
video: tegra: Move to using simple-panel and pwm-backlight

We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.

This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:

   - colibri
   - medcom-wide
   - paz00
   - tec

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agotegra: dts: Sync tegra20 device tree files with Linux
Simon Glass [Sun, 8 May 2016 22:55:19 +0000 (16:55 -0600)]
tegra: dts: Sync tegra20 device tree files with Linux

Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoerrno: Allow errno_str() to be used without CONFIG_ERRNO_STR
Simon Glass [Sun, 8 May 2016 22:55:18 +0000 (16:55 -0600)]
errno: Allow errno_str() to be used without CONFIG_ERRNO_STR

The pmic framework uses errno_str() and this requires board that use it to
enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide
a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build
error.

This will show as "(null)" when U-Boot prints it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoerrno: Add copyright header and header guard
Simon Glass [Sun, 8 May 2016 22:55:17 +0000 (16:55 -0600)]
errno: Add copyright header and header guard

Bring in a copyright for this file from cmd/pmic.c since this file was
submitted by the same author at around the same time. Also fix the missing
header guard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agopci: tegra: actually program REFCLK_CFG* on recent SoCs
Stephen Warren [Fri, 24 Jun 2016 14:36:04 +0000 (08:36 -0600)]
pci: tegra: actually program REFCLK_CFG* on recent SoCs

On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.

For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agopci: tegra: correctly program PADS_REFCLK registers
Stephen Warren [Tue, 21 Jun 2016 18:47:51 +0000 (12:47 -0600)]
pci: tegra: correctly program PADS_REFCLK registers

The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>