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8 years agorockchip: Add basic support for evb-rk3036 board
huang lin [Tue, 17 Nov 2015 06:20:28 +0000 (14:20 +0800)]
rockchip: Add basic support for evb-rk3036 board

This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one

8 years agorockchip: rk3036: Add core Soc start-up code
huang lin [Tue, 17 Nov 2015 06:20:27 +0000 (14:20 +0800)]
rockchip: rk3036: Add core Soc start-up code

rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288

8 years agorockchip: add rk3036 sdram driver
huang lin [Tue, 17 Nov 2015 06:20:26 +0000 (14:20 +0800)]
rockchip: add rk3036 sdram driver

add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: add early uart driver
huang lin [Tue, 17 Nov 2015 06:20:25 +0000 (14:20 +0800)]
rockchip: add early uart driver

add early uart driver so we can print debug message in
SPL stage

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: mmc: get the fifo mode and fifo depth property from dts
huang lin [Tue, 17 Nov 2015 06:20:24 +0000 (14:20 +0800)]
rockchip: mmc: get the fifo mode and fifo depth property from dts

rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
8 years agorockchip: mmc: use non-removable property to distinguish emmc and sdcard register
huang lin [Wed, 18 Nov 2015 01:37:25 +0000 (09:37 +0800)]
rockchip: mmc: use non-removable property to distinguish emmc and sdcard register

emmc and sdcard have different register address, use non-removeable property
to distinguish them.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agommc: dw_mmc: support fifo mode in dwc mmc driver
huang lin [Tue, 17 Nov 2015 06:20:22 +0000 (14:20 +0800)]
mmc: dw_mmc: support fifo mode in dwc mmc driver

some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agommc: dw_mmc: move data transfer as a separate function
huang lin [Tue, 17 Nov 2015 06:20:21 +0000 (14:20 +0800)]
mmc: dw_mmc: move data transfer as a separate function

the data transfer seem to long in the dwmci_send_cmd function,
so move this block as a separate funciton.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: Add pinctrl driver
huang lin [Tue, 17 Nov 2015 06:20:20 +0000 (14:20 +0800)]
rockchip: rk3036: Add pinctrl driver

Add a driver which support pin multiplexing setup for rk3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: Add a simple syscon driver
huang lin [Tue, 17 Nov 2015 06:20:19 +0000 (14:20 +0800)]
rockchip: rk3036: Add a simple syscon driver

Add a driver that provides access to system controllers

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: Add Soc reset driver
huang lin [Tue, 17 Nov 2015 06:20:18 +0000 (14:20 +0800)]
rockchip: rk3036: Add Soc reset driver

We can reset the Soc using some CRU (clock/reset unit) register.
Add support for this.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: Add header files for GRF
huang lin [Tue, 17 Nov 2015 06:20:17 +0000 (14:20 +0800)]
rockchip: rk3036: Add header files for GRF

GRF is the gereral register file. Add header files with register definitions.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: Add clock driver
huang lin [Tue, 17 Nov 2015 06:20:16 +0000 (14:20 +0800)]
rockchip: rk3036: Add clock driver

Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Bring in RK3036 device tree file includes and bindings
huang lin [Tue, 17 Nov 2015 06:20:15 +0000 (14:20 +0800)]
rockchip: Bring in RK3036 device tree file includes and bindings

Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: serial driver support rk3036
huang lin [Tue, 17 Nov 2015 06:20:14 +0000 (14:20 +0800)]
rockchip: serial driver support rk3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: core: Add SPL Kconfig for REGMAP and SYSCON
huang lin [Tue, 17 Nov 2015 06:20:13 +0000 (14:20 +0800)]
dm: core: Add SPL Kconfig for REGMAP and SYSCON

Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can
remove from SPL stage.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: add config decide whether to build common.c
huang lin [Tue, 17 Nov 2015 06:20:12 +0000 (14:20 +0800)]
rockchip: add config decide whether to build common.c

some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rename board-spl.c to rk3288-board-spl.c
huang lin [Tue, 17 Nov 2015 06:20:11 +0000 (14:20 +0800)]
rockchip: rename board-spl.c to rk3288-board-spl.c

since different rockchip soc need different spl file,
so rename board-spl.c.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
huang lin [Tue, 17 Nov 2015 06:20:10 +0000 (14:20 +0800)]
rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig

since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: add timer driver
huang lin [Tue, 17 Nov 2015 06:20:09 +0000 (14:20 +0800)]
rockchip: add timer driver

some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: firefly: Save the environment on SD card
Sjoerd Simons [Fri, 18 Sep 2015 21:49:12 +0000 (23:49 +0200)]
rockchip: firefly: Save the environment on SD card

Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Also load the initrd below 512M
Sjoerd Simons [Fri, 18 Sep 2015 21:49:11 +0000 (23:49 +0200)]
rockchip: Also load the initrd below 512M

Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: pci: Disable PCI compatibility functions by default
Simon Glass [Fri, 27 Nov 2015 02:51:30 +0000 (19:51 -0700)]
dm: pci: Disable PCI compatibility functions by default

We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: pci: Convert 'pci' command to driver model
Simon Glass [Fri, 27 Nov 2015 02:51:29 +0000 (19:51 -0700)]
dm: pci: Convert 'pci' command to driver model

Adjust this command to use the correct PCI functions, instead of the
compatibility layer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Move PCI header output code into its own function
Simon Glass [Fri, 27 Nov 2015 02:51:28 +0000 (19:51 -0700)]
pci: Move PCI header output code into its own function

We want to share this code with the driver model version, so put it in a
separate function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Use a separate 'dev' variable for the PCI device
Simon Glass [Fri, 27 Nov 2015 02:51:27 +0000 (19:51 -0700)]
pci: Use a separate 'dev' variable for the PCI device

In the 'pci' command, add a separate variable to hold the PCI device. When
this code is converted to driver model, this variable will be used to hold a
struct udevice instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Use common functions to read/write config
Simon Glass [Fri, 27 Nov 2015 02:51:26 +0000 (19:51 -0700)]
pci: Use common functions to read/write config

Currently we use switch() and access PCI configuration via several
functions, one for each data size. Adjust the code to use generic functions,
where the data size is a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Tidy up function comments in cmd_pci.c
Simon Glass [Fri, 27 Nov 2015 02:51:25 +0000 (19:51 -0700)]
pci: Tidy up function comments in cmd_pci.c

The function comments use an old style and some are incorrect. Update them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: pci: Reorder functions in cmd_pci.c
Simon Glass [Fri, 27 Nov 2015 02:51:24 +0000 (19:51 -0700)]
dm: pci: Reorder functions in cmd_pci.c

Before converting this to driver model, reorder the code to avoid forward
function declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: pci: Move common auto-config functions to a common file
Simon Glass [Fri, 27 Nov 2015 02:51:23 +0000 (19:51 -0700)]
dm: pci: Move common auto-config functions to a common file

Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: pci: Rename pci_auto.c to pci_auto_old.c
Simon Glass [Fri, 27 Nov 2015 02:51:22 +0000 (19:51 -0700)]
dm: pci: Rename pci_auto.c to pci_auto_old.c

This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: pci: Add a comment about how to find struct pci_controller
Simon Glass [Fri, 27 Nov 2015 02:51:21 +0000 (19:51 -0700)]
dm: pci: Add a comment about how to find struct pci_controller

With driver mode, struct pci_controller is stored as uclass-private data.
Add a comment to that effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Refactor the pciinfo() function
Simon Glass [Fri, 27 Nov 2015 02:51:20 +0000 (19:51 -0700)]
pci: Refactor the pciinfo() function

This function uses macros to output data. It seems better to use a table of
registers rather than macro-based code generation. It also reduces the
code/data size by 2KB on ARM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Use a separate variable for the bus number
Simon Glass [Fri, 27 Nov 2015 02:51:19 +0000 (19:51 -0700)]
pci: Use a separate variable for the bus number

At present in do_pci(), bdf can either mean a bus number or a PCI bus number.
Use separate variables instead to reduce confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Use a common return in command processing
Simon Glass [Fri, 27 Nov 2015 02:51:18 +0000 (19:51 -0700)]
pci: Use a common return in command processing

Adjust the commands to return from the same place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: tegra: pci: Convert tegra boards to driver model for PCI
Simon Glass [Fri, 20 Nov 2015 03:27:02 +0000 (20:27 -0700)]
dm: tegra: pci: Convert tegra boards to driver model for PCI

Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Add a function to find the regions for a PCI bus
Simon Glass [Fri, 20 Nov 2015 03:27:01 +0000 (20:27 -0700)]
dm: pci: Add a function to find the regions for a PCI bus

This function looks up the controller and returns a pointer to each region
type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Add a function to get the controller for a bus
Simon Glass [Fri, 20 Nov 2015 03:27:00 +0000 (20:27 -0700)]
dm: pci: Add a function to get the controller for a bus

A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Add functions to emulate 8- and 16-bit access
Simon Glass [Fri, 20 Nov 2015 03:26:59 +0000 (20:26 -0700)]
dm: pci: Add functions to emulate 8- and 16-bit access

Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Support decoding ranges with duplicate entries
Simon Glass [Fri, 20 Nov 2015 03:26:58 +0000 (20:26 -0700)]
dm: pci: Support decoding ranges with duplicate entries

At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.

There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).

We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Set up the SDRAM mapping correctly
Simon Glass [Fri, 20 Nov 2015 03:26:57 +0000 (20:26 -0700)]
dm: pci: Set up the SDRAM mapping correctly

SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.

This needs testing on other platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM
Simon Glass [Fri, 20 Nov 2015 03:26:56 +0000 (20:26 -0700)]
dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM

This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.

This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
Simon Glass [Fri, 20 Nov 2015 03:26:55 +0000 (20:26 -0700)]
dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig

Move this option to Kconfig and fix up all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agoARM: tegra: refactor common Kconfig options
Stephen Warren [Mon, 23 Nov 2015 17:32:01 +0000 (10:32 -0700)]
ARM: tegra: refactor common Kconfig options

This makes it easier to select common options in a single place, rather
than having to add them separately for different SoCs or architectures.

The lists of select statements are now also sorted for easy searching.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agox86: tsc: Move tsc_timer.c to drivers/timer
Bin Meng [Fri, 13 Nov 2015 08:11:24 +0000 (00:11 -0800)]
x86: tsc: Move tsc_timer.c to drivers/timer

To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agox86: tsc: Remove legacy timer codes
Bin Meng [Fri, 13 Nov 2015 08:11:23 +0000 (00:11 -0800)]
x86: tsc: Remove legacy timer codes

Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.

Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agox86: Convert to use driver model timer
Bin Meng [Fri, 13 Nov 2015 08:11:22 +0000 (00:11 -0800)]
x86: Convert to use driver model timer

Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: timer: Avoid using timer before it is ready
Simon Glass [Sun, 29 Nov 2015 05:16:35 +0000 (22:16 -0700)]
dm: timer: Avoid using timer before it is ready

At present bootstage will try to read the timer very early after relocation.
When driver model is used to provide the timer, we cannot read it until
driver model is ready. Correct this by adding a separate stage for the
post-relocation bootstage init.

This fixes booting on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agox86: tsc: Add driver model timer support
Bin Meng [Fri, 13 Nov 2015 08:11:21 +0000 (00:11 -0800)]
x86: tsc: Add driver model timer support

This adds driver model timer support to x86 tsc timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agox86: tsc: Use notrace from <linux/compiler.h>
Bin Meng [Fri, 13 Nov 2015 08:11:20 +0000 (00:11 -0800)]
x86: tsc: Use notrace from <linux/compiler.h>

Replace __attribute__((no_instrument_function)) with notrace from
<linux/compiler.h>.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agox86: Remove MIN_PORT80_KCLOCKS_DELAY
Bin Meng [Fri, 13 Nov 2015 08:11:19 +0000 (00:11 -0800)]
x86: Remove MIN_PORT80_KCLOCKS_DELAY

This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: timer: Support 64-bit counter
Bin Meng [Tue, 24 Nov 2015 20:31:17 +0000 (13:31 -0700)]
dm: timer: Support 64-bit counter

There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agotimer: sandbox: Use device tree to pass the clock frequency
Bin Meng [Fri, 13 Nov 2015 08:11:17 +0000 (00:11 -0800)]
timer: sandbox: Use device tree to pass the clock frequency

We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agotimer: altera: Remove the codes to get clock frequency
Bin Meng [Fri, 13 Nov 2015 08:11:16 +0000 (00:11 -0800)]
timer: altera: Remove the codes to get clock frequency

Since we have timer uclass to get clock frequency for us, remove
the custom version in the altera timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: timer: Implement pre_probe()
Bin Meng [Fri, 13 Nov 2015 08:11:15 +0000 (00:11 -0800)]
dm: timer: Implement pre_probe()

Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodm: timer: Fix several nits
Bin Meng [Fri, 13 Nov 2015 08:11:14 +0000 (00:11 -0800)]
dm: timer: Fix several nits

This changes 'Timer' to 'timer' at several places.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-atmel
Tom Rini [Mon, 30 Nov 2015 23:13:10 +0000 (18:13 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel

8 years agoarm: at91/spl: atmel_sfr: move saic redirect to separate file
Wenyou Yang [Thu, 5 Nov 2015 08:37:53 +0000 (16:37 +0800)]
arm: at91/spl: atmel_sfr: move saic redirect to separate file

To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c

Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: matrix: use matrix slave id macros
Wenyou Yang [Thu, 5 Nov 2015 08:37:52 +0000 (16:37 +0800)]
arm: at91/spl: matrix: use matrix slave id macros

To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: matrix: remove security peripheral select code
Wenyou Yang [Thu, 5 Nov 2015 08:37:51 +0000 (16:37 +0800)]
arm: at91/spl: matrix: remove security peripheral select code

Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: matrix: remove matrix write protection code
Wenyou Yang [Thu, 5 Nov 2015 08:37:50 +0000 (16:37 +0800)]
arm: at91/spl: matrix: remove matrix write protection code

On processor reset, the matrix write protection is disabled,
so no need to disable/enable write protection when writing
the matrix registers.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: matrix: move matrix init to separate file
Wenyou Yang [Thu, 5 Nov 2015 08:37:49 +0000 (16:37 +0800)]
arm: at91/spl: matrix: move matrix init to separate file

To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: atmel: Add SAMA5D2 Xplained board
Wenyou Yang [Fri, 30 Oct 2015 01:55:52 +0000 (09:55 +0800)]
arm: atmel: Add SAMA5D2 Xplained board

The board supports following features:
 - Boot media support: SD card/e.MMC/SPI flash,
 - Support LCD display (optional, disabled by default),
 - Support ethernet,
 - Support USB mass storage.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agogpio: atmel: Add the PIO4 driver support
Wenyou Yang [Wed, 4 Nov 2015 06:25:13 +0000 (14:25 +0800)]
gpio: atmel: Add the PIO4 driver support

The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Mon, 30 Nov 2015 20:18:30 +0000 (15:18 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agoarmv8: fsl-layerscape: Fix early MMU table for nand boot
York Sun [Wed, 25 Nov 2015 22:56:40 +0000 (14:56 -0800)]
armv8: fsl-layerscape: Fix early MMU table for nand boot

The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
8 years agoarmv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddr
Alison Wang [Fri, 13 Nov 2015 08:49:06 +0000 (16:49 +0800)]
armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddr

As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agonet: phy: added aquantia PHY AQR405 support
Shaohui Xie [Tue, 10 Nov 2015 11:16:33 +0000 (19:16 +0800)]
net: phy: added aquantia PHY AQR405 support

The phy can share driver with other aquantia PHYs, so we only
add PHY ID.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: ls2085a: Add workaround of errata A009635
Prabhakar Kushwaha [Thu, 5 Nov 2015 06:30:14 +0000 (12:00 +0530)]
armv8: ls2085a: Add workaround of errata A009635

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoboard/ls2080qds: Fix typo in README for QSGMII riser card
Prabhakar Kushwaha [Thu, 5 Nov 2015 04:12:31 +0000 (09:42 +0530)]
board/ls2080qds: Fix typo in README for QSGMII riser card

DPMACx to PHY mapping for SGMII is mentioned as QSGMII.

So fix typo in README for QSGMII rise card.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Change from ls2085aqds to ls2080aqds]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board
Alison Wang [Thu, 5 Nov 2015 03:16:26 +0000 (11:16 +0800)]
arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board

As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.

To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.

For the same reason, initrd_high is set to the value of 0xffffffff too.

This patch is to update fdt_high and initrd_high for LS1021AQDS board.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: fsl-layerscape: Fix "cpu release" command
York Sun [Thu, 12 Nov 2015 20:38:21 +0000 (12:38 -0800)]
armv8: fsl-layerscape: Fix "cpu release" command

When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodrivers/ddr/fsl: Fix typo in BIST test for DDR4
York Sun [Fri, 6 Nov 2015 17:58:46 +0000 (09:58 -0800)]
drivers/ddr/fsl: Fix typo in BIST test for DDR4

BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
8 years agoarmv8/layerscape: Update MMU table with execute-never bits
Alison Wang [Thu, 5 Nov 2015 03:15:49 +0000 (11:15 +0800)]
armv8/layerscape: Update MMU table with execute-never bits

For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
8 years agodrivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
York Sun [Wed, 4 Nov 2015 17:53:10 +0000 (09:53 -0800)]
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb: add USB support
Gong Qianyu [Wed, 11 Nov 2015 09:58:40 +0000 (17:58 +0800)]
armv8/ls1043ardb: add USB support

Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb: add DSPI support
Gong Qianyu [Wed, 11 Nov 2015 09:58:39 +0000 (17:58 +0800)]
armv8/ls1043ardb: add DSPI support

Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043aqds: dts: add dtb support
Gong Qianyu [Wed, 11 Nov 2015 09:58:38 +0000 (17:58 +0800)]
armv8/ls1043aqds: dts: add dtb support

Reuse the dts files from ls1043a linux kernel.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043aqds: add LS1043AQDS board support
Shaohui Xie [Wed, 11 Nov 2015 09:58:37 +0000 (17:58 +0800)]
armv8/ls1043aqds: add LS1043AQDS board support

LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb: dts: add dtb support
Gong Qianyu [Wed, 11 Nov 2015 09:58:36 +0000 (17:58 +0800)]
armv8/ls1043ardb: dts: add dtb support

Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/fsl-layerscape: Remove reference to gdata
Gong Qianyu [Wed, 11 Nov 2015 09:58:35 +0000 (17:58 +0800)]
armv8/fsl-layerscape: Remove reference to gdata

The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agopci/layerscape: add support for LS1043A PCIe LUT register access
Mingkai Hu [Wed, 11 Nov 2015 09:58:34 +0000 (17:58 +0800)]
pci/layerscape: add support for LS1043A PCIe LUT register access

The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: ls2085a: Add support of LS2085A SoC
Prabhakar Kushwaha [Mon, 9 Nov 2015 11:12:20 +0000 (16:42 +0530)]
armv8: ls2085a: Add support of LS2085A SoC

Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: LS2080A: Rename LS2085A to reflect LS2080A
Prabhakar Kushwaha [Mon, 9 Nov 2015 11:12:07 +0000 (16:42 +0530)]
armv8: LS2080A: Rename LS2085A to reflect LS2080A

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: ldpaa: Fix Rx buffer alignment
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:56:02 +0000 (12:26 +0530)]
driver: net: ldpaa: Fix Rx buffer alignment

MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"

Updating the DPNI Eth driver to comply with the restriction.

Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: ldpaa: Add debug information
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:56:01 +0000 (12:26 +0530)]
driver: net: ldpaa: Add debug information

Add following debug information in the driver
 - Get various DPNI counter values
 - Get link status of DPNI objects
 - Get information of both ends of connection (DPMAC - DPNI)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: ldpaa: Use DPMAC as net device
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:56:00 +0000 (12:26 +0530)]
driver: net: ldpaa: Use DPMAC as net device

As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.

Use DPMAC as net device where it represents physical lane.
Below modification done in driver
 - Use global DPNI object
 - Connect DPMAC to DPNI
 - Create and destroy DPMAC

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: Create DPAA2 object at run-time
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:59 +0000 (12:25 +0530)]
driver: net: fsl-mc: Create DPAA2 object at run-time

Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.

Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: Add DPAA2 commands to manage MC
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:58 +0000 (12:25 +0530)]
driver: net: fsl-mc: Add DPAA2 commands to manage MC

Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.

Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: Increase MC command timeout
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:57 +0000 (12:25 +0530)]
driver: net: fsl-mc: Increase MC command timeout

dpni_create API take takes more time as comapred to existing supported
APIs of MC Flib.
So increase MC command timeout.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: ldpaa: Add api to return linked PHY ID of DPMAC
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:56 +0000 (12:25 +0530)]
driver: ldpaa: Add api to return linked PHY ID of DPMAC

DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.

So Add an api to return linked PHY ID of DPMAC object.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: ls2085aqds: Print function name during SerDes error
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:55 +0000 (12:25 +0530)]
armv8: ls2085aqds: Print function name during SerDes error

Print function name along with SerDes Protocol during SerDes Protocol
not supported error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:54 +0000 (12:25 +0530)]
driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB

DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: Add create, destroy APIs in flibs
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:53 +0000 (12:25 +0530)]
driver: net: fsl-mc: Add create, destroy APIs in flibs

Current Management Complex Flibs does not support APIs for adding and
destroying the objects.

Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: lsch3: Fix lane protocol parsing logic
Prabhakar Kushwaha [Wed, 4 Nov 2015 06:55:52 +0000 (12:25 +0530)]
armv8: lsch3: Fix lane protocol parsing logic

Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
Alison Wang [Tue, 4 Aug 2015 01:55:37 +0000 (09:55 +0800)]
arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.

To fix the above issue, the generic physical timer is disabled
before jumping to the OS.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
Alison Wang [Wed, 15 Jul 2015 07:13:05 +0000 (15:13 +0800)]
arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot.  Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.  This causes the timer compare to fire 344 seconds
after u-boot configures it.  Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains.  Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoMerge git://git.denx.de/u-boot-socfpga
Tom Rini [Mon, 30 Nov 2015 13:30:14 +0000 (08:30 -0500)]
Merge git://git.denx.de/u-boot-socfpga

8 years agoarm: socfpga: Remove fsloadcmd from environment
Chin Liang See [Fri, 27 Nov 2015 13:32:40 +0000 (21:32 +0800)]
arm: socfpga: Remove fsloadcmd from environment

Remove fsloadcmd / ext2load as we are using load command
which use the corresponding latest file system command.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
8 years agoarm: socfpga: dts: Adding drvsel and smplsel to dts
Chin Liang See [Thu, 26 Nov 2015 01:44:11 +0000 (09:44 +0800)]
arm: socfpga: dts: Adding drvsel and smplsel to dts

Adding new node drvsel and smplsel for SDMMC

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>