Jagan Teki [Wed, 27 Sep 2017 17:33:10 +0000 (23:03 +0530)]
armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Thu, 28 Sep 2017 10:24:03 +0000 (18:24 +0800)]
rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 09:57:28 +0000 (17:57 +0800)]
rockchip: mkimage: add support for rk3128 soc
Add support for rk3128 package header in mkimage tool.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:59:56 +0000 (16:59 +0800)]
rockchip: clk: fix typo in rk322x clock driver
Fix typo RK322X/RK3036 in rk322x clock driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 10:48:12 +0000 (12:48 +0200)]
rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.
With this factored out, the spl_board_init function can not be
customised for each RK3399 board.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 25 Sep 2017 08:33:22 +0000 (16:33 +0800)]
rockchip: rk3188: ram: add support for 16bit row address
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed compile-error by declaring 'row':] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:38:22 +0000 (16:38 +0800)]
rockchip: rk322x: add sdram driver
Add driver for rk322x to support sdram initialize in SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:33 +0000 (16:11 +0800)]
rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:32 +0000 (16:11 +0800)]
rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:31 +0000 (16:11 +0800)]
rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:30 +0000 (16:11 +0800)]
rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Wed, 20 Sep 2017 11:50:13 +0000 (13:50 +0200)]
rockchip: imply ADC and SARADC_ROCKCHIP for Rockchip SOCs
Enable the Rockchip SARADC driver for all Rockchip SoCs.
Note that the SARADC peripheral is available on all SoCs except the
RK3036 and RK3228. However, as this is a DM-driver, enabling by
default will not cause any function problems (and can always be
changed from defconfig, if size is a concern).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: David Wu <david.wu@rock-chips.com>
David Wu [Wed, 20 Sep 2017 06:47:19 +0000 (14:47 +0800)]
rockchip: dts: Enable SARADC for rk3399-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:46:19 +0000 (14:46 +0800)]
rockchip: dts: Enable SARADC for rk3368-sheep
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:45:21 +0000 (14:45 +0800)]
rockchip: dts: Enable SARADC for rk3368-px5-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:44:23 +0000 (14:44 +0800)]
rockchip: dts: Enable SARADC for rk3328-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:43:08 +0000 (14:43 +0800)]
rockchip: dts: Enable SARADC for rk3288-popmetal
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:41:38 +0000 (14:41 +0800)]
rockchip: dts: Enable SARADC for rv1108-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:40:11 +0000 (14:40 +0800)]
rockchip: dts: rv1108: Add SARADC node at dtsi level
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:38:58 +0000 (14:38 +0800)]
rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:37:50 +0000 (14:37 +0800)]
rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:35:44 +0000 (14:35 +0800)]
rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:19 +0000 (14:28 +0800)]
rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:18 +0000 (14:28 +0800)]
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:16 +0000 (14:28 +0800)]
dm: adc: Add driver for Rockchip SARADC
The ADC can support some channels signal-ended some bits Successive Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:59 +0000 (22:37 +0300)]
env: ti: boot: Show boot status information
Add tracing printings to Linux/Android boot commands, so that we can see
what's going on. Helps to trace possible bugs on early stages and
improves the output for user (which is especially useful, because we
have a bunch of boot commands executing one by one).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:58 +0000 (22:37 +0300)]
env: ti: boot: Extract command for eMMC Linux boot
Extract commands for booting Linux from eMMC to separate command. It
seems more logical that way, and allows us to run the whole command set
from U-Boot shell with only one command.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:57 +0000 (22:37 +0300)]
arm: dra7xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:
1. Change bootpart to be 1:1
2. Or add preceding partition, so that rootfs is actually 1:2
Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.
This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:
Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).
This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Sam Protsenko [Thu, 21 Sep 2017 19:37:56 +0000 (22:37 +0300)]
arm: am57xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:
1. Change bootpart to be 1:1
2. Or add preceding partition, so that rootfs is actually 1:2
Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.
This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:
Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).
This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
This re-syncs omap3 DTS file with current file from
Linux v4.14-rc1 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from usbhsohci,
usbhsehci, ssi_port1 and ssi_port2 sub nodes.
Andrew F. Davis [Wed, 20 Sep 2017 19:45:09 +0000 (14:45 -0500)]
configs: k2g_evm: Make findfdt command populate fdtfile variable
On all other platforms the command 'findfdt' populates the variable
'fdtfile', but on K2G we only populate 'name_fdt'. The generic boot
and automation scripts fail when 'findfdt' is not populated, fix
this for K2G.
arm: am33xx: security: adds auth support for encrypted images
This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.
The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.
Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.
On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.
The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.
Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
Adam Ford [Wed, 20 Sep 2017 01:32:10 +0000 (20:32 -0500)]
arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.
There are some spacing issues in the patch, but they appear to be
present in the Linux source files. I'll try to get to fixing them there,
and do a future re-sync at a later date.
Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib).
Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:
configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to SPL_LDSCRIPT changes mode of containing choice from "arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"
The change in 8639f69 (genconfig.py: Print defconfig next to warnings)
was reapplied.
tools/moveconfig.py previously depended on a hack that merged 'select's
with 'imply's. It was modified to look at the union of
Symbol.get_selected_symbols() and Symbol.get_implied_symbols(), which
should give the same behavior.
tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.
Checkpatch can use two dictionaries for finding typos:
* scripts/spelling.txt
* /usr/share/codespell/dictionary.txt
which comes with package codespell and is selected by parameter
--codespell
If the file scripts/spelling.txt is missing, a warning is shown.
Add the spelling.txt file from the Linux kernel 4.13 source.
We can later add our own typo corrections.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Dan Murphy <dmurphy@ti.com>
Stephen Warren [Mon, 18 Sep 2017 17:50:47 +0000 (11:50 -0600)]
test/py: fix anchors in HTML status report
The current code wraps a pre tag inside an a tag. For some reason, this
causes at least Firefox to attempt to drag the pre section content when
using a mouse drag to select text. Re-order the tags so that the text can
be selected using the mouse, at least if you start the drag outside the
text (after the end of the line, for example).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 18 Sep 2017 17:11:49 +0000 (11:11 -0600)]
test/py: add skip marker for reliance on tools
Some tests use external tools (executables) during their operation. Add
a test.py mark to indicate this. This allows those tests to be skipped if
the required tool is not present.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Sun, 17 Sep 2017 15:44:49 +0000 (11:44 -0400)]
TI: ARCH_OMAP2PLUS: Enable SPL_STACK_R and provide default value
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it. select this and re-sync the defconfigs.
Adam Ford [Mon, 18 Sep 2017 01:43:48 +0000 (20:43 -0500)]
ARM: da850-evm: Enable DM_I2C
With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.
Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning] Signed-off-by: Tom Rini <trini@konsulko.com>
Adam Ford [Mon, 18 Sep 2017 01:43:47 +0000 (20:43 -0500)]
arm: da850-evm: Enable MTD Parts in SPI Flash
There is a discrepency between U-Boot and Linux on the partition map.
This enabes the MTD parts to pass MTD partition information from U-Boot to
Linux. Linux already has a pending patch to enable MTD PARTS in
davinci_all_defconfig
Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com>
mmc: sdhci-cadence: set timing mode register depending on frequency
The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.
U-Boot just provides a hook to change the clock frequency via
mmc_set_clock(). It is up to drivers if additional register
settings are needed.
This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode. Only increasing clock frequency
could result in setup/hold timing violation.
The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now. Just use mmc->clock to decide the
timing mode.
Seung-Woo Kim [Tue, 19 Sep 2017 04:29:45 +0000 (13:29 +0900)]
spl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector()
If there are no CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SPL_OS_BOOT,
there is unused-function build warning. Add __maybe_unused macro
to remove the warning.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Marek Vasut [Tue, 26 Sep 2017 18:05:34 +0000 (20:05 +0200)]
mmc: uniphier-sd: Update the file to match V3 patchset
Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.
Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
_ Full compliance with MultiMediaCard System Specification
Version 4.51. Card support for three different databus modes:
1-bit (default), 4-bit and 8-bit.
_ Full compatibility with previous versions of MultiMediaCards
(backward compatibility).
_ Full compliance with SD memory card specifications version 4.1.
(SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
SPI mode and UHS-II mode not supported).
_ Full compliance with SDIO card specification version 4.0.
Card support for two different databus modes: 1-bit (default)
and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
speed, SPI mode and UHS-II mode not supported).
_ Data transfer up to 208 Mbyte/s for the 8 bit mode.
(depending maximum allowed IO speed).
_ Data and command output enable signals to control external
bidirectional drivers.
The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.
Bin Meng [Wed, 13 Sep 2017 08:19:43 +0000 (01:19 -0700)]
usb: kbd: Set a default polling mechanism for USB keyboard
The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.
Fixes: ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot") Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 7 Sep 2017 13:13:21 +0000 (06:13 -0700)]
dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled
When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.
With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.
Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.
xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.
Marek Vasut [Tue, 12 Sep 2017 21:02:08 +0000 (23:02 +0200)]
usb: xhci: Set number of event segments and entries to 1
The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.
Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com>
GPT: incomplete initialization in allocate_disk_part
memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.
We should use sizeof(struct disk_part).
Instead of malloc and memset we can use calloc.
Identified by cppcheck.
Fixes: 09a49930e41 GPT: read partition table from device into a data structure Reported-by: Coverity (CID: 167228) Cc: Stefan Roese <sr@denx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 12 Sep 2017 17:09:31 +0000 (19:09 +0200)]
mtd: cfi: Add support for status register polling
The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Marek Vasut [Tue, 12 Sep 2017 17:09:08 +0000 (19:09 +0200)]
mtd: cfi: Zap cfi_flash_base in DM case
Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.
Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Fri, 22 Sep 2017 16:50:31 +0000 (04:50 +1200)]
ARM: mvebu: handle unused DRAM banks with ECC enabled
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.
Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Joshua Scott [Mon, 4 Sep 2017 05:38:32 +0000 (17:38 +1200)]
ARM: mvebu: add additional information to board_add_ram_info()
Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz
DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 30 Aug 2017 07:55:01 +0000 (09:55 +0200)]
arm: mvebu: Remove theadorable_defconfig
Currently, we support 2 "theadorable" MVEBU build targets. One with a
stripped down configuration (theadorable) and one with a full blown
configuration (theadorable_debug), including PCI, ethernet etc. When
we introduced these configs, the plan was to remove the debug version
at some point. But now it seems better to keep the full-blown version
and remove the "non-debug" version instead.
At a later stage, I will rename the remaining "theadorable_debug"
target into a more fitting one.
Suresh Gupta [Mon, 5 Jun 2017 09:07:20 +0000 (14:37 +0530)]
spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.
Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
incorrectly detects FS flash as FL. Thus its better to compare with
S25FS256S first.
Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com>
[Added S-o-b] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Yogesh Gaur [Thu, 31 Aug 2017 04:56:31 +0000 (10:26 +0530)]
mtd/spi: Add MT35XU512ABA1G12 NOR flash support
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Suresh Gupta [Wed, 30 Aug 2017 14:36:33 +0000 (20:06 +0530)]
spi: fsl_qspi: Add controller busy check before new spi operation
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Tom Rini [Sun, 24 Sep 2017 03:14:33 +0000 (23:14 -0400)]
tools/mkimage: Make the path to the dtc binary that mkimage calls configurable
In some cases, such as FreeBSD, the path to an alternative dtc needs to
be used. Rather than override the one given in the Makefile on the
command line, make this part of the build configuration.
Tom Rini [Sat, 23 Sep 2017 17:00:57 +0000 (13:00 -0400)]
dtc: Switch to building and using our own dtc unless provided
This makes us act like the Linux Kernel does and allow for dtc to be
provided externally but otherwise we use the version of dtc that is
included in the sources. This in turn means that we can drop the
checkdtc logic. We select DTC in the cases where we will need the dtc
tool provided.
fe50bd1ecc1d fdtget: Split out cell list display into a new function 62d812308d11 README: Add a note about test_tree1.dts 5bed86aee9e8 pylibfdt: Add support for fdt_subnode_offset() 46f31b65b3b3 pylibfdt: Add support for fdt_node_offset_by_phandle() a3ae43723687 pylibfdt: Add support for fdt_parent_offset() a198af80344c pylibfdt: Add support for fdt_get_phandle() b9eba92ea50f tests: Return a failure code when any tests fail 155faf6cc209 pylibfdt: Use local pylibfdt module 50e5cd07f325 pylibfdt: Add a test for use of uint32_t ab78860f09f5 pylibfdt: Add stdint include to fix uint32_t 36f511fb1113 tests: Add stacked overlay tests on fdtoverlay 1bb00655d3e5 fdt: Allow stacked overlays phandle references a33c2247ac8d Introduce fdt_setprop_placeholder() method 0016f8c2aa32 dtc: change default phandles to ePAPR style instead of both e3b9a9588a35 tests: fdtoverlay unit test 42409146f2db fdtoverlay: A tool that applies overlays aae22722fc8d manual: Document missing options 13ce6e1c2fc4 dtc: fix sprintf() format string error, again d990b8013889 Makefile: Fix build on MSYS2 and Cygwin 51f56dedf8ea Clean up shared library compile/link options 21a2bc896e3d Suppress expected error message in fdtdump test 2a42b14d0d03 dtc: check.c fix compile error a10cb3c818d3 Fix get_node_by_path string equality check 548aea2c436a fdtdump: Discourage use of fdtdump c2258841a785 fdtdump: Fix over-zealous version check 9067ee4be0e6 Fix a few whitespace and style nits e56f2b07be38 pylibfdt: Use setup.py to build the swig file 896f1c133265 pylibfdt: Use Makefile constructs to implement NO_PYTHON 90db6d9989ca pylibfdt: Allow setup.py to operate stand-alone e20d9658cd8f Add Coverity Scan support b04a2cf08862 pylibfdt: Fix code style in setup.py 1c5170d3a466 pylibfdt: Rename libfdt.swig to libfdt.i 580a9f6c2880 Add a libfdt function to write a property placeholder ab15256d8d02 pylibfdt: Use the call function to simplify the Makefile 9f2e3a3a1f19 pylibfdt: Use the correct libfdt version in the module e91c652af215 pylibfdt: Enable installation of Python module 8a892fd85d94 pylibfdt: Allow building to be disabled 741cdff85d3e .travis.yml: Add builds with and without Python library prerequisites 14c4171f4f9a pylibfdt: Use package_dir to set the package directory 89a5062ab231 pylibfdt: Use environment to pass C flags and files 4e0e0d049757 pylibfdt: Allow pkg-config to be supplied in the environment 6afd7d9688f5 Correct typo: s/pylibgfdt/pylibfdt/ 756ffc4f52f6 Build pylibfdt as part of the normal build process 8cb3896358e9 Adjust libfdt.h to work with swig b40aa8359aff Mention pylibfdt in the documentation 12cfb740cc76 Add tests for pylibfdt 50f250701631 Add an initial Python library for libfdt cdbb2b6c7a3a checks: Warn on node name unit-addresses with '0x' or leading 0s 4c15d5da17cc checks: Add bus checks for simple-bus buses 33c3985226d3 checks: Add bus checks for PCI buses
Tom Rini [Sat, 23 Sep 2017 21:30:53 +0000 (17:30 -0400)]
scripts/dtc: Update to upstream version v1.4.4
This adds the following commits from upstream:
558cd81bdd43 dtc: Bump version to v1.4.4 c17a811c62eb fdtput: Remove star from value_len documentation 194d5caaefcb fdtget: Use @return to document the return value d922ecdd017b tests: Make realloc_fdt() really allocate *fdt 921cc17fec29 libfdt: overlay: Check the value of the right variable 9ffdf60bf463 dtc: Simplify asm_emit_string() implementation 881012e44386 libfdt: Change names of sparse helper macros bad5b28049e5 Fix assorted sparse warnings 672ac09ea04d Clean up gcc attributes 49300f2ade6a dtc: Don't abuse struct fdt_reserve_entry
Tom Rini [Sat, 23 Sep 2017 16:52:44 +0000 (12:52 -0400)]
scripts/dtc: Update to upstream version v1.4.3
Using the update-dtc-source.sh script from Linux v4.14-rc1 import the
portions of dtc that we require. We bring in update-dtc-source.sh and
scripts/dtc/Makefile from Linux v4.14-rc1. Rework DTC_FLAGS handling to
not require a test.