Stefan Roese [Sat, 28 Jun 2008 12:56:17 +0000 (14:56 +0200)]
ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic
This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:
Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.
This errata is not officially available yet. I'll update the comment
to add the errata number later.
MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver
This patch is based on the following patch sent a few minutes ago:
"NAND FSL UPM: driver re-write using the hwcontrol callback"
It is untested, of course. Anton, could you please give it a try.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Stefan Roese [Mon, 16 Jun 2008 08:40:02 +0000 (10:40 +0200)]
cfi-flash: Fix problem in flash_toggle(), busy was not detected reliably
This patch simplifies flash_toggle() (AMD commandset), which is used to
detect if a FLASH device is still busy with erase/program operations. On
800MHz Canyonlands/Glacier boards (460EX/GT) the current implementation
did not detect the busy state reliably, resulting in non erased sectors
etc. This patch now simplifies this function by "just" comparing the
complete data-word instead of ANDing it with the command-word (0x40)
before the compatison. It is done the same way in the Linux implementation
chip_ready() in cfi_cmdset_0002.c.
MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Roese [Tue, 10 Jun 2008 13:34:11 +0000 (15:34 +0200)]
ppc4xx: Canyonlands: Disable the RTC M41T62 square wave output
This patch disables the square wave output of the M41T62 RTC used on
Canyonlands & Glacier. Here the explanation:
The serial real-time clock part used in the design is an
STMicro M41T62. This part has a full-time 32KHz square wave
output that is connected to the TmrClk input to the
processor. The default state for this square wave output is
enabled so the output runs continuously when the board is
powered normally and also from the battery. The TmrClk input
to the processor goes to ground when the power is removed
from the board/processor, and therefore the running square
wave output is driving ground which drains the battery quickly.
tools/mkimage: fix compiler warnings on some systems.
Broke building on some systems, because the host's string.h was interfering
with u-boot's linux/string.h. It doesn't look like we need the u-boot one if
we're building for the host, so now we only include when building inside
u-boot.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Becky Bruce [Mon, 9 Jun 2008 21:03:40 +0000 (16:03 -0500)]
Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory. phys_size_t is defined as an unsigned long on almost
all current platforms.
This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram). It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.
Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Becky Bruce [Tue, 10 Jun 2008 01:37:18 +0000 (20:37 -0500)]
Change lmb to use phys_size_t/phys_addr_t
This updates the lmb code to use phys_size_t
and phys_addr_t instead of unsigned long. Other code
which interacts with this code, like getenv_bootm_size()
is also updated.
Booted on MPC8641HPCN, build-tested ppc, arm, mips.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Becky Bruce [Tue, 10 Jun 2008 01:37:16 +0000 (20:37 -0500)]
Change bd/gd memsize/ram_size to be phys_size_t.
Currently, both are defined as an unsigned long, but
should be phys_size_t. This should result in no real change,
since phys_size_t is currently an unsigned long for all the
default configs. Also add print_lnum to cmd_bdinfo to deal
with the potentially wider memsize.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Kumar Gala [Tue, 10 Jun 2008 21:16:02 +0000 (16:16 -0500)]
FSL LAW: Add new interface to use the last free LAW
LAWs have the concept of priority so its useful to be able to allocate
the lowest (highest number) priority. We will end up using this with the
new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 11 Jun 2008 05:51:45 +0000 (00:51 -0500)]
85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose. This makes life
a bit easier going forward with the new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
TQM85xx: Change memory map to support Flash memory > 128 MiB
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash
memory. The current memory map only supports up to 128 MiB Flash.
This patch adds the configuration option CONFIG_TQM_BIGFLASH. If
set, up to 1 GiB flash is supported. To achieve this, the memory
map has to be adjusted in great parts (for example the CCSRBAR is
moved from 0xE0000000 to 0xA0000000).
If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new
memory map also has to be considered in the kernel (changed
CCSRBAR address, changed PCI IO base address, ...). Please use
an appropriate Flat Device Tree blob (tqm8548.dtb).
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for NAND FLASH on the TQM8548. It is disabled by
default and can be enabled for the TQM8548 modules. It is now based on
the re-written FSL NAND UPM driver. A patch has been posted earlier today
with the subject:
"NAND FSL UPM: driver re-write using the hwcontrol callback"
Note that the R/B pin is not supported by that module requiring to use
the specified maximum delay time.
Note: With NAND support enabled the size of the U-Boot image exceeds
256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk,
doubling the image size :-(.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds basic support for the TQM8548 module from TQ-Components
(http://www.tqc.de/) including DDR2 SDRAM initialisation and support for
eTSEC 3 and 4
Furthermore Flash buffer write has been enabled to speed up output to
the Flash by approx. a factor of 10.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for Linux kernels using the Flat Device Tree.
It also re-defines the default environment settings for booting Linux
with the FDT blob.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
TQM85xx: Support for Spansion 'N' type flashes added
The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors,
than the formerly used 'M' types (S29GLxxxM series), so the flash layout
needs to be changed -> new start address of the environment. The macro
definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be
defined for boards with 'N' type flashes.
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560
board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used
as serial interface anyway. Worse, on some board variants configuring the
pins for SCC1 leads to short circuits (for example on the TQM8541-BG).
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Gerald Van Baren [Wed, 11 Jun 2008 02:15:58 +0000 (22:15 -0400)]
libfdt: Move the working_fdt pointer to cmd_fdt.c
The working_fdt pointer was declared in common/fdt_support.c but was
not used there. Move it to common/cmd_fdt.c where it is used (it is
also used in lib_ppc/bootm.c).
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
NAND FSL UPM: driver re-write using the hwcontrol callback
This is a re-write of the NAND FSL UPM driver using the more universal
hwcontrol callback (instead of the cmdfunc callback). Here is a brief
list of furher modifications:
- For the time being, the UPM setup writing the UPM array has been
removed from the driver and must now be done by the board specific
code.
- The bus width definition in "struct fsl_upm_nand" is now in bits to
comply with the corresponding Linux driver and 8, 16 and 32 bit
accesses are supported.
- chip->dev_read is only set if fun->dev_ready != NULL, which is
required for boards not connecting the R/B pin.
- A few issue have been fixed with MxMR bit manipulation like in the
corresponding Linux driver.
Note: I think the "io_addr" field of "struct fsl_upm" could be removed
as well, because the address is already determined by
"nand->IO_ADDR_[RW]", but I'm not 100% sure.
This patch has been tested on a TQM8548 modules with the NAND chip
Micron MT29F8G08FABWP.
This patch is based on the following patches posted to this list a few
minutes ago:
PPC: add accessor macros to clear and set bits in one shot
83xx/85xx/86xx: add more MxMR local bus definitions
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
PPC: add accessor macros to clear and set bits in one shot
PPC: add accessor macros to clear and set bits in one shot
This patch adds macros from linux/include/asm-powerpc/io.h to clear and
set bits in one shot using the in_be32, out_be32, etc. accessor functions.
They are very handy to manipulate bits it I/O registers.
This patch is required for my forthcoming FSL NAND UPM driver re-write and
the support for the TQM8548 module.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
83xx/85xx/86xx: add more MxMR local bus definitions
83xx/85xx/86xx: add more MxMR local bus definitions
This patch adds more macro definitions for the UPM Machine Mode Registers
They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx
common local bus definitions into include/asm-ppc/fsl_lbc.h. They are
required for my forthcoming FSL NAND UPM driver re-write and the support
for the TQM8548 module.
This patch is based on the following two patches from Anton Vorontsov:
Kumar Gala [Tue, 10 Jun 2008 21:53:46 +0000 (16:53 -0500)]
85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot. There are some other locations that the name
is useful (device tree setup). Expose the functionality to other bits
of code.
Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out. This is mainly to allow the most flexible use
of the name. The device tree code tends to not care about the 'E' suffix.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Anton Vorontsov [Wed, 28 May 2008 14:20:15 +0000 (18:20 +0400)]
83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h
This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
David Gibson [Tue, 20 May 2008 07:19:11 +0000 (17:19 +1000)]
libfdt: Several cleanups to parameter checking
This patch makes a couple of small cleanups to parameter checking of
libfdt functions.
- In several functions which take a node offset, we use an
idiom involving fdt_next_tag() first to check that we have indeed been
given a node offset. This patch adds a helper function
_fdt_check_node_offset() to encapsulate this usage of fdt_next_tag().
- In fdt_rw.c in several places we have the expanded version
of the RW_CHECK_HEADER() macro for no particular reason. This patch
replaces those instances with an invocation of the macro; that's what
it's for.
- In fdt_sw.c we rename the check_header_sw() function to
sw_check_header() to match the analgous function in fdt_rw.c, and we
provide an SW_CHECK_HEADER() wrapper macro as RW_CHECK_HEADER()
functions in fdt_rw.c
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Becky Bruce [Wed, 14 May 2008 18:10:04 +0000 (13:10 -0500)]
MPC85xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Stuart Wood [Fri, 30 May 2008 20:05:28 +0000 (16:05 -0400)]
env_nand.c: Added bad block management for environment variables
Modified to check for bad blocks and to skipping over them when
CFG_ENV_RANGE has been defined.
CFG_ENV_RANGE must be larger than CFG_ENV_SIZE and aligned to the NAND
flash block size.
Signed-off-by: Stuart Wood <stuart.wood@labxtechnologies.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Becky Bruce [Wed, 14 May 2008 18:09:58 +0000 (13:09 -0500)]
MPC86xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd to prevent us from trying to access
non-mapped memory.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.
Remy Bohmer [Thu, 5 Jun 2008 11:03:36 +0000 (13:03 +0200)]
DM9000 fix status check fail 0x6d error for trizeps board
According to the Application Notes of the DM9000, only the 2 bits 0:1 of
the status byte need to be checked to identify a valid packet in the fifo
But, The several different Application Notes do not all speak the same
language on these bits. They do not disagree, but only 1 Application Note
noted explicitly that only these 2 bits need to be checked.
Even the datasheets do not mention anything about these 2 bits.
Because the old code, and the kernel check the whole byte, I left this piece
untouched.
However, I tested all board/DM9000[A|E|EP] devices with this 2 bit check, so
it should work.
Notice, that the 2nd iteration through this receive loop (when a 2nd packet is
in the fifo) is much shorter now, compared to the older U-boot driver code,
so that we can maybe run into a hardware condition now that was never seen
before, or maybe was seen very unfrequently.
Additionaly added a cleanup of a stack variable.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
[MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines
MIPS port has two problems in timer routines. One is now we assume CFG_HZ
equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000
in the U-Boot system.
The other is we don't have a proper time management counter like timestamp
other ARCHs have. We need the 32-bit millisecond clock counter.
This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a
32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number
of calculated CP0 counter cycles in a CFG_HZ.
STRATEGY:
* Fix improper CFG_HZ value to have 1000
* Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead.
* timer_init: initialize timestamp and set up the first timer expiration.
Note that we don't need to initialize CP0 count/compare registers here
as they have been already zeroed out on the system reset. Leave them as
they are.
* get_timer: calculate how many timestamps have been passed, then return
base-relative timestamp. Make sure we can easily count missed timestamps
regardless of CP0 count/compare value.
* get_ticks: return the current timestamp, that is get_timer(0).
Most parts are from good old Linux v2.6.16 kernel.
v2:
- Remove FIXME comments as they turned out to be trivial.
- Use CP0 compare register as a global variable for expirelo.
- Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY
instead.
[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros
We already have many pre-defined CP0 access macros in <asm/mipsregs.h>.
This patch replaces mips_{compare,count}_set and mips_count_get with
existing macros.
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