]> git.sur5r.net Git - u-boot/log
u-boot
13 years agompc85xx: Enable unique mode registers and dynamic ODT for DDR3
York Sun [Mon, 10 Jan 2011 12:03:00 +0000 (12:03 +0000)]
mpc85xx: Enable unique mode registers and dynamic ODT for DDR3

Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc85xx: Adding more registers and options
York Sun [Mon, 10 Jan 2011 12:02:59 +0000 (12:02 +0000)]
mpc85xx: Adding more registers and options

This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agocorenet_ds: Enable ECC for corenet_ds
York Sun [Mon, 10 Jan 2011 12:02:58 +0000 (12:02 +0000)]
corenet_ds: Enable ECC for corenet_ds

ECC can be turned on/off by hwconfig without recompiling. So enable it
by default.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc8xxx: Enable ECC on/off control in hwconfig
York Sun [Mon, 10 Jan 2011 12:02:57 +0000 (12:02 +0000)]
mpc8xxx: Enable ECC on/off control in hwconfig

Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.

Updated hwconfig calls to use local buffer.

Syntax is
hwconfig=fsl_ddr:ecc=on

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc8xxx: Display RDIMM if detected
York Sun [Mon, 10 Jan 2011 12:02:56 +0000 (12:02 +0000)]
mpc8xxx: Display RDIMM if detected

Print a message when a RDIMM is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers
Kumar Gala [Wed, 19 Jan 2011 09:05:26 +0000 (03:05 -0600)]
powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers

Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agopowerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init
Kumar Gala [Sun, 9 Jan 2011 17:37:00 +0000 (11:37 -0600)]
powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init

There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup.  This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in.  Additionally the access
might be so early that memory isn't even properly setup for us.

Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.

We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.

We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.

Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all.  We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agopowerpc/p2040: Add various p2040 specific information
Kumar Gala [Tue, 1 Jun 2010 15:29:11 +0000 (10:29 -0500)]
powerpc/p2040: Add various p2040 specific information

Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/p5020: Add various p5020 specific information
Kumar Gala [Thu, 8 Jul 2010 10:24:44 +0000 (05:24 -0500)]
powerpc/p5020: Add various p5020 specific information

Add P5020 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/p3041: Add various p3041 specific information
Kumar Gala [Sun, 4 Jul 2010 18:07:08 +0000 (13:07 -0500)]
powerpc/p3041: Add various p3041 specific information

Add P3041 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add Support for Freescale P1014 Processor
Poonam Aggrwal [Thu, 13 Jan 2011 16:10:05 +0000 (21:40 +0530)]
powerpc/85xx: Add Support for Freescale P1014 Processor

The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add Support for Freescale P1010 Processor
Poonam Aggrwal [Thu, 13 Jan 2011 16:09:27 +0000 (21:39 +0530)]
powerpc/85xx: Add Support for Freescale P1010 Processor

Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
* TCP/IP acceleration and classification capabilities
* IEEE 1588 support
* Lossless flow control
* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoFix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
Prabhakar [Tue, 18 Jan 2011 03:33:59 +0000 (09:03 +0530)]
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR

CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
13 years agopowerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h
Kumar Gala [Wed, 12 Jan 2011 08:48:53 +0000 (02:48 -0600)]
powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h

Rather than defining it config.mk we can set it in config.h and remove
config.mk from several boards that don't need it.

We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for
config.h to set.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years ago8xxx/ddr: add support to only compute the ddr sdram size
Haiying Wang [Wed, 1 Dec 2010 15:35:31 +0000 (10:35 -0500)]
8xxx/ddr: add support to only compute the ddr sdram size

This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Mon, 17 Jan 2011 19:31:46 +0000 (20:31 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-i2c
Wolfgang Denk [Mon, 17 Jan 2011 19:11:40 +0000 (20:11 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c

13 years agopowerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)
Kumar Gala [Thu, 13 Jan 2011 08:58:23 +0000 (02:58 -0600)]
powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)

Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)
Kumar Gala [Thu, 13 Jan 2011 07:56:18 +0000 (01:56 -0600)]
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)

CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)
Kumar Gala [Thu, 13 Jan 2011 07:54:01 +0000 (01:54 -0600)]
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)

CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boards
Kumar Gala [Tue, 11 Jan 2011 06:52:35 +0000 (00:52 -0600)]
powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boards

CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we
should also allow the kernel image to be up to 16M decompressed.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code
Kumar Gala [Sun, 9 Jan 2011 20:06:28 +0000 (14:06 -0600)]
powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code

Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)
Roy Zang [Fri, 7 Jan 2011 06:24:27 +0000 (00:24 -0600)]
fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)

False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
Roy Zang [Fri, 7 Jan 2011 06:06:47 +0000 (00:06 -0600)]
fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)

The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)
Jerry Huang [Fri, 7 Jan 2011 05:42:19 +0000 (23:42 -0600)]
fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)

Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add SRIO support to P2020DS
Li Yang [Thu, 30 Dec 2010 17:17:44 +0000 (11:17 -0600)]
powerpc/85xx: Add SRIO support to P2020DS

The P2020 has 2 SRIO ports and they are useable on the P2020 DS board.
Enable them using the common SRIO init code.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/86xx: Convert SBC8641 to use common SRIO init code
Kumar Gala [Tue, 4 Jan 2011 23:48:51 +0000 (17:48 -0600)]
powerpc/86xx: Convert SBC8641 to use common SRIO init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
13 years agopowerpc/86xx: Convert MPC8641HPCN to use common SRIO init code
Kumar Gala [Tue, 4 Jan 2011 23:45:13 +0000 (17:45 -0600)]
powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/86xx: Enable common SRIO init code
Kumar Gala [Tue, 4 Jan 2011 23:07:54 +0000 (17:07 -0600)]
powerpc/86xx: Enable common SRIO init code

Add the needed defines and code to utilize the common 8xxx srio init
code to setup LAWs and modify device tree if we have SRIO enabled on a
board.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Convert MPC8569MDS to use common SRIO init code
Kumar Gala [Wed, 5 Jan 2011 00:04:01 +0000 (18:04 -0600)]
powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Convert MPC8568MDS to use common SRIO init code
Kumar Gala [Wed, 5 Jan 2011 00:01:49 +0000 (18:01 -0600)]
powerpc/85xx: Convert MPC8568MDS to use common SRIO init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Convert MPC8548CDS to use common SRIO init code
Kumar Gala [Tue, 4 Jan 2011 23:57:59 +0000 (17:57 -0600)]
powerpc/85xx: Convert MPC8548CDS to use common SRIO init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Refactor SRIO initialization into common code
Kumar Gala [Thu, 30 Dec 2010 18:09:53 +0000 (12:09 -0600)]
powerpc/8xxx: Refactor SRIO initialization into common code

Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO.  We mimic what we do with PCIe
controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agofsl_pci: Update PCIe boot ouput
Peter Tyser [Tue, 28 Dec 2010 23:47:25 +0000 (17:47 -0600)]
fsl_pci: Update PCIe boot ouput

This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code
Kumar Gala [Thu, 6 Jan 2011 16:39:52 +0000 (10:39 -0600)]
powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code

Remove duplicated code in corenet_ds boards and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:30:44 +0000 (10:30 -0600)]
powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

Remove duplicated code in SBC8548 board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
13 years agopowerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:26:44 +0000 (10:26 -0600)]
powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

Remove duplicated code in SBC8641 board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
13 years agopowerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:42:33 +0000 (10:42 -0600)]
powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8610HPCD board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:42:01 +0000 (10:42 -0600)]
powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

Remove duplicated code in P1_P2_RDB boards and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:18:07 +0000 (10:18 -0600)]
powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8569MDS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:13:19 +0000 (10:13 -0600)]
powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8568MDS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:23:45 +0000 (10:23 -0600)]
powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code

Remove duplicated code in TQM 85xx boards and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: wd@denx.de
13 years agopowerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:23:03 +0000 (10:23 -0600)]
powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8xxx XES boards and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Peter Tyser <ptyser@xes-inc.com>
13 years agopowerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:21:22 +0000 (10:21 -0600)]
powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8548CDS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 16:47:36 +0000 (10:47 -0600)]
powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8641HPCN board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 21:14:54 +0000 (15:14 -0600)]
powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8536DS board and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 12:01:24 +0000 (06:01 -0600)]
powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8544DS board and utilize the common
fsl_pcie_init_ctrl().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3
specially to setup the additional memory map region and we utilize a
single LAW to cover the controller.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 13:01:00 +0000 (07:01 -0600)]
powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code
Kumar Gala [Fri, 17 Dec 2010 12:53:52 +0000 (06:53 -0600)]
powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/fsl-pci: Add generic code to setup PCIe controllers
Kumar Gala [Wed, 15 Dec 2010 20:21:41 +0000 (14:21 -0600)]
powerpc/fsl-pci: Add generic code to setup PCIe controllers

Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Based on patch by: Li Yang <leoli@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup
Kumar Gala [Fri, 17 Dec 2010 11:57:25 +0000 (05:57 -0600)]
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup

Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus.  Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.

Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agopowerpc/85xx: Fix bug in dcache_disable
Kumar Gala [Wed, 5 Jan 2011 16:33:46 +0000 (10:33 -0600)]
powerpc/85xx: Fix bug in dcache_disable

We set the L1 dache register with a bogus register value.  Need to be
using 'r3' instead of 'r0'.

Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMPC8xxx DDR: align informational prints
Becky Bruce [Fri, 17 Dec 2010 23:17:59 +0000 (17:17 -0600)]
MPC8xxx DDR: align informational prints

Add spaces to cause the informational prints to line up with
the ones from init_func_ram() in board.c.  Output now looks like
this:

....
DRAM:  Detected 4096 MB of memory
       This U-Boot only supports < 4G of DDR
       You could rebuild it with CONFIG_PHYS_64BIT
       DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off)
....

The prints from lbc_sdram_init() have also been modified to line
line up and changed to start with "LBC SDRAM" instead of the
confusing "SDRAM".

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years ago85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN
Becky Bruce [Fri, 17 Dec 2010 23:17:58 +0000 (17:17 -0600)]
85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN

This config option is for an erratum workaround; rename it to be more
clear.  Also, drop it from config files don't need it and were
undefining it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc85xx: rename sdram_init() lbc_sdram_init()
Becky Bruce [Fri, 17 Dec 2010 23:17:57 +0000 (17:17 -0600)]
mpc85xx: rename sdram_init() lbc_sdram_init()

sdram_init() is used to initialize sdram on the lbc.  Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc85xx boards: initdram() cleanup/bugfix
Becky Bruce [Fri, 17 Dec 2010 23:17:56 +0000 (17:17 -0600)]
mpc85xx boards: initdram() cleanup/bugfix

Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts.  Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others.  I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document.  It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled.  This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc85xx/tlb.c: Allow platforms to specify wimge bits
Becky Bruce [Fri, 17 Dec 2010 23:17:55 +0000 (17:17 -0600)]
mpc85xx/tlb.c: Allow platforms to specify wimge bits

Some platforms might want to override the default wimge=0 for
DDR.  Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use.
This will initially only be used by TQM85xx, but could be
useful for other boards or testing going forward.  Note that
the name of this define is not 85xx-specific.  WIMGE is a
fairly universal concept, so any ppc platforms that require
different WIMGE settings for DDR can use the same #define.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agotqm85xx: create fixed_sdram() to do sdram setup
Becky Bruce [Fri, 17 Dec 2010 23:17:54 +0000 (17:17 -0600)]
tqm85xx: create fixed_sdram() to do sdram setup

Also, change this code to use phys_size_t instead of long int.
Using common naming for this function will enable us to use the common
initdram() for 85xx going forward.  Other than the type change,
this is just a code rearrange.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Cleanup SGMII detection and reporting
Kumar Gala [Thu, 16 Dec 2010 20:28:06 +0000 (14:28 -0600)]
powerpc/85xx: Cleanup SGMII detection and reporting

Use new is_serdes_configured to determine if TSECs are in SGMII mode and
report that on the various boards that use or can be configured in SGMII
mode in board_eth_init() instead of in the PCI init code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured
Kumar Gala [Wed, 15 Dec 2010 10:55:20 +0000 (04:55 -0600)]
powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured

Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_esdhc: Fix esdhc disabled problem on some platforms
Chenhui Zhao [Tue, 4 Jan 2011 09:23:05 +0000 (17:23 +0800)]
fsl_esdhc: Fix esdhc disabled problem on some platforms

Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.

Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.

Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processors
Piergiorgio Beruto [Tue, 4 Jan 2011 13:32:15 +0000 (14:32 +0100)]
powerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processors

Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for P1021 SERDES
Kumar Gala [Wed, 15 Dec 2010 10:04:56 +0000 (04:04 -0600)]
powerpc/85xx: Add is_serdes_configured() support for P1021 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDES
Kumar Gala [Tue, 27 Apr 2010 14:20:20 +0000 (09:20 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDES
Kumar Gala [Tue, 27 Apr 2010 05:05:41 +0000 (00:05 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDES
Kumar Gala [Tue, 27 Apr 2010 04:44:10 +0000 (23:44 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDES
Kumar Gala [Tue, 27 Apr 2010 04:25:33 +0000 (23:25 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDES
Kumar Gala [Tue, 27 Apr 2010 04:09:23 +0000 (23:09 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add is_serdes_configured() support for P2020 SERDES
Kumar Gala [Wed, 15 Dec 2010 08:49:03 +0000 (02:49 -0600)]
powerpc/85xx: Add is_serdes_configured() support for P2020 SERDES

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/86xx: Add SERDES support on MPC8641 & MPC8610
Kumar Gala [Wed, 15 Dec 2010 10:52:48 +0000 (04:52 -0600)]
powerpc/86xx: Add SERDES support on MPC8641 & MPC8610

Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.  This mimics the code we have in place
for the 85xx platforms.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Create a SERDES section in Makefile
Kumar Gala [Wed, 15 Dec 2010 10:07:55 +0000 (04:07 -0600)]
powerpc/85xx: Create a SERDES section in Makefile

Created a section in the Makefile for SoC specific SERDES code.  Also
added P1013 SERDES (use P1022 SERDES code).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function
Kumar Gala [Wed, 15 Dec 2010 09:50:47 +0000 (03:50 -0600)]
powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function

Instead of a #define use a null weak function for fsl_serdes_init

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for booting from NAND on MPC8572DS
Kumar Gala [Fri, 12 Nov 2010 14:22:01 +0000 (08:22 -0600)]
powerpc/85xx: Add support for booting from NAND on MPC8572DS

Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting
from NAND.

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMPC8568/MPC8569: Remove CONFIG_DDR_DLL define
Becky Bruce [Mon, 13 Dec 2010 21:06:48 +0000 (15:06 -0600)]
MPC8568/MPC8569: Remove CONFIG_DDR_DLL define

Neither of these parts should have the erratum this is meant to
work around.  Delete it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition
Becky Bruce [Mon, 13 Dec 2010 21:06:45 +0000 (15:06 -0600)]
mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition

This isn't used - delete it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agosocrates: rename sdram_setup fixed_sdram()
Becky Bruce [Mon, 13 Dec 2010 21:06:44 +0000 (15:06 -0600)]
socrates: rename sdram_setup fixed_sdram()

This will help us go to a fixed initdram() for all 85xx boards going
forward.  sdram_setup() had an argument that it didn't need, since the
value was #defined.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMPC8xxx: Update maintainer entry for Wind River sbc8xxx boards
Paul Gortmaker [Mon, 13 Dec 2010 19:46:43 +0000 (14:46 -0500)]
MPC8xxx: Update maintainer entry for Wind River sbc8xxx boards

I've probably got the best chance of getting access to these
boards in order to test things, and since Joe's e-mail is
bouncing, update the MAINTAINERS entry to reflect this.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Remove support for PM854/PM856 boards
Kumar Gala [Tue, 14 Dec 2010 04:02:08 +0000 (22:02 -0600)]
powerpc/85xx: Remove support for PM854/PM856 boards

The PM854/PM856 boards are no longer maintained and thus we are removing
support for them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agopowerpc/85xx: Removed support for MPC8540EVAL board
Kumar Gala [Tue, 14 Dec 2010 04:01:01 +0000 (22:01 -0600)]
powerpc/85xx: Removed support for MPC8540EVAL board

The MPC8540EVAL board is no longer maintained and thus we are removing
support for it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Removed support for ATUM8548 board
Kumar Gala [Tue, 14 Dec 2010 03:53:09 +0000 (21:53 -0600)]
powerpc/85xx: Removed support for ATUM8548 board

The ATUM8548 board is no longer maintained and thus we are removing
support for it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agomtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
Lei Wen [Thu, 6 Jan 2011 01:48:18 +0000 (09:48 +0800)]
mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()

This patch sync with David's patch on Linux for handling nand_scan_ident.

commit 5e81e88a4c140586d9212999cea683bcd66a15c6
Author: David Woodhouse <David.Woodhouse@intel.com>
Date:   Fri Feb 26 18:32:56 2010 +0000

mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
13 years agoNAND: add the ability to directly write yaffs image
Lei Wen [Thu, 6 Jan 2011 03:11:58 +0000 (11:11 +0800)]
NAND: add the ability to directly write yaffs image

This patch add addition suffix to nand write to give the uboot
the power to directly burn the yaffs image to nand.

Signed-off-by: Lei Wen <leiwen@marvell.com>
13 years agonand: fix bug with multiple NAND devices if CONFIG_MTD_DEVICE is defined.
Alexander Holler [Sat, 18 Dec 2010 02:16:28 +0000 (02:16 +0000)]
nand: fix bug with multiple NAND devices if CONFIG_MTD_DEVICE is defined.

The variable i has to be static, otherwise it would be always zero.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Wolfgang Denk [Wed, 12 Jan 2011 22:59:53 +0000 (23:59 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-ubi
Wolfgang Denk [Wed, 12 Jan 2011 22:57:05 +0000 (23:57 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-cfi-flash
Wolfgang Denk [Wed, 12 Jan 2011 22:55:41 +0000 (23:55 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Wolfgang Denk [Wed, 12 Jan 2011 22:54:32 +0000 (23:54 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-microblaze
Wolfgang Denk [Wed, 12 Jan 2011 22:46:37 +0000 (23:46 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-microblaze

13 years agoRevert "boot cmds: convert to getenv_yesno() with autostart"
Wolfgang Denk [Tue, 11 Jan 2011 19:56:34 +0000 (20:56 +0100)]
Revert "boot cmds: convert to getenv_yesno() with autostart"

This reverts commit 5a442c0addc69d0c4b58e98e5aec1cf07576debb.

This commit changed the behaviour of getenv_yesno() (both the default
behaviour and the documented behaviour for abbreviated arguments)
which resulted in problems in several areas.

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoUBIFS: Fix dereferencing type-punned pointer compiler warning
Dirk Behme [Sat, 25 Dec 2010 09:58:46 +0000 (10:58 +0100)]
UBIFS: Fix dereferencing type-punned pointer compiler warning

Fix compiler warning

In file included from ubifs.h:2137:0,
                 from ubifs.c:26:
misc.h: In function 'ubifs_idx_key':
misc.h:263:26: warning: dereferencing type-punned pointer will break strict-aliasing rules

seen with gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50).

No functional change.

CC: Stefan Roese <sr@denx.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agoxilinx-ppc4xx-generic: Fix Makefile to work with MAKEALL
Ricardo Ribalda Delgado [Fri, 24 Dec 2010 00:38:10 +0000 (01:38 +0100)]
xilinx-ppc4xx-generic: Fix Makefile to work with MAKEALL

config.mk only mkdirs $(obj), but we have objects shared with other
boards located on other dirs.

This patch mkdirs the needed dirs for the xlnx-generic boards.

Signed-off-by: Stefan Roese <sr@denx.de>
13 years agoadd AM29F400BB to table of supported legacy flashs
David Müller [Tue, 21 Dec 2010 09:09:56 +0000 (10:09 +0100)]
add AM29F400BB to table of supported legacy flashs

Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agoppc4xx: Fix compilation breakage in miiphy.c
Stefan Roese [Mon, 10 Jan 2011 11:56:13 +0000 (12:56 +0100)]
ppc4xx: Fix compilation breakage in miiphy.c

Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small
problem in the ppc4xx miiphy.c version. This patch fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
13 years agoLAN91C*: Change chip names to fit the eth_device struct size
Yanjun Yang [Sun, 26 Dec 2010 02:40:54 +0000 (10:40 +0800)]
LAN91C*: Change chip names to fit the eth_device struct size

The eth_device.name field length is limited by NAMESIZE,
which is 16 defined in include/net.h. Unfortunately, two
of the names in lan91c96.c are beyond that.

Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>
13 years agoPPC4xx: Reduce NAND TLB window size on Canyonlands
Felix Radensky [Sun, 2 Jan 2011 09:07:34 +0000 (11:07 +0200)]
PPC4xx: Reduce NAND TLB window size on Canyonlands

16MiB NAND TLB window is way too big. Reduce it to 1KiB.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agoppc4xx: Remove PCI support from lwmon5
Stefan Roese [Tue, 21 Dec 2010 18:03:44 +0000 (19:03 +0100)]
ppc4xx: Remove PCI support from lwmon5

PCI is not used at all on lwmon5. So lets remove it. It saves space and
reduces boot time a bit (approx. 50ms).

Signed-off-by: Stefan Roese <sr@denx.de>
13 years agomicroblaze: Fix bd_info pointer
Michal Simek [Tue, 21 Dec 2010 08:32:44 +0000 (09:32 +0100)]
microblaze: Fix bd_info pointer

Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value"
(sha1: 25ddd1fb0a2281b182529afbc8fda5de2dc16d96)
introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t
(currently 0x40).
Microblaze configs used 0x40(128) because this place also contained
board info structure which lies on the top of ram.

U-Boot is placed to the top of the ram (for example 0xd7ffffff)
and bd structure was moved out of ram.

This patch is fixing this scheme with GENERATED_BD_INFO_SIZE
which swap global data and board info structures.

For example:
Current: gd 0xd7ffffc0, bd 0xd8000000
Fixed:   gd 0xd7ffffc0, bd 0xd7ffff90

Signed-off-by: Michal Simek <monstr@monstr.eu>
13 years agomicroblaze: Disabling interrupt should return 1 if was enabled
Michal Simek [Tue, 21 Dec 2010 07:30:39 +0000 (08:30 +0100)]
microblaze: Disabling interrupt should return 1 if was enabled

Microblaze implement enable/disable interrupts through MSR
that's why disable_interrupts function should return 1 when interrupt
was enabled. Return 0 when interrupt was disabled.

Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Wolfgang Denk <wd@denx.de>
13 years agopca953x: support 16-pin devices
Chris Packham [Sun, 19 Dec 2010 10:12:13 +0000 (10:12 +0000)]
pca953x: support 16-pin devices

This adds support for for the PCA9535/PCA9539 family of gpio devices which
have 16 output pins.

To let the driver know which devices are 16-pin it is necessary to define
CONFIG_SYS_I2C_PCA953X_WIDTH in your board config file. This is used to
create an array of {chip, ngpio} tuples that are used to determine the
width of a particular chip. For backwards compatibility it is assumed that
any chip not defined in CONFIG_SYS_I2C_PCA953X_WIDTH has 8 pins.

Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
13 years agoftgmac100: support of gigabit eth ftgmac100
Macpaul Lin [Tue, 21 Dec 2010 08:59:46 +0000 (16:59 +0800)]
ftgmac100: support of gigabit eth ftgmac100

Add Faraday's ftgmac100 (gigabit ethernet)
MAC controller's driver.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>