Masahiro Yamada [Thu, 12 Mar 2015 04:24:39 +0000 (13:24 +0900)]
kconfig: remove meaningless prefixes in defconfig files
Since commit e02ee2548afe (kconfig: switch to single .config
configuration), the prefixes in defconfig files such as "+S:",
"+ST:", etc., are meaningless.
This commit was generated by the following command:
find configs -name '*_defconfig' | xargs sed -i 's/^+*S*T*://'
Masahiro Yamada [Wed, 11 Mar 2015 08:34:25 +0000 (17:34 +0900)]
README: remove description about driver model configuration options (again)
The Driver Model description in README was removed by commit 65eb659e56fa (README: remove description about driver model
configuration options), and was revived by mistake by commit b79dadf846e5 when resolving the conflict.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Tue, 10 Mar 2015 21:40:58 +0000 (15:40 -0600)]
config_distro_bootcmd.h: add note on error handling
This should make it more clear why there appear to be C pre-processor
symbols in the file that contain mixed case. They're really error
messages.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Nishanth Menon [Mon, 9 Mar 2015 22:12:09 +0000 (17:12 -0500)]
ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Praveen Rao [Mon, 9 Mar 2015 22:12:06 +0000 (17:12 -0500)]
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:03 +0000 (17:12 -0500)]
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:02 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 621766
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:01 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:00 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:11:59 +0000 (17:11 -0500)]
ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 9 Mar 2015 16:40:36 +0000 (12:40 -0400)]
am335x_evm_usbspl: Remove other SPL modes
The purpose of this build target is to do SPL over USB RNDIS. We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets. This brings us well under size limit again.
Hans de Goede [Sat, 7 Mar 2015 11:00:02 +0000 (12:00 +0100)]
sunxi: video: Fix VIDEO_LCD_PANEL_I2C being enabled by default
Fix a typo in board/sunxi/Kconfig which caused VIDEO_LCD_PANEL_I2C to be
enabled on all sunxi boards. Also fix a compile error which shows up once
VIDEO_LCD_PANEL_I2C is actually disabled on most boards as it should be.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Aleksei Mamlin [Wed, 4 Mar 2015 07:44:18 +0000 (10:44 +0300)]
sunxi: Add Wexler TAB7200 support
This patch add support for Wexler TAB7200 tablet.
The Wexler TAB7200 is a A20 based tablet with 7 inch display(800x480),
capacitive touchscreen(5 fingers), 1G RAM, 4G NAND, micro SD card slot,
mini HDMI port, 3.5mm audio plug, 1 USB OTG port and 1 USB 2.0 port.
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Mon, 9 Mar 2015 07:44:16 +0000 (15:44 +0800)]
sunxi: musb: Support checking VBUS using AXP221 PMIC
This enables the musb glue layer to use the AXP221's VBUS detection
function to check for VBUS. This fixes otg support on the A23 q8h
tablets.
Note that u-boot never calls musb_shutdown(), so once VBUS is enabled,
it is never disabled until the system is powered off, or the OS does
so. This can be used to our advantage to keep VBUS powered into the
OS, where support for AXP221 is not available yet.
Fixes: 52defe8f6570 ("sunxi: musb: Check Vbus-det before enabling otg port power") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Mon, 9 Mar 2015 07:44:15 +0000 (15:44 +0800)]
sunxi: axp221: Add VBUS detection support
Some of the AXP PMICs support VBUS detection, i.e. checking whether
VBUS power input is available and usable (supplied by an external
source). A few boards use this instead of a separate GPIO to detect
VBUS on USB OTG.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sat, 7 Mar 2015 14:03:00 +0000 (15:03 +0100)]
sun7i: Add support for the Orange Pi Mini board
The Orange Pi Mini is an A20 based development board featuring 1G RAM, HDMI,
1Gbit ethernet, USB wifi, SATA, 2 sdcard slots (use the top one for booting),
2 USB 2.0 A receptacles, a micro USB B receptacle (otg) and a 3 ring 3.5 mm
jack connector for A/V.
Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 7 Mar 2015 14:01:46 +0000 (15:01 +0100)]
sun7i: Add support for the Orange Pi board
The Orange Pi is an A20 based development board featuring 1G RAM, HDMI & VGA,
1Gbit ethernet, USB wifi, SATA, 4 USB 2.0 A receptacles, a micro USB B
receptacle (otg) and a 3 ring 3.5 mm jack connector for A/V.
Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 7 Mar 2015 11:01:16 +0000 (12:01 +0100)]
sun7i: Add support for the Wits Pro A20 DKT board
The Wits Pro A20 DKT is an A20 Development KiT with 1G RAM, 4G NAND, sdio wifi,
1Gbit ethernet, 1024x768 lcd screen with ft5x_ts touchscreen and a ton of
IO connectors.
Note there seem to be multiple sdcard slots on the board (4 in total), but
other then mmc0 none of these are hooked up by default, there is a ton of
dip-switches which likely allow hooking some of these up, but the documentation
of the board only describes the use of a fraction of them, so for now we
only support mmc0.
Also see: http://www.merrii.com/en/pla_d.asp?id=163
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Gábor Nyers [Thu, 26 Feb 2015 11:08:15 +0000 (12:08 +0100)]
sunxi: Add support for the Jesurun Q5 board
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity can
be extended up to 32GB with a MicroSD card. The external connectors are: 2x
USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female,
SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired to
power) and an programmable green led. On the board there is also an unpopulated
IR receiver and the UART. The devices is equipped with an AXP209 PMU.
For more details see: http://linux-sunxi.org/Jesurun_Q5
Signed-off-by: Gábor Nyers <gnyers@opensuse.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Adam Sampson [Mon, 23 Feb 2015 20:44:10 +0000 (20:44 +0000)]
sunxi: Make CONFIG_DRAM_TPR3 apply to sun[57]i
The tpr3 (timing skew) parameter is used in all supported versions of
the sunxi DRAM controller, but it was only enabled for sun4i in 47e3501a76894f4ba08bc61f33774bd5d39ff464.
Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Linus Walleij [Mon, 9 Mar 2015 09:53:21 +0000 (10:53 +0100)]
armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.
Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.
This makes the Juno platform start U-Boot properly.
Tom Rini [Fri, 6 Mar 2015 01:19:36 +0000 (20:19 -0500)]
ARM: PSCI: Rework the DT handler slightly
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.
To fix this, we rework the hook slightly. A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large. So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.
Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
Reduce the boot time of Odroid X2/U3 by disabling the memset
at malloc init.
This was tested on Odroid X2.
A quick test with checking gpio pin state using the oscilloscope.
Boot time from start to bootcmd (change gpio state by memory write command):
- ~228ms - before this change (arch memset enabled for .bss clear)
- ~100ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Reduce the boot time of Trats2 by disabling the memset
at malloc init.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~464ms - before this change (arch memset enabled for .bss clear)
- ~341ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
dlmalloc: do memset in malloc init as new default config
This commit introduces new config: CONFIG_SYS_MALLOC_CLEAR_ON_INIT.
This config is an expert option and is enabled by default.
The all amount of memory reserved for the malloc, is by default set
to zero in mem_malloc_init(). When the malloc reserved memory exceeds
few MiB, then the boot process can slow down.
So disabling this config, is an expert option to reduce the boot time,
and can be disabled by Kconfig.
Note:
After disable this option, only calloc() will return the pointer
to the zeroed memory area. Previously, without this option,
the memory pointed to untouched malloc memory region, was filled
with zeros. So it means, that code with malloc() calls should
be reexamined.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
For writing files, DFU implementation requires the file buffer
with the len at least of file size. For big files it requires
the same big buffer.
Previously the file buffer was allocated as a static variable,
so it was a part of U-Boot .bss section. For 32MiB len of buffer
we have 32MiB of additional space, required for this section.
The .bss needs to be cleared after the relocation.
This introduces an additional boot delay at every start, but usually
the dfu feature is not required at the standard boot, so the buffer
should be allocated only if required.
This patch removes the static allocation of this buffer,
and alloc it with memalign after first call of function:
- dfu_fill_entity_mmc()
and the buffer is freed on dfu_free_entity() call.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~888ms - before this change (arch memset enabled for .bss clear)
- ~464ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Cc: Marek Vasut <marek.vasut@gmail.com>
arm: relocation: clear .bss section with arch memset if defined
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.
Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.
A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.
So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
- ~888ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
exynos: config: enable arch memcpy and arch memset
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot time.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1527ms - before this change (arch memset enabled for .bss clear)
- ~1384ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Masahiro Yamada [Fri, 27 Feb 2015 15:37:57 +0000 (00:37 +0900)]
fixdep: remove multiple .config support code
Since commit e02ee2548afe (kconfig: switch to single .config
configuration), the ".*.cmd" files are not correctly created
for SPL/TPL. The U-Boot extension code in fixdep, which was
introduced to support the multiple .config, must be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Alexey Brodkin [Wed, 25 Feb 2015 14:59:02 +0000 (17:59 +0300)]
common/board_f: implement type casting for gd structure
In case of global data structure defined as "register volatile" compiler
throws an warning about incorrect type used:
--->8---
common/board_f.c: In function "board_init_f_r":
common/board_f.c:1073:2: warning: passing argument 1 of "&board_init_r
+(sizetype)gd->reloc_off" discards "volatile" qualifier from pointer
target type [enabled by default]
(board_init_r + gd->reloc_off)(gd, gd->relocaddr);
^
common/board_f.c:1073:2: note: expected "struct gd_t *" but argument is
of type "volatile struct gd_t *"
--->8---
An obvious fix is manual casting to "gd_t *".
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
Alexey Brodkin [Wed, 25 Feb 2015 10:09:20 +0000 (13:09 +0300)]
lib/asm-offsets - make GD_RELOCADDR, GD_RELOC_OFF & GD_START_ADDR_SP available for all architectures
GD_RELOCADDR, GD_RELOC_OFF & GD_START_ADDR_SP are generic members of
global data structure so why don't we allow architectures other than ARM
to use it.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
Heiko Schocher [Tue, 24 Feb 2015 06:04:38 +0000 (07:04 +0100)]
spl: fix calling "spl export .." more than once
running "spl export ..." more than once fails with:
Trying to execute a command out of order
Trying to execute a command out of order
Trying to execute a command out of order
Trying to execute a command out of order
Trying to execute a command out of order
Trying to execute a command out of order
ERROR prep subcommand failed!
Subcommand failed
reason is commmit: 35fc84fa1f: Refactor the bootm command to reduce code duplication
It used "state != BOOTM_STATE_START" but state is a bitfield, so
check if the bit BOOTM_STATE_START is not set. With this fix,
"spl export ..." can called more than once ...
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Chen Gang [Thu, 19 Feb 2015 15:51:27 +0000 (18:51 +0300)]
use ASM_NL instead of '; ' for assembler new line character in the macro
For some assemblers, they use another character as newline in a macro
(e.g. arc uses '`'), so for generic assembly code, need use ASM_NL (a
macro) instead of ';' for it.
Basically this is the same patch as applied to Linux kernel -
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/include/linux/linkage.h?id=9df62f054406992ce41ec4558fca6a0fa56fffeb
but modified a bit to fit in U-Boot.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>
Ash Charles [Wed, 18 Feb 2015 19:25:11 +0000 (11:25 -0800)]
omap: gpmc: 'nandecc sw' can use HAM1 or BCH8
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Michal Sojka [Tue, 17 Feb 2015 16:08:37 +0000 (17:08 +0100)]
mtd: nand: omap_gpmc: Make ready/busy pins configurable
Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.
This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:
#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.
Signed-off-by: Michal Sojka <sojka@merica.cz> Acked-by: Stefan Roese <sr@denx.de> Tested-by: Michal Vokáč <michal.vokac@comap.cz> Cc: Tom Rini <trini@ti.com>
After rework of the file system API, the size of ext4
write was missed. This causes printing unreliable write
size at the end of the file system write operation.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Linus Walleij [Tue, 17 Feb 2015 10:35:25 +0000 (11:35 +0100)]
vexpress64: juno: support SMC9118 ethernet
This configures the Juno board to enable ethernet using the
SMSC9118 ethernet controller found in the board. Tested by
TFTP-booting a kernel over ethernet.
Alison Wang [Thu, 12 Feb 2015 10:33:15 +0000 (18:33 +0800)]
m68k: Add generic board support for MCF547X/8X and MCF5445X
This patch adds generic board support for MCF547X/8X and MCF5445X.
It is based on the patch about common generic board support for
M68K architecture sent by Angelo.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
vxWorks needs several parameters which are set by the bootloader und his
environment. So we form a vxWorks bootline and pass the result to vxWorks on
a predefined address.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/common: Introduce Network Console and common environment for it
It is often necessary to "break in" into boards bootloader commandline if
something fails or even for development purposes some parameters have to be
changed.
So we enable u-boot's CONFIG_NETCONSOLE feature.
We also modify Networksettings to apply with this new use-case.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/common: try to setup cpsw mac-address from the devicetree
since we have a dtb blob programmed on the board we try to setup the cpsw
interface with the programmed mac.
If this method fails, we fall back to the device-fuses.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
common/lcd: Add command for writing to lcd-display
Sometimes we do not want redirect u-boot's console to screen but anyway we want
write out some status information out of a u-boot script to the display.
So we cannot use the normal "echo ....", instead we write explicitly using
"lcdputs ..." for writing to the actual cursor position on LCD.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
common/lcd: Add command for setting cursor within lcd-console
Sometimes we do not want redirect u-boot's console to screen but anyway we want
write out some status information out of a u-boot script to the display.
To define the specific position of the string to be written, we have to set
the cursor with "setcurs" before writing.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
projects / u-boot / log