Stefan Roese [Mon, 22 Oct 2007 13:44:39 +0000 (15:44 +0200)]
ppc4xx: Rework of 4xx serial driver (2)
Change all linker scripts to reference the changed driver name 4xx_uart.o.
Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.
Stefan Roese [Mon, 22 Oct 2007 13:09:59 +0000 (15:09 +0200)]
ppc4xx: Rework of 4xx serial driver (1)
This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).
Stefan Roese [Sun, 21 Oct 2007 06:16:12 +0000 (08:16 +0200)]
rtc: Add Xicor/Intersil X1205 RTC support
This patch adds support for the Xicor/Intersil X1205 RTC used on the
AMCC Makalu eval board. This driver is basically cloned from the Linux
driver version (2.6.23).
This patch also introduces the Linux bcd.h header for the BCD2BIN/
BIN2BCD conversions. In the future some of the other U-Boot RTC driver
should be converted to also use this header instead of implementing
their own local copy of these functions/macros.
Stefan Roese [Thu, 18 Oct 2007 05:42:27 +0000 (07:42 +0200)]
ppc4xx: Change inbound PCIe location for endpoint tests on Katmai
On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
is the internal SRAM. Since I now ported and tested this endpoint mode
on Kilauea successfully to map to 0 (SDRAM), I also changed this for
Katmai.
Yucca will stay at internal SRAM for now. Not sure if somebody relies on
this setup.
Stefan Roese [Thu, 18 Oct 2007 05:39:38 +0000 (07:39 +0200)]
ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.
In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.
Stefan Roese [Sat, 13 Oct 2007 14:43:23 +0000 (16:43 +0200)]
ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 11 Oct 2007 09:15:59 +0000 (11:15 +0200)]
ppc4xx: Enable device tree support (fdt) on Kilauea per default
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.
This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Stefan Roese [Fri, 5 Oct 2007 05:57:20 +0000 (07:57 +0200)]
ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Stefan Roese [Wed, 3 Oct 2007 13:01:02 +0000 (15:01 +0200)]
ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Stefan Roese [Wed, 3 Oct 2007 08:38:09 +0000 (10:38 +0200)]
ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
the SDR registers of the PCIe ports. This makes the overall design
clearer, since it removed a lot of switch statements which are not
needed anymore.
Also, the functions ppc4xx_init_pcie_rootport() and
ppc4xx_init_pcie_entport() are merged into a single function
ppc4xx_init_pcie_port(), since most of the code was duplicated.
This makes maintainance and porting to other 4xx platforms
easier.
Stefan Roese [Wed, 3 Oct 2007 05:48:09 +0000 (07:48 +0200)]
ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Stefan Roese [Wed, 3 Oct 2007 05:34:10 +0000 (07:34 +0200)]
ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Martin Krause [Mon, 22 Oct 2007 14:45:53 +0000 (16:45 +0200)]
TQM5200: fix spurious characters on second serial interface
With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Martin Krause [Mon, 22 Oct 2007 14:40:06 +0000 (16:40 +0200)]
TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Marcel Ziswiler [Thu, 18 Oct 2007 22:25:33 +0000 (00:25 +0200)]
fix pxa255_idp board
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Bartlomiej Sieka [Tue, 23 Oct 2007 11:14:10 +0000 (13:14 +0200)]
Motion-PRO: Update configuration to accomodate next generation board.
New board has faster oscillator and a different Flash chip. This affects:
- CFG_MPC5XXX_CLKIN
- SDRAM timings
- Flash CS configuration (timings)
- Flash sector size, and thus MTD partition layout
- malloc() arena size (due to bigger Flash sectors)
- smaller memory test range (due to bigger malloc() arena)
This patch also enables more extensive memory testing via "mtest".
Bartlomiej Sieka [Tue, 23 Oct 2007 09:36:07 +0000 (11:36 +0200)]
Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.
Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Vlad Lungu [Thu, 4 Oct 2007 17:47:10 +0000 (20:47 +0300)]
Fix NE2000 driver:
Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try
to do anything in eth_stop() if eth_init() was not called.
Simplified RX path in order to avoid timeouts on really really
fast NE2000 cards (read: qemu with internal tftp), NetLoop() is
clever enough to cope with 1 packet per eth_rx().
Jon Loeliger [Mon, 27 Aug 2007 17:41:03 +0000 (12:41 -0500)]
86xx: Allow for fewer DDR slots per memory controller.
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.
Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Rodolfo Giometti [Mon, 15 Oct 2007 09:59:17 +0000 (11:59 +0200)]
PXA USB OHCI: "usb stop" implementation.
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Stefan Roese [Mon, 15 Oct 2007 09:39:00 +0000 (11:39 +0200)]
ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.
This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.
Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Martin Krause [Thu, 27 Sep 2007 12:54:36 +0000 (14:54 +0200)]
TQM866M: fix SDRAM refresh
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 97. This result
in a refresh rate of 4 * 7.8 us at the default clock
50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
CFG_MEMTEST_START uses weird magic involving gd, which fails to
compile. Use hardcoded values instead (we actually know how much RAM
we have on board.)
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