Fabio Estevam [Wed, 27 May 2015 04:11:44 +0000 (01:11 -0300)]
warp: Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE
Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE in order to avoid the following error
when running the dfu command:
=> dfu 0 mmc 0
dfu_get_buf: Could not memalign 0x2000000 bytes
Peter Robinson [Fri, 22 May 2015 16:30:45 +0000 (17:30 +0100)]
imx6: move all standard includes to mx6_common.h
The linux/sizes.h, asm/arch/imx-regs.h, asm/imx-common/gpio.h,
config_cmd_default.h includes are used fairly universally across imx6 boards
so include them in mx6_common.h by default.
We define CONFIG_SYS_NO_FLASH before config_cmd_default.h so that we
don't have to undef CONFIG_CMD_FLASH / CONFIG_CMD_IMLS everywhere.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Tim Harvey [Thu, 21 May 2015 15:40:06 +0000 (08:40 -0700)]
thermal: imx_thermal: increase critical temperature threshold
The CPU temperature grade from OTP is now used to define the critical
threshold at which point we busyloop until we are below, however this
threshold is still too low.
Instead of 20C below the max CPU temperature, change it to 5C defined now
by TEMPERATURE_HOT_DETLA for clarity. Rename 'passive' to 'critical'
as that better defines our use case here. Additionally change the output
of the busyloop message to show the max CPU temperature as well as current.
Before:
CPU Temperature is 101 C, too hot to boot, waiting...
CPU Temperature is 101 C, too hot to boot, waiting...
After:
CPU Temperature (101C) too close to max (105C) waiting...
CPU Temperature (101C) too close to max (105C) waiting...
Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Peng Fan [Wed, 20 May 2015 02:28:48 +0000 (10:28 +0800)]
imx: dma: correct MXS_DMA_ALIGNMENT
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
Masahiro Yamada [Mon, 18 May 2015 06:31:52 +0000 (15:31 +0900)]
ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70x
Due to licensing issues, the files ps7_init.c/h are not able to be
distributed with U-Boot source code. Recent Xilinx tools also
provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot
license.
Prior to this commit, we had to copy ps7_init files into
board/xilinx/zynq/ before the compile.
To be more user-friendly, let's include ps7_init_gpl.c/h for
Zedboard, MicroZed, ZC702, ZC706.
These init code have been taken from the hwplatform_templates
directory of Xilinx SDK 2014.4.
You can still use customized ps7_init_gpl.c/h by enabling
CONFIG_ZYNQ_CUSTOM_INIT. The recommended directory for storing them
is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq
is still supported for backward compatibility. The latter emits
a warning message to prompt users to gradually switch to the new
directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Mon, 18 May 2015 06:31:51 +0000 (15:31 +0900)]
ARM: zynq: add separate configuration for ZC702 and ZC706
Prior to this commit, ZC702 and ZC706 shared the same configuration
and were built as follows:
ZC702: make zynq_zc70x_defconfig && make
ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706
This commit introduces separate configuration for them, which makes
the next commit much easier.
Going forward, the recommended build commands are:
ZC702: make zynq_zc702_defconfig && make
ZC706: make zynq_zc706_defconfig && make
Although the old work flow is still supported, CONFIG_TARGET_ZC70X
has been marked as deprecated. If used, the warning message is
shown to prompt users to switch to the new scheme.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Stefan Agner [Fri, 8 May 2015 17:07:13 +0000 (19:07 +0200)]
mtd: vf610_nfc: enable ONFI detection
This changes enable ONFI detection. The Read ID command now allows
one address byte which is needed for ONFI detection. To read the
ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
CMD code enables one command and one address byte along with reading
data from flash using R/B#, as specified by ONFI.
Stefan Agner [Fri, 8 May 2015 17:07:12 +0000 (19:07 +0200)]
mtd: vf610_nfc: add 32-error correction option for HW ECC
Add option to choose between current 24-error correction and 32-error
correction through Kconfig. 32-error correction allow to use NAND
chips which require up to 8-bit error correction per 512 byte (when
using 2K pages).
Stefan Agner [Fri, 8 May 2015 17:07:11 +0000 (19:07 +0200)]
mtd: vf610_nfc: add Freescale NFC controller configs to Kconfig
This commit allows users to enable/disable the Freescale NFC
controller found in systems like Vybrid (VF610), MPC5125, MCF54418
or Kinetis K70 via Kconfig with more detailed help docs.
Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefano Babic <sbabic@denx.de>
[scottwood: updated vf610twr_nand_defconfig] Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Agner [Fri, 8 May 2015 17:07:10 +0000 (19:07 +0200)]
mtd: vf610_nfc: use in-band bad block table
Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
use the full OOB for hardare ECC purposes. Since there is no
ECC correction on the OOB it is also safer to use in-band area
to store the bad block table marker.
Stefan Agner [Fri, 8 May 2015 17:07:09 +0000 (19:07 +0200)]
mtd: vf610_nfc: implement OOB only read
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
the special handling of OOB (spareonly).
Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.
Stefan Agner [Fri, 8 May 2015 17:07:07 +0000 (19:07 +0200)]
mtd: vf610_nfc: remove read on SEQIN
Since we do not support sub-page writes anyway, reading the page
back to the controller on SEQIN command is not required. Remove
the page read on SEQIN.
However, the column/page values relevant to the SEQIN command, hence
set the column/row address on SEQIN command.
Stefan Agner [Fri, 8 May 2015 17:07:06 +0000 (19:07 +0200)]
mtd: vf610_nfc: remove caching of page in buffer
To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
Stephen Warren [Tue, 14 Apr 2015 14:59:00 +0000 (08:59 -0600)]
nand: fix buffer alignment in new verification feature
On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
buffers.
This prevents cache alignment warnings from being spewed when using
U-Boot to write an updated version of itself to flash on NVIDIA Tegra
Seaboard (after perturbation of stack/data layout in current
u-boot-dm/next branch).
I have validatd (executed) nand_verify(), but I don't think I've executed
nand_verify_page_oob(); testing of that would be useful.
Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Fixes: 59b5a2ad83df ("nand: Add verification functions") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com>
Joe Hershberger [Wed, 20 May 2015 19:27:34 +0000 (14:27 -0500)]
test: Return values from the asserts compatible with cmds
The asserts are sometimes called from the context of the test command
itself so make sure that a return that happens as a result of a failure
is compatible with that command return. When called within a test, the
return value is ignored.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Joe Hershberger [Wed, 20 May 2015 19:27:26 +0000 (14:27 -0500)]
net: Handle ethaddr changes as an env callback
When the ethaddr is changed in the env, update the device pdata at the
same time (only if it is probed for the DM case; only if registered for
the non-DM case). Again this gets us closer to completely non-polled
env needed to simplify the net_loop.
This requires that the NET feature select the REGEX feature.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Wed, 20 May 2015 19:27:23 +0000 (14:27 -0500)]
net: Use env callbacks for net variables
Instead of checking for changes to the env each time we enter the
net_loop, use the env callbacks to update the values of the variables.
Don't update the variables when the source was programmatic, since the
variables were the source of the new value.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Joe Hershberger [Wed, 20 May 2015 19:27:21 +0000 (14:27 -0500)]
env: Distinguish finer between source of env change
We already could tell the difference in the callback between an import
and "other" which we called interactive. Now add further distinction
between interactive (i.e. running env set / env edit / env ask / etc.
from the U-Boot command line) and programmatic (i.e. when u-boot source
calls any variant of setenv() ).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Joe Hershberger [Wed, 20 May 2015 19:27:18 +0000 (14:27 -0500)]
env: Simplify the reverse_strstr() interface
The logic to find the whole matching name was split needlessly between
the reverse_strstr function and its caller. Fully contain it to make the
interface for calling it more consistent.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Wed, 20 May 2015 19:27:14 +0000 (14:27 -0500)]
sandbox: Cleanup order and extra defines in defconfig
The defconfigs should not be edited directly. They should be generated
by editing the .config (through menuconfig or whatever) and then run
make savedefconfig to have the Kconfig system generate a clean defconfig
I did this for sandbox here with no actual changes.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Alison Wang [Tue, 21 Apr 2015 08:04:38 +0000 (16:04 +0800)]
arm: ls102xa: Adjust the load address of U-Boot for NOR boot
The original load address of U-Boot is 0x67f80000. The address
space of NOR flash is 0x60000000 to 0x67ffffff. It will cause
the size of u-boot couldn't be larger than 512K. As more features
are supported in u-boot, the size of u-boot is larger than 512K.
To fix this issue, the load address of U-Boot for NOR boot is
adjusted to 0x60100000.
In RCW, the PBI command needs to change as follows:
.pbi
-write 0xee0200, 0x67f80000
+write 0xee0200, 0x60100000
.end
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Joe Hershberger [Mon, 4 May 2015 19:55:14 +0000 (14:55 -0500)]
net: Remove all references to CONFIG_ETHADDR and friends
We really don't want boards defining fixed MAC addresses in their config
so we just remove the option to set it in a fixed way. If you must have
a MAC address that was not provisioned, then use the random MAC address
functionality.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 13 May 2015 11:40:40 +0000 (13:40 +0200)]
net: phy: Add support for all targets which requires MANUAL_RELOC
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Shengzhou Liu [Fri, 24 Apr 2015 08:57:17 +0000 (16:57 +0800)]
net/phy: refactor RTL8211F initialization
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Tue, 24 Mar 2015 07:41:49 +0000 (02:41 -0500)]
net: Update hardware MAC address if it changes in env
When the ethaddr changes in the env, the hardware should also be updated
so that MAC filtering will work properly without resetting U-Boot.
Also remove the manual calls to set the hwaddr that was included in a
few drivers as a result of the framework not doing it.
Reported-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.
This is required to e.g. enable USB gadget.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: VBUS detection function fixup in g_dnl_board_usb_cable_connected
sunxi_usbc_vbus_detect was renamed to sunxi_usb_phy_vbus_detect but
g_dnl_board_usb_cable_connected was still using the old name, breaking the build
when USB gadget is enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Thu, 14 May 2015 16:52:54 +0000 (18:52 +0200)]
sunxi: video: Fix lvds panel support for sun6i+
We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 13 May 2015 13:00:46 +0000 (15:00 +0200)]
sunxi: Make DRAM_ODT_EN Kconfig setting a bool
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.
Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.
For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Laurent Itti [Wed, 6 May 2015 00:02:00 +0000 (17:02 -0700)]
sunxi: add support for UART2 on A23/A33
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3
Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Tue, 5 May 2015 11:13:36 +0000 (13:13 +0200)]
console: Fix pre-console flushing via cfb_console being very slow
On my A10 OlinuxIno Lime I noticed a huge (5+ seconds) delay coming from
console_init_r. This turns out to be caused by the preconsole buffer flushing
to the cfb_console. The Lime only has a 16 bit memory bus and that is already
heavy used to scan out the 1920x1080 framebuffer.
The problem is that print_pre_console_buffer() was printing the buffer once
character at a time and the cfb_console code then ends up doing a cache-flush
for touched display lines for each character.
This commit fixes this by first building a 0 terminated buffer and then
printing it in one puts() call, avoiding unnecessary cache flushes.
This changes the time for the flush from 5+ seconds to not noticable.
The downside of this approach is that the pre-console buffer needs to fit
on the stack, this is not that much to ask since we are talking about plain
text here. This commit also adjusts the sunxi CONFIG_PRE_CON_BUF_SZ to
actually fit on the stack. Sunxi currently is the only user of the pre-console
code so no other boards need to be adjusted.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tim Harvey [Mon, 18 May 2015 13:56:46 +0000 (06:56 -0700)]
imx: mx6: add display of CPU temperature grade in print_cpuinfo()
When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
along with the current temperature.
Before:
CPU: Temperature 42 C
After:
CPU: Automotive temperature grade (-40C to 125C) at 42C
CPU: Industrial temperature grade (-40C to 105C) at 42C
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Mon, 18 May 2015 13:56:45 +0000 (06:56 -0700)]
imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
projects / u-boot / log