Vignesh R [Wed, 6 Jul 2016 04:56:03 +0000 (10:26 +0530)]
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:57 +0000 (10:20 +0530)]
ARM: dts: K2G: Add support for QSPI controller
K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:56 +0000 (10:20 +0530)]
spi: cadence_quadspi: Enable QUAD mode based on DT data
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:55 +0000 (10:20 +0530)]
spi: cadence_qspi_apb: Support 32 bit AHB address
AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:05 +0000 (09:59 +0530)]
ARM: dts: k2g: add support for Davinci SPI controller
K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:03 +0000 (09:59 +0530)]
ARM: dts: k2l: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:01 +0000 (09:59 +0530)]
ARM: dts: k2e: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:28:59 +0000 (09:58 +0530)]
ARM: dts: k2hk: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:28:55 +0000 (09:58 +0530)]
dm: core: implement dev_map_physmem()
This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R <vigneshr@ti.com> Suggested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------
In this change we disable struct arch_global_data in ASM which fixes
the issue above.
Alexey Brodkin [Thu, 16 Jun 2016 08:55:00 +0000 (10:55 +0200)]
arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HS
Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.
Quentin Schulz [Fri, 24 Jun 2016 12:33:35 +0000 (14:33 +0200)]
sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)
The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.
The DTS file is identical to the one submitted to the upstream kernel.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Olliver Schinagl [Mon, 13 Jun 2016 16:13:07 +0000 (18:13 +0200)]
sunxi: Add missing boot_media fields in the SPL header
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Mon, 27 Jun 2016 07:23:02 +0000 (16:23 +0900)]
autoboot: rename abortboot_{keyed, normal} to __abortboot
Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
Masahiro Yamada [Mon, 27 Jun 2016 07:23:01 +0000 (16:23 +0900)]
autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECK
As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.
To sum up, the autoboot behaves as follows:
[1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
autoboot with no delay, with no check for abort
[3] CONFIG_BOOTDELAY=-1
disable autoboot
[4] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK. We can control all the
cases only by CONFIG_BOOTDELAY, like this:
[1] CONFIG_BOOTDELAY=0
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=-1
disable autoboot
[3] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
This commit converts the logic as follow:
CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
--> CONFIG_BOOTDELAY=-2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Christian Riesch <christian.riesch@omicronenergy.com> Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.
Furthermore, update and cleanup associated MAINTAINERS file.
Masahiro Yamada [Wed, 29 Jun 2016 10:39:03 +0000 (19:39 +0900)]
ARM: uniphier: add external IRQ setup code
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:59 +0000 (19:38 +0900)]
pinctrl: uniphier: support pin configuration for dedicated pins
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:58 +0000 (19:38 +0900)]
pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:57 +0000 (19:38 +0900)]
pinctrl: uniphier: allow to have pinctrl node under syscon node
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Bin Meng [Wed, 22 Jun 2016 09:30:03 +0000 (02:30 -0700)]
x86: coreboot: Remove the dummy pch driver
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Abhimanyu Saini [Tue, 14 Jun 2016 07:48:31 +0000 (13:18 +0530)]
armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with similar SoCs that
have different cores like LS2080A and LS2088A.
This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Wed, 15 Jun 2016 02:53:02 +0000 (10:53 +0800)]
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ye Li [Wed, 15 Jun 2016 02:53:01 +0000 (10:53 +0800)]
fsl_esdhc: Update clock enable bits for USDHC
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Wed, 15 Jun 2016 02:53:00 +0000 (10:53 +0800)]
mmc: fsl: reset to normal boot mode when eMMC fast boot
When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will generate different IVT headers according
to boot medias.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Francois Retief <fgretief@spaceteq.co.za> Cc: Tom Rini <trini@konsulko.com>
Steve Rae [Tue, 7 Jun 2016 18:19:38 +0000 (11:19 -0700)]
fastboot: sparse: implement reserve()
In order to process the CHUNK_TYPE_DONT_CARE properly, there is
a requirement to be able to 'reserve' a specified number of blocks
in the storage media. Because of the special handling of "bad blocks"
in NAND devices, this is implemented in a storage abstraction function.
Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
While retaining the storage abstraction feature, this is the second
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
While retaining the storage abstraction feature, this is the first
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
Jaehoon Chung [Fri, 13 May 2016 14:37:44 +0000 (23:37 +0900)]
mmc: dw_mmc: fix the wrong AND operation
These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Heiko Schocher [Wed, 25 May 2016 05:23:48 +0000 (07:23 +0200)]
arm: at91: taurus/axm: add DM and DTS support
add DM and DTS support for the at91 based siemens
boards.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Heiko Schocher [Wed, 25 May 2016 05:23:47 +0000 (07:23 +0200)]
arm: at91: smartweb: add DM and DTS support
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Marek Vasut [Sat, 14 May 2016 21:42:28 +0000 (23:42 +0200)]
ARM: at91: Don't invoke spl_boot_device() twice
Since the spl_boot_mode() is now passed the boot device to boot from,
make use of it instead of inquiring for the boot device again. This
allows board_boot_order() to function correctly.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Marek Vasut [Sat, 14 May 2016 21:42:07 +0000 (23:42 +0200)]
common: Pass the boot device into spl_boot_mode()
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
Peng Fan [Mon, 20 Jun 2016 01:43:09 +0000 (09:43 +0800)]
ehci: mx7: fix otg id detection
The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the
OTG ID detection, not set it. When the bit is set, the ACA
Resistance Detection is enabled, which disables the OTG ID
detection, because the internal pull up is off.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Masahiro Yamada [Thu, 23 Jun 2016 04:53:46 +0000 (13:53 +0900)]
kbuild: avoid race between dtbs and dt/dt.dtb targets
If the final targets depend on both "dtbs" and "dts/dt.dtb",
and -j option is given to the command line, multiple threads
descend into the dts/ directory, which causes build error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Alexander Graf [Wed, 22 Jun 2016 23:15:38 +0000 (01:15 +0200)]
efi_loader: Fix typo in distro script
The distro script is supposed to use the internal fdt as fallback if we
find no viable other option. However, we're missing a space key to actually
make that work.
Add the space, so we can successfully load an EFI blob even when there is
no device tree provided on the target device.
Stephen Warren [Tue, 21 Jun 2016 19:32:07 +0000 (13:32 -0600)]
clk: sandbox: don't check clk ID against 0
clk->id is unsigned, so it can't be < 0. Remove the check for that.
FWIW, this issue was introduced when the clock API converted e.g.
clk_get_rate()'s clock ID parameter from an int to an unsigned long
(with a struct clk), without removing this check.
Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style") Reported-by: Coverity Scan Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Andre Renaud [Mon, 20 Jun 2016 01:25:25 +0000 (19:25 -0600)]
mtd: nand: Drop a blank line in nand_wait()
This empty line should not be there. Remove it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Signed-off-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log