Heiko Stübner [Thu, 23 Feb 2017 16:30:40 +0000 (17:30 +0100)]
rockchip: rk3188: drop CONFIG_SYS_NO_FLASH
Commit e856bdcfb492 ("flash: complete CONFIG_SYS_NO_FLASH move with renaming")
obsoleted the CONFIG_SYS_NO_FLASH option, which still is in our
rk3188_common.h header, resulting in warnings like
The following new ad-hoc CONFIG options were detected:
CONFIG_SYS_NO_FLASH
So also drop it from the rk3188 header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:56 +0000 (15:37 +0800)]
rockchip: rk3328: add defconfig for evb-rk3328
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:55 +0000 (15:37 +0800)]
rockchip: rk3328: add evb-rk3328 support
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:54 +0000 (15:37 +0800)]
rockchip: rk3328: add sysreset driver
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:53 +0000 (15:37 +0800)]
rockchip: rk3328: add pinctrl driver
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:51 +0000 (15:37 +0800)]
rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:50 +0000 (15:37 +0800)]
rockchip: rk3328: add device tree file
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 22 Feb 2017 08:56:38 +0000 (16:56 +0800)]
rockchip: config: rk3399: enable SPL config for evb-rk3399
Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 08:09:05 +0000 (16:09 +0800)]
rockchip: arm64: rk3399: add SPL support
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 22 Feb 2017 08:56:36 +0000 (16:56 +0800)]
rockchip: dts: rk3399: update for spl require driver
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Mon, 20 Feb 2017 03:08:16 +0000 (11:08 +0800)]
rockchip: tinker: configs: use correct mmc instance as boot target device
We are using wrong mmc instance as boot target device now. below Jaehoon Chung's
patch use mmc alias which correct it. That make tinker board can not find mmc
device. So give it correct mmc device instance.
Heiko Stübner [Sat, 18 Feb 2017 18:46:38 +0000 (19:46 +0100)]
rockchip: rk3188: Add main, spl and tpl boards
The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:37 +0000 (19:46 +0100)]
rockchip: rk3188: Add sdram driver
The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.
There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.
More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:36 +0000 (19:46 +0100)]
rockchip: rk3188: Add core support
Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:35 +0000 (19:46 +0100)]
rockchip: rk3188: Add core devicetree files
The rk3188 shares a lot of peripherals with the rk3066 and thus
has a common include called rk3xxx.dtsi. Add both this one and
the specialized rk3188 on top of it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Bring in required device clock binding files from Linux.
The clock trees for rk3066 and rk3188 are largely similar, which makes
them share the common parts in a shared header. While we focus on rk3188
for now, bring in both headers already for completeness sake.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:27 +0000 (19:46 +0100)]
rockchip: mkimage: Allow encoding of loader code in spl images
Rockchip SoCs allow the spl code to be rc4-encoded, not only the
image header, but only newer SoCs allow this encoding to be disabled.
The rk3188 is not part of those and requires its boot code to be
rc4-encoded with the regular key. So add the ability to do this
encoding via a setting on a per-soc basis when building spl images.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:26 +0000 (19:46 +0100)]
rockchip: Move bootrom-related declarations to a header
So far spl-boards have declared the back_to_brom() function as simple
extern in the files themself. That doesn't scale well if every boards
defines this on its own.
Therefore move the declarations to a bootrom header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:25 +0000 (19:46 +0100)]
rockchip: Move bootrom helper compilation to a hidden option
Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers
compilation of the bootrom hook-code as well as enabling the
behaviour of loading the full U-Boot via the boot.
New added socs may always need the bootrom code, while still
being able to decide between loading U-Boot regularly or via
the bootrom separately.
So move the compilation of the bootrom code to a hidden option
that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also
be selected by other parts.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:24 +0000 (19:46 +0100)]
rockchip: rk3288: sdram: style fixes from rk3188 sdram review
The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar
and we want to unify things once all 3 work as expected.
Therefore try to keep the rk3288 sdram driver in line by applying the
general review comments received for the rk3188 variant to it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:22 +0000 (19:46 +0100)]
rockchip: clk: rk3288: limit gpll and cpll init to SPL build
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:21 +0000 (19:46 +0100)]
dm: allow limiting pre-reloc markings to spl or tpl
Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.
So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.
The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 13 Feb 2017 09:38:59 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: syscon addition for rk3399
rk3399 has different syscon registers which may used in spl,
add to support rk3399 spl.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:58 +0000 (17:38 +0800)]
rockchip: pinctrl: rk3399: add the of-platdata support
Do not use the API which of-platdata not support.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:57 +0000 (17:38 +0800)]
rockchip: sdhci: rk3399: update driver to support of-platdata
Change some API in order to enable of-platdata.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:55 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h
rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Wed, 15 Mar 2017 14:43:28 +0000 (08:43 -0600)]
spl: Add spl_early_init()
At present malloc_base/_limit/_ptr are not initialised in spl_init() when
we call spl_init() in board_init_f(). This is due to a recent change aimed
at avoiding overwriting the malloc area set up on some boards by
spl_relocate_stack_gd().
However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
skip setting up the memory area in spl_init() which is obviously wrong.
To fix this, add a new function spl_early_init() which can be called in
board_init_f().
Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit) Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Rewrote spl_{,early_}init() to avoid duplicate code:
Rewrite/expand commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Masahiro Yamada [Thu, 9 Mar 2017 07:28:25 +0000 (16:28 +0900)]
arm64: booti: allow to place kernel image anywhere in physical memory
At first, the ARM64 Linux booting requirement recommended that the
kernel image be placed text_offset bytes from 2MB aligned base near
the start of usable system RAM because memory below that base address
was unusable at that time.
This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
allow kernel Image to be loaded anywhere in physical memory").
Since then, the bit 3 of the flags field indicates the tolerance
of the kernel physical placement. If this bit is set, the 2MB
aligned base may be anywhere in physical memory. For details, see
Documentation/arm64/booting.txt of Linux.
The booti command should be also relaxed. If the bit 3 is set,
images->ep is respected, and the image is placed at the nearest
bootable location. Otherwise, it is relocated to the start of the
system RAM to keep the original behavior.
Another wrinkle we need to take care of is the unknown endianness of
text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
We can detect this based on the image_size field. If the field is
zero, just use a fixed offset 0x80000.
Masahiro Yamada [Mon, 13 Mar 2017 08:43:16 +0000 (17:43 +0900)]
tools: fix cross-compiling tools when HOSTCC is overridden
Richard reported U-Boot tools issues in OpenEmbedded/Yocto project.
OE needs to be able to change the default compiler. If we pass in
HOSTCC through the make command, it overwrites all HOSTCC instances,
including ones in tools/Makefile and tools/env/Makefile, which breaks
"make cross_tools" and "make env", respectively.
Add "override" directives to avoid overriding HOSTCC instances that
really need to point to the cross-compiler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Ladislav Michl [Sat, 18 Feb 2017 23:24:49 +0000 (00:24 +0100)]
igep00x0: fixup FDT according to detected flash type
Leave only detected flash type enabled in FTD as otherwise GPMC CS is
claimed (and never freed) by Linux, causing 'concurent' flash type
not to be probed.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Ladislav Michl [Sat, 18 Feb 2017 23:23:39 +0000 (00:23 +0100)]
igep00x0: disable environment
ISEE's U-Boot and Linux are using 1bit ECC scheme, while we
switched to 8bit ECC to fullfill flash specification requirements.
However when trying to run U-Boot on board with 1bit ECC'd data
on flash, UBI code takes several minutes to pass scan as reading
of every block ends with ecc error (which is also printed on
console).
So, until proper solution is developed, disable environment
alltogether.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Patrice Chotard [Tue, 21 Feb 2017 12:37:12 +0000 (13:37 +0100)]
board: Add STMicroelectronics STiH410-B2260 support
This is a 96Board compliant board based on STiH410 SoC:
- 1GB DDR
- On-Board USB combo WiFi/Bluetooth RTL8723BU
with PCB soldered antenna
- Ethernet 1000-BaseT
- SATA
- HDMI
- 2 x USB2.0 type A
- 1 x USB2.0 type micro-AB
- SD card slot
- High speed connector (SD/I2C/USB interfaces)
- Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 21 Feb 2017 12:37:09 +0000 (13:37 +0100)]
STiH410: Add STi SDHCI driver
Add SDHCI host controller found on STMicroelectronics SoCs
On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live
inside a dedicated flashSS sub-system that provides an extend subset
of registers that can be used to configure the Arasan MMC/SD Host
Controller.
This means, that the SDHCI Arasan Controller can be configured to be
eMMC4.5 or 4.3 spec compliant.
W/o these settings the SDHCI will configure and use the MMC/SD
controller with limited features e.g. PIO mode, no DMA, no HS etc.
Patrice Chotard [Tue, 21 Feb 2017 12:37:07 +0000 (13:37 +0100)]
STiH410: Add STi serial driver
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP
is common across other STMicroelectronics SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Phil Edworthy [Fri, 17 Feb 2017 08:22:17 +0000 (08:22 +0000)]
armv7m: Add SysTick timer driver
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
The number of reference clock ticks that correspond to 10ms is normally
defined in the SysTick Calibration register's TENMS field. However, on some
devices this is wrong, so this driver allows the clock rate to be defined
using CONFIG_SYS_HZ_CLOCK.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
Lokesh Vutla [Wed, 15 Feb 2017 13:12:54 +0000 (18:42 +0530)]
tools: omapimage: Fix size in header
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage generates a gp header
only with size of the image as size field. Fix it
arm: omap3: Bring back ARM errata workaround 725233
The workaround for ARM errata 725233 had been lost since
commit 45bf05854bc94e (armv7: adapt omap3 to the new cache
maintenance framework). Bring it back in order to avoid
very difficult to reproduce, but actually encountered in
the wild CPU deadlocks when running software rendered
X11 desktop on OMAP3530 hardware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Migrate to Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
arm: omap3: Compile clock.c with -marm option to unbreak OMAP3530
Boards with OMAP3530 SoC fail to boot since commit bd2c4522c26d5
("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)")
because it enabled the use of Thumb2 for the SPL.
Experiments have shown that the deadlock happens in the
prcm_init() function from 'arch/arm/mach-omap2/omap3/clock.c'.
This patch enforces the compilation of clock.c source file in
ARM mode and makes the deadlock disappear. We are yet to figure
out the root cause of the problem. Still this is somewhat
better than having non-bootable boards for years.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Mon, 6 Mar 2017 20:28:25 +0000 (05:28 +0900)]
ARM: uniphier: set DRAM_SPARSE flag for LD21 boards
Commit 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from
board parameters") accidentally unset the DRAM_SPARSE flag, and
changed the physical map of the DRAM channels. Revive the original
behavior.
Fixes: 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board parameters") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Shunji Sato <sato.shunji@socionext.com>
arm: omap-common: Fix typo in CONFIG_OMAP54XX guard
Some initialization was unintentionally being skipped on omap5.
Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX") Signed-off-by: Matthijs van Duin <matthijsvanduin@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Ladislav Michl [Mon, 6 Mar 2017 12:54:30 +0000 (13:54 +0100)]
arm: OMAP2+: nandecc: propagate error to command return status
Currently nandecc returns zero even if underlaying
omap_nand_switch_ecc function fails. Fix that by
propagating error returned to command return value.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 7 Mar 2017 12:13:42 +0000 (07:13 -0500)]
ARM: Migrate errata to Kconfig
This moves all of the current ARM errata from various header files and in to
Kconfig. This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config. We now just select these once at the higher level in Kconfig
Tom Rini [Fri, 3 Mar 2017 20:33:30 +0000 (15:33 -0500)]
am335x_evm: Switch to using imply keyword
These particular SPL options are part of what the ROM provides, but for
compatibility with how we have previously used them, move them to being
implied by the board being selected.
Tom Rini [Fri, 3 Mar 2017 20:33:29 +0000 (15:33 -0500)]
kconfiglib.py: Kludge in 'imply' support
Currently upstream does not yet understand the imply keyword. For what
we use kconfiglib.py for today, this is OK. We only need to be able to
evaluate in order to make boards.cfg and none of those choices will
depend on how imply evaluates out.
Ryan Harkin [Thu, 2 Mar 2017 17:45:16 +0000 (17:45 +0000)]
do_smhload: fix return code
do_smhload was using a ulong to store the return value from
smh_load_file. That returns an int, where -1 indicates an error. As a
ulong will never be negative, smh_load_file errors were not detected and
so_smhload always returned zero.
Also, when errors were spotted, do_smhload was returning 1, rather than
the enumeration CMD_RET_FAILURE (which is also 1).
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 27 Feb 2017 06:24:45 +0000 (15:24 +0900)]
kbuild: turn of dtc unit address warnings by default
DTC 1.4.2 or later checks DT unit-address without reg property and
vice-versa, and generates lots of warnings. Fixing DT files will
take for a while. Until then, let's turn off the check unless
building with W=*.
Introduce a new helper dtc-option to check if the option is supported
in order to suppress warnings on older versions.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Adam Ford [Wed, 8 Mar 2017 03:27:52 +0000 (21:27 -0600)]
omap3_logic: Move SPL Stack into SDRAM
A previous patch broke the board. This patch will add missing part
from the previous patch and also move the SPL Stack into SDRAM at
0x82000000.
Tested with GCC 4.8.2 and GCC 6.2
Fixes: 0959649dc6d9 ("omap3_logic: Switch to simple malloco in SPL") Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
- Keep CONFIG_SPL_SYS_MALLOC_SIMPLE
- Add CONFIG_SYS_MALLOC_F_LEN=0x2000 (8 MB)
Andre Przywara [Mon, 6 Mar 2017 01:13:38 +0000 (01:13 +0000)]
video: cfb_console: fix 32-bit display on 64-bit architectures
"unsigned long" is a lousy data type when it comes to match peripheral
hardware registers with a fixed size.
Just do the obvious and match a 32-bit display format with an "u32"
data type for casting.
This fixes the logo display on 64-bit architectures, which produced
a black line on the right side of the logo with non-black backgrounds.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Nathan Rossi [Sun, 5 Mar 2017 14:36:23 +0000 (00:36 +1000)]
net: zynq_gem: Fix masking of supported phydev features
When the zynq_gem driver initializes the phy it sets the supported
features that the phy can support and advertise. However instead of
masking the supported features such that it limits the available
features it sets the phy to have the exact supported features of the
zynq_gem. This is problematic as it will enable features that a phy does
not have or cannot advertise.
Specifically this appears as an issue when using a phy that is only
capable of 10/100, but the zynq_gem driver will override this and try to
enable and advertise 10/100/1000.
Reported-by: Arno Steffens <star@gmx.li> Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN") Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Tested-by: Arno Steffens <star@gmx.li> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Wenyou Yang [Tue, 14 Feb 2017 08:24:40 +0000 (16:24 +0800)]
net: macb: Fix ETH not found when clock not support
For the boards such as smartweb on which the clock driver isn't
supported, the ethernet fail to be found when booting up with
the below log.
---8<---
Net: No ethernet found.
--->8---
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Philipp Tomsich [Wed, 1 Mar 2017 20:04:15 +0000 (21:04 +0100)]
armv8: spl: Call spl_relocate_stack_gd for ARMv8
As part of the startup process for boards using the SPL, we need to
call spl_relocate_stack_gd. This is needed to set up malloc with its
DRAM buffer.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Albert ARIBAUD [Mon, 27 Feb 2017 19:19:07 +0000 (20:19 +0100)]
armv5te: make 'ret lr' produce iinterworking 'bx lr'
Current ARM assembler helper for the 'return to caller' pseudo-instruction
turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain
in its current ARM state even when the routine doing the 'ret' was called
from Thumb-1 state, triggering an undefined instruction exception.
This causes early run-time failures in all boards compiled using the Thumb-1
instruction set (for instance the Open-RD family).
ARMv5TE supports 'bx lr' which properly implements interworking and thus
correctly returns to Thumb-1 state from ARM state.
This change makes 'ret lr' turn into 'bx lr' for ARMv5TE.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Andrew F. Davis [Wed, 22 Feb 2017 23:46:39 +0000 (17:46 -0600)]
arm: mach-omap2: Flush cache after FIT post-processing image
After we authenticate/decrypt an image we need to flush the caches
as they may still contain bits of the encrypted image. This will
cause failures if we attempt to jump to this image.
Reported-by: Yogesh Siraswar<yogeshs@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
projects / u-boot / log