Simon Glass [Wed, 5 Dec 2012 14:46:33 +0000 (14:46 +0000)]
sha1: Use const where possible, and unsigned for input len
In preparation for making the hash function common, we may as well use
const where we can. Also the input length cannot be negative, but may
be very large, so use unsigned.
designware_i2c: Fixed the setting of the i2c bus speed
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.
This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Marek Vasut [Fri, 30 Nov 2012 18:17:07 +0000 (18:17 +0000)]
mxs: i2c: Implement algorithm to set up arbitrary i2c speed
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.
The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Fri, 30 Nov 2012 18:17:06 +0000 (18:17 +0000)]
mxs: i2c: Restore speed setting after block reset
The I2C block reset configures the I2C bus speed to strange value.
Read the I2C speed from the block before reseting the block and
restore it afterwards, so the I2C operates correctly. This issue
can be replicated by doing unsuccessful I2C transfer, after such
transfer finishes, the I2C block clock speed is misconfigured.
Marek Vasut [Mon, 12 Nov 2012 14:34:31 +0000 (14:34 +0000)]
i2c: mxs: Fix TIMING2 register value
According to FSL, the value in the TIMING2 register shall be 0x00300030
instead of what's written in the datasheet. This new value correlates
with older STMP36xx datasheet. Issues were detected in Linux when this
register was misconfigured, so write this correct value.
Marek Vasut [Mon, 12 Nov 2012 14:34:28 +0000 (14:34 +0000)]
i2c: mxs: Abstract out the MXS I2C speed setup
This patch pulls out the I2C speed setup from the i2c_init() call
and implements the bus configuration lookup table with register
values that needs to be programmed into the I2C IP to run at
particular speed.
This patch is a first step towards implementing run-time I2C bus
speed configuration for the MXS I2C IP.
Marek Vasut [Mon, 12 Nov 2012 14:34:25 +0000 (14:34 +0000)]
i2c: Use __weak instead of __attribute__((weak, alias))
Use __weak from linux/compiler.h instead of __attribute__((weak, alias))
to define overridable function. This patch is intended as a cleanup patch
to bring some consistency into the code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
In file included from ubifs.h:2137:0,
from ubifs.c:26:
misc.h: In function 'ubifs_zn_dirty':
misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default]
../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *'
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Zhi-zhou Zhang [Sat, 24 Nov 2012 05:07:12 +0000 (05:07 +0000)]
MIPS: fix a latent bug on initialize $gp
If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned.
then the following ld insntrustion generates a Adel exception.
So here make _gp be always aligned in 8 bytes.
Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The filename buffer is allocated dynamically. It must be cache aligned.
Moreover, it is necessary to erase its content before we use it for
file name operations.
This prevents from corruption of written file names.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Łukasz Majewski [Wed, 5 Dec 2012 08:06:38 +0000 (08:06 +0000)]
fs:ext4:write: Store block device descriptor in file system structure
The device block descriptor (block_dev_desc_t) )shall be stored at
ext4 early code (at ext4fs_set_blk_dev in this case) to be available
for latter use (like put_ext4()).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Łukasz Majewski [Wed, 5 Dec 2012 08:06:37 +0000 (08:06 +0000)]
fs:ext4:write: Add lldiv and do_div to perform 64-32 bits division
The ext4write code has been using direct calls to 64-32 division
(/ and %).
Officially supported u-boot toolchains (eldk-5.[12].x) generate calls
to __aeabi_uldivmod(), which is niether defined in the toolchain libs
nor u-boot source tree.
Due to that, when the ext4write command has been executed, "undefined
instruction" execption was generated (since the __aeabi_uldivmod()
is not provided).
To fix this error, lldiv() for division and do_div() for modulo have
been used.
Those two functions are recommended for performing 64-32 bit number
division in u-boot.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Joshua Housh [Sun, 2 Dec 2012 17:09:26 +0000 (17:09 +0000)]
serial_pl011: Set RTS during initialization
If the pl011 is connected to another device which has hardware
flow-control on, characters are never received by the pl011.
Asserting RTS when flow-control is off will have no effect.
This is in line with how Linux behaves.
Signed-off-by: Joshua Housh <joshua.housh@calxeda.com> Tested-by: Marek Vasut <marex@denx.de>
Stefan Reinauer [Sat, 3 Nov 2012 11:41:39 +0000 (11:41 +0000)]
x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.
monitor_flash_len is unused, drop it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Sat, 3 Nov 2012 11:41:37 +0000 (11:41 +0000)]
x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.
This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.
Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Mon, 3 Dec 2012 13:59:20 +0000 (13:59 +0000)]
x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.
Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Duncan Laurie [Mon, 3 Dec 2012 13:59:00 +0000 (13:59 +0000)]
x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move. Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Dec 2012 13:56:51 +0000 (13:56 +0000)]
x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Stefan Reinauer [Sat, 3 Nov 2012 11:41:29 +0000 (11:41 +0000)]
x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.
This can address the security risk of untrusted data being used during boot.
When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.
Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Gabe Black [Sat, 3 Nov 2012 11:41:28 +0000 (11:41 +0000)]
x86: Add back cold- and warm-boot flags
These were removed, but actually are useful.
Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.
We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.
Gabe Black [Mon, 3 Dec 2012 14:26:08 +0000 (14:26 +0000)]
x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.
Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.
Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Gabe Black [Sat, 3 Nov 2012 11:41:24 +0000 (11:41 +0000)]
x86: Reorder x86's post relocation memory layout
This changes the layout in decreasing addresses from:
1. Stack
2. Sections in the image
3. Heap
to
1. Sections in the image
2. Heap
3. Stack
This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.
Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Gabe Black [Tue, 23 Oct 2012 18:04:46 +0000 (18:04 +0000)]
x86: Implement arch_phys_memset so that it can wipe memory above 4GB
Implement arch_phys_memset so that it can set memory at physical addresses
above 4GB using PAE paging. Because there are only 5 page tables in PAE mode,
1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The
tables must be 4K page aligned and are declared that way, and because U-Boot
starts as 4K aligned and the relocation code relocates it to a 4K aligned
address, the tables work as intended.
While paging is turned on, all 4GB are identity mapped except for one 2MB
page which is used as the window into high memory. This way, U-Boot will
continue to work as expected when running code that expects to access memory
freely, but the code can still get at high memory through its window.
The window is put at 2MB so that it's 2MB page aligned, low in memory to be
out of the way of things U-Boot is likely to care about, and above the lowest
1MB where lots of random things live.
Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Gabe Black [Sun, 2 Dec 2012 04:55:18 +0000 (04:55 +0000)]
Introduce arch_phys_memset which works like memset but on physical memory
The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.
Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Oct 2012 18:04:40 +0000 (18:04 +0000)]
x86: Fix indirect jmp warning in zimage.c
This fixes the following warning:
zimage.c:312: Warning: indirect jmp without `*'
Also fixed these warnings to keep checkpatch quiet:
warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline
Gabe Black [Tue, 23 Oct 2012 18:04:35 +0000 (18:04 +0000)]
x86: Fill in the dram info using the e820 map on coreboot/x86
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.
This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.
Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Tue, 23 Oct 2012 18:04:34 +0000 (18:04 +0000)]
x86: Add a CBMEM timestamp generated right before the kernel startup.
To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Tue, 23 Oct 2012 18:04:33 +0000 (18:04 +0000)]
x86: Enable coreboot timestamp facility support in u-boot.
This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.
Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.
The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.
Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Bill Richardson [Sat, 20 Oct 2012 11:44:36 +0000 (11:44 +0000)]
x86: gpio: Add additional GPIO banks to the ICH6 driver
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.
BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
them all, or even keep track of the new ones.
So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.
Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Jerry Huang [Tue, 6 Nov 2012 15:33:12 +0000 (15:33 +0000)]
part: check each variable for capability calculation
In order to calculate the capability, we use the below expression to check:
((dev_desc->lba * dev_desc->blksz)>0L)
If the capability is greater than 4GB (e.g. 8GB = 8 * 1024 * 104 * 1024),
the result will overflow, the low 32bit may be zero.
Therefore, change to check each variable to fix this potential issue.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Joe Hershberger [Tue, 30 Oct 2012 15:55:21 +0000 (15:55 +0000)]
MAKEALL: Add options for incremental building
--continue will allow you to <ctrl-c> the MAKEALL and pick up where
you left off.
--rebuild-errors will allow you to rebuild only those boards which
had trouble on the last run of MAKEALL, allowing you to quickly test
a simple fix on just those boards.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Joe Hershberger [Tue, 30 Oct 2012 15:55:20 +0000 (15:55 +0000)]
MAKEALL: Fix kill_children
When building in parallel, make sure that we look up the children
based on the the actual process group id instead of just assuming
that the MAKEALL pid is the process group id.
Also ensure that logs from incomplete builds are deleted in the
process.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 24 Aug 2012 15:36:53 +0000 (17:36 +0200)]
Makefile: Add target for combined spl/u-boot.bin & u-boot.img
This new make target "u-boot-img.bin" consists of the U-Boot
SPL image with the real, full-blown U-Boot image directly
attached to it. The full-blown U-Boot image has the mkimage
header included, with its load-address and entry-point.
This will be used by the upcoming a3m071 MPC5200 board port.
Stefan Roese [Thu, 16 Aug 2012 15:54:52 +0000 (17:54 +0200)]
Makefile: Add possibility to set entry-point for u-boot.img
This patch enabled boards using the SPL framework to set
an entry point in the U-Boot mkimage image "u-boot.img".
Until now the entry point in the header has been set to 0.
By setting CONFIG_SYS_UBOOT_START in the board header, boards
can override this default location.
This will be used by the upcoming a3m071 MPC5200 board port.
Stefan Roese [Wed, 26 Sep 2012 11:01:00 +0000 (13:01 +0200)]
env: Enable getenv_f() for SPL_BUILD
With this patch, getenv_f() can be included easily into the SPL
binary. With this, SPL boards can now use getenv_f() to read
environment variables (e.g. to detect if the OS or U-Boot shall
be executed).
In the approach this is done for env stored in NOR flash, as this
will be used by an upcoming MPC5200 board port.
Stefan Roese [Thu, 23 Aug 2012 06:34:21 +0000 (08:34 +0200)]
SPL: Port SPL framework to powerpc
This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.
timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.
Stefan Reinauer [Sat, 20 Oct 2012 12:33:16 +0000 (12:33 +0000)]
x86: Don't spam POST80 codes with slow IO functions
This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.
It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log