Akshay Saraswat [Mon, 26 May 2014 13:50:08 +0000 (19:20 +0530)]
Exynos5420: DMC: Add software read leveling
Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Doug Anderson [Mon, 26 May 2014 13:49:05 +0000 (19:19 +0530)]
DMC: exynos5420: Gate CLKM to when reading PHY_CON13
when CLKM is running. If we stop CLKM when sampling it the glitches
all go away, so we'll do that as per Samsung suggestion.
We also check the "is it locked" bits of PHY_CON13 and loop until they
show the the value sampled actually represents a locked value. It
doesn't appear that the glitching and "is it locked" are related, but
it seems wise to wait until the PHY tells us the value is good before
we use it. In practice we will not loop more than a couple times (and
usually won't loop at all).
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Mon, 26 May 2014 13:48:06 +0000 (19:18 +0530)]
Exynos5420: Remove code for enabling read leveling
This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Mark Rutland [Wed, 21 May 2014 13:29:23 +0000 (14:29 +0100)]
arm64: zero cntvoff_el2
Currently cntvoff_el2 is initialised with an arbitrary bag of bits
derived from the initial value of cnthctl_el2 on the current CPU. This is
somewhat odd and problematic as some of these bits are UNKNOWN at reset
and may differ across CPUs (which may cause an OS at EL1 to observe time
going backwards across CPUs).
This patch instead initialises cntvoff_el2 with xzr, giving the register
a consistent value of zero on all CPUs.
Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Tom Rini <trini@ti.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
Tom Rini [Thu, 5 Jun 2014 15:15:30 +0000 (11:15 -0400)]
arm:am43xx: Add TPS65218 support to scale voltages up
This family is supported by the TPS65218 PMIC. Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).
Lokesh Vutla [Mon, 2 Jun 2014 05:19:03 +0000 (10:49 +0530)]
ARM: AM43xx: Fix UART clocks enabling
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Lokesh Vutla [Mon, 2 Jun 2014 05:15:38 +0000 (10:45 +0530)]
ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS
loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.
Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Jeroen Hofstee [Sat, 31 May 2014 15:08:30 +0000 (17:08 +0200)]
tam3517: fix NAND detection
commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"
Murali Karicheri [Thu, 29 May 2014 15:57:12 +0000 (18:57 +0300)]
keystone: init: enable UART1 to be able use it from kernel
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Tom Rini [Wed, 21 May 2014 16:57:22 +0000 (12:57 -0400)]
arm:am33xx: Rework s_init and add board_early_init_f
With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared. When SPL booting, this is handled by setting gd
to point to SRAM in s_init. However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.
Tom Rini [Wed, 21 May 2014 16:57:21 +0000 (12:57 -0400)]
arm:am33xx: Make dram_init call sdram_init() in some contexts
We have two contexts for booting these platforms. One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads. The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.
In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus). In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.
Sourav Poddar [Mon, 19 May 2014 20:53:37 +0000 (16:53 -0400)]
am43xx_evm: Add qspiboot target
The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.
Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
pekon gupta [Mon, 2 Jun 2014 11:44:42 +0000 (17:14 +0530)]
mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16_ECC to omap_gpmc driver.
*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
pekon gupta [Mon, 5 May 2014 19:16:20 +0000 (00:46 +0530)]
omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.
pekon gupta [Mon, 5 May 2014 19:16:19 +0000 (00:46 +0530)]
mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.
Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.
This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.
David Mosberger [Mon, 5 May 2014 19:16:18 +0000 (00:46 +0530)]
mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
So porting following commit from linux kernel
commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
Author: David Mosberger <davidm@egauge.net> (preserving authorship)
mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
Brian Norris [Mon, 5 May 2014 19:16:17 +0000 (00:46 +0530)]
mtd: nand: force NAND_CMD_READID onto 8-bit bus
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.
commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults.
Brian Norris [Mon, 5 May 2014 19:16:16 +0000 (00:46 +0530)]
mtd: nand: don't use read_buf for 8-bit ONFI transfers
Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author: Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers
Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:
mtd: nand: omap: fix error-codes returned from omap-elm driver
This patch
omap-elm.c: replaces -ve integer value returned during errorneous condition,
with proper error-codes.
omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
omap-elm driver to upper layers
Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes
Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'
This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
- remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
- remove nand_bch_priv.mode: <unused>
Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
mtd: nand: omap_elm: use macros for register definitions
This patch adds macros for following parameters of ELM Hardware engine
- ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
- ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme
Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'
Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
Stephen Warren [Thu, 29 May 2014 21:29:40 +0000 (15:29 -0600)]
ARM: tegra: enable USB device mode and UMS on some boards
For each of Jetson TK1, Venice2, and Beaver:
- Enable the first USB controller in DT, and describe its configuration.
- Enable USB device/gadget support. This allows the user to type e.g.
"ums 0 mmc 0" at the command-line to cause U-Boot to act a USB device
implementing the USB Mass Storage protocol, and expose MMC device 0
that way.
This allows a host PC to mount the Tegra device's MMC, partition it, and
install a filesystem on it.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Doug Anderson [Thu, 29 May 2014 16:10:54 +0000 (21:40 +0530)]
Exynos: Make sure ps_hold gets set in the SPL
Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Simon Glass [Tue, 20 May 2014 12:01:43 +0000 (06:01 -0600)]
initcall: Improve debugging support
Add the ability to display the code offset of an initcall even after it
is relocated. This makes it much easier to relate initcalls back to the
U-Boot System.map file.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Simon Glass [Tue, 20 May 2014 12:01:40 +0000 (06:01 -0600)]
exynos: Enable PSHOLD in SPL
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.
Add a call in SPL to enable PSHOLD.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Aaron Durbin [Tue, 20 May 2014 12:01:39 +0000 (06:01 -0600)]
exynos5: support tps65090 pmic
The TSP65090 is a PMIC on some exynos5 boards. The init function is
called for the TPS65090 pmic. If that device is not a part of the device
tree (returns -ENODEV) then continue. Otherwise return a failure.
Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Aaron Durbin [Tue, 20 May 2014 12:01:38 +0000 (06:01 -0600)]
power: Explicitly select pmic device's bus
The current pmic i2c code assumes the current i2c bus is
the same as the pmic device's bus. There is nothing ensuring
that to be true. Therefore, select the proper bus before performing
a transaction.
Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Wai-Hong Tam [Tue, 20 May 2014 12:01:36 +0000 (06:01 -0600)]
power: Add support for TPS65090 PMU chip.
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:
- fet enable/disable/querying
- getting and setting of charge state
Even though it is connected to the pmic infrastructure it does
not hook into the pmic charging charging infrastructure.
The device tree binding is from Linux, but only a small subset of
functionality is supported.
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andreas Bießmann [Mon, 19 May 2014 12:23:39 +0000 (14:23 +0200)]
mkimage: add atmelimage
The new atmelimage converts a machine code BLOB to bootable ROM image. Atmel
ROM has no sophisticated image format, it only checks the first 7 ARM vectors.
The vectors can contain valid B or LDR opcodes, the 6'th vector contains the
image size to load.
Additionally the PMECC header can be written by the atmelimage target. The
parameters must be given via the -n switch as a coma separated list. For
example:
A provided image can be checked for correct header setup. It prints out the
PMECC header parameters if it has one and the 6'th interrupt vector content.
Bo Shen [Thu, 24 Apr 2014 03:42:16 +0000 (11:42 +0800)]
ARM: atmel: at91sam9x5ek: convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following
warning on boot:
"Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed."
Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Thu, 24 Apr 2014 03:42:15 +0000 (11:42 +0800)]
ARM: atmel: at91sam9m10g45ek: convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following
warning on boot:
"Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed."
Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Thu, 24 Apr 2014 03:42:14 +0000 (11:42 +0800)]
ARM: atmel: sama5d3_xplained: convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following
warning on boot:
"Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed."
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Thu, 24 Apr 2014 03:42:13 +0000 (11:42 +0800)]
ARM: atmel: sama5d3xek: convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following
warning on boot:
"Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed."
Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Wed, 19 Mar 2014 06:48:44 +0000 (14:48 +0800)]
ARM: atmel: switch to main crystal osc for SPL boot
If without switch to main crystal oscillator, the sama5d3 SoC will
use internal on chip RC oscillator.
In order to get better accuracy, switch to main crystal oscillator.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Ian Campbell [Wed, 14 May 2014 18:30:29 +0000 (19:30 +0100)]
net/designware: reorder struct dw_eth_dev to pack more efficiently.
On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
> The {r,t}xbuffs fields also need to be aligned. Previously this was done
> implicitly because they immediately followed the descriptor tables. Make this
> explicit and also move to the head of the struct.
Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....
Ian.
8<------------
>From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
efficiently.
The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.
Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.
The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.
Ian Campbell [Thu, 8 May 2014 21:26:33 +0000 (22:26 +0100)]
net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN
This is required at least on ARM.
When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
Ian Campbell [Thu, 8 May 2014 21:26:32 +0000 (22:26 +0100)]
net/designware: ensure device private data is DMA aligned.
struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0
Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de>
Ian Campbell [Mon, 5 May 2014 10:52:30 +0000 (11:52 +0100)]
sunxi: non-FEL SPL boot support for sun7i
Add support for booting from an MMC card.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
Ian Campbell [Mon, 5 May 2014 13:42:31 +0000 (14:42 +0100)]
sunxi: mmc support
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > + case 1:
> > +#if CONFIG_MMC1_PG
> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?
It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...
> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.
...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.
> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>
Thanks!
8<---------------------------------
>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support
This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Cc: Aaron Maoye <leafy.myeh@allwinnertech.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: Tom Rini <trini@ti.com>
Ian Campbell [Mon, 5 May 2014 10:52:27 +0000 (11:52 +0100)]
sunxi: add support for Cubietruck booting in FEL mode
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Reviewed-by: Marek Vasut <marex@denx.de>
Ian Campbell [Mon, 5 May 2014 10:52:26 +0000 (11:52 +0100)]
sunxi: add sun7i cpu, board and start of day support
This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.
Signed-off-by: Adam Sampson <ats@offog.org> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luc Verhaegen <libv@skynet.be> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Patrick Wood <patrickhwood@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
Ian Campbell [Mon, 5 May 2014 10:52:25 +0000 (11:52 +0100)]
sunxi: add sun7i dram setup support
This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
Ian Campbell [Mon, 5 May 2014 10:52:24 +0000 (11:52 +0100)]
sunxi: add sun7i pinmux and gpio support
This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
Ian Campbell [Mon, 5 May 2014 10:52:23 +0000 (11:52 +0100)]
sunxi: add sun7i clocks and timer support.
This patch adds the basic clocks and timer support for the Allwinner A20
(sun7i) processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
Some of the code here is common to multiple sunxi subarchtectures, hence files
are named sun4i which is the earliest similar variant.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
Stefan Agner [Wed, 23 Apr 2014 16:17:51 +0000 (18:17 +0200)]
arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
Michael Walle [Tue, 1 Apr 2014 18:09:14 +0000 (20:09 +0200)]
lsxl: rework boot scripts
Move addresses for kernel, ramdisk and fdt blob to own variables. Add dtb
blob loading to all existing boot scripts, dtb filenames were taken from
vanilla kernel. Introduce new boot script bootcmd_legacy, which only loads
a kernel and a ramdisk. Make this the default boot script. This should also
restore the behaviour of the original bootloader.
Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Michael Walle <michael@walle.cc>
projects / u-boot / log