arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263)
Add support for USB-A9263 board manufactured by Calao Systems
(http://www.calao-systems.com/).
Code is based on old U-Boot sources (2010.09) released by Calao.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Mon, 2 Dec 2013 06:47:23 +0000 (07:47 +0100)]
arm, at91: add siemens corvus board
enable support for the siemens AT91SAM9G20 based board corvus.
Signed-off-by: Boris Schmidt <boris.schmidt@siemens.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Mon, 2 Dec 2013 06:47:22 +0000 (07:47 +0100)]
arm, at91: add Siemens board taurus and axm
enable support for the siemens AT91SAM9G20 based boards taurus
and axm.
Signed-off-by: Roger Meier <r.meier@siemens.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Albert ARIBAUD [Thu, 7 Nov 2013 13:21:46 +0000 (14:21 +0100)]
arm: keep all sections in ELF file
Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Masahiro Yamada [Mon, 7 Oct 2013 02:46:56 +0000 (11:46 +0900)]
ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.
This commit moves ".algin 5" directive to the correct place.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
Roger Quadros [Mon, 2 Dec 2013 13:47:43 +0000 (15:47 +0200)]
usb: ehci-omap: Reset the USB Host OMAP module
In commit bb1f327 we removed the UHH reset to fix NFS root (over usb
ethernet) problems with Beagleboard (3530 ES1.0). However, this
seems to cause USB detection problems for Pandaboard, about (3/8).
On further investigation, it seems that doing the UHH reset is not
the cause of the original Beagleboard problem, but in the way the reset
was done.
This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based
on the UHH_REVISION register. This should fix the Beagleboard NFS
problem as well as the Pandaboard USB detection problem.
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Roger Quadros <rogerq@ti.com>
arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.
Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Minkyu Kang [Fri, 6 Dec 2013 10:04:03 +0000 (19:04 +0900)]
arm: exynos: adds ifdef for spi boot
This patch fix following errors and warnings
spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Vladimir Koutny [Thu, 28 Nov 2013 09:38:40 +0000 (10:38 +0100)]
am335x: cpsw: optimize cpsw_recv to increase network performance
In 48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.
Signed-off-by: Vladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
Lokesh Vutla [Thu, 14 Nov 2013 06:01:51 +0000 (11:31 +0530)]
ARM: OMAP5+: Remove unnecessary EFUSE settings
Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.
Roger Quadros [Mon, 11 Nov 2013 14:56:38 +0000 (16:56 +0200)]
ahci: Fix cache align error messages
Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.
scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818
CC: Aneesh V <aneesh@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
SRICHARAN R [Fri, 8 Nov 2013 12:10:38 +0000 (17:40 +0530)]
ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039
When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
SRICHARAN R [Fri, 8 Nov 2013 12:10:37 +0000 (17:40 +0530)]
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Tom Rini [Thu, 7 Nov 2013 16:42:57 +0000 (11:42 -0500)]
am33xx: Stop modifying certain EMIF4D registers
Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified. This has been tested
on AM335x GP EVM and Beaglebone White.
[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
Oleg Kosheliev [Tue, 8 Oct 2013 12:49:55 +0000 (15:49 +0300)]
ARMV7: OMAP4: Add struct for twl603x data
The data struct is used to support different
PMIC chip types. It contains the chip type and
the data (e.g. registers addresses, adc multiplier)
which is different for twl6030 and twl6032.
Replaced some hardcoded values with the
structure vars.
Based on Balaji T K <balajitk@ti.com> patches for TI u-boot.
Lars Poeschel [Tue, 19 Nov 2013 10:22:18 +0000 (11:22 +0100)]
pcm051: Support for revision 3
Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
the board. The difference for u-boot is that is has other DDR3 RAM on it:
1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
2. Both configurations are 512 MiB.
Configure your u-boot build with pcm051_rev3 for the new RAM and
pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
pcm051_rev1 also.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Chin Liang See [Mon, 2 Dec 2013 18:01:39 +0000 (12:01 -0600)]
socfpga: Adding Freeze Controller driver
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Piotr Wilczek [Wed, 27 Nov 2013 10:11:02 +0000 (11:11 +0100)]
board: trats2: update Tizen partition definitions
This patch updates Tizen partions layout.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek [Wed, 27 Nov 2013 10:11:01 +0000 (11:11 +0100)]
board: trats2: fix access to samsung registers
This patch use 'samsung_get_base' common functions to access registers.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek [Wed, 27 Nov 2013 10:11:00 +0000 (11:11 +0100)]
board: trats2: fix environmental variables
In this patch variable names are used instead of hardcoded names
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek [Wed, 27 Nov 2013 10:10:59 +0000 (11:10 +0100)]
board: trats2: remove unused defines from config file
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch implements a custom spi_copy funtion to copy u-boot from SF
to RAM. This is faster then iROM spi_copy funtion as this runs spi at
50Mhz and also in WORD mode of operation.
Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arm: kzm9g: Fix undefined reference to `__aeabi_uldivmod' error
The kzm9g board fails in building with -march=armv7-a.
This fixs this problem by converting to do_div().
-----
USE_PRIVATE_LIBGCC=yes ./MAKEALL kzm9g
...
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_us':
arch/arm/cpu/armv7/rmobile/timer.c:41: undefined reference to `__aeabi_uldivmod'
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_ms':
arch/arm/cpu/armv7/rmobile/timer.c:47: undefined reference to `__aeabi_uldivmod'
-----
Piotr Wilczek [Tue, 12 Nov 2013 14:22:46 +0000 (15:22 +0100)]
trats2: enable dfu and thor protocol for Tizen download
Trats2 config is updated to support DFU mode.
Malloc pool must be increased for DFU buffer allocation.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek [Thu, 21 Nov 2013 14:46:44 +0000 (15:46 +0100)]
driver:usb:s3c_udc: add support for Exynos4x12
This patch add new defines for usb phy for Exynos4x12.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Bo Shen [Wed, 20 Nov 2013 03:17:16 +0000 (11:17 +0800)]
arm: atmel: sam9m10g45ek: let CONFIG_SYS_NO_FLASH at proper position
In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide
whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, if the
CONFIG_SYS_NO_FLASH defined later than include/config_cmd_default.h,
These two commands will be included always.
So move CONFIG_SYS_NO_FLASH definition to proper position.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Luka Perkov [Mon, 4 Nov 2013 01:12:00 +0000 (02:12 +0100)]
config: arm: exynos5250: remove duplicate defines
The SPI section is already defined in this file (lines 268-288) so we can
remove the duplicate definitions. While at it, also fix one tiny whitespace
typo.
Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Paul Burton [Tue, 26 Nov 2013 17:45:27 +0000 (17:45 +0000)]
malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.
Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:26 +0000 (17:45 +0000)]
malta: correct UART baudrate
CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud
rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in
a UART at 115200 baud, thus the x16 clock rate is 115200 * 16.
Previously the divider was left at 0 which led to a rate of 38400 baud
regardless of CONFIG_BAUDRATE or the baudrate environment variable.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:25 +0000 (17:45 +0000)]
mips: don't hardcode Malta env baudrate
The baudrate passed to Linux in the environment was hardcoded at 38400.
Instead pass the correct baudrate from global data, allowing Linux to
correctly inherit the baudrate used by U-boot when console setup is not
explicitly specified.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:12 +0000 (17:39 +0800)]
t2080qds/ramboot: enable PBL tool for t2080qds
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:11 +0000 (17:39 +0800)]
powerpc/t2080qds: add support for t2080qds board
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080QDS feature overview
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/SDHC/SDXC/eMMC Card
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: removed Makefile blank line at EOF,
fix conflicts with moving DDR driver] Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:10 +0000 (17:39 +0800)]
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
York Sun [Tue, 22 Oct 2013 19:39:02 +0000 (12:39 -0700)]
Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
York Sun [Mon, 3 Jun 2013 19:39:06 +0000 (12:39 -0700)]
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
projects / u-boot / log