Igor Grinberg [Tue, 21 Oct 2014 13:39:47 +0000 (16:39 +0300)]
omap3: cm-t35: remove enable_gpmc_cs_config()
The gpmc_init() function already calls enable_gpmc_cs_config() for chip
select 0. Although the bus width is configured for 16 bit, it gets
reconfigured correctly in the omap_gpmc driver later.
Remove the enable_gpmc_cs_config() function call and the associated
gpmc_nand_config[] array.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tom Rini [Wed, 8 Oct 2014 21:10:27 +0000 (17:10 -0400)]
am335x_boneblack: Only modify NAND/NOR/MMC1 pinmux on BBB in boneblack builds.
In the case of Beaglebone Black we only want to set the NAND or NOR cape
pinmux when the config has been specifically modified by the user for
this non-default case. Make the default be to set the MMC1 (eMMC)
pinmux. We don't need similar changes for Beaglebone White as there is
nothing on MMC1 by default there.
Felipe Balbi [Tue, 23 Sep 2014 15:44:18 +0000 (10:44 -0500)]
arm: am43xx: switch over to CONFIG_ENV_IS_IN_FAT
By using CONFIG_ENV_IS_IN_FAT it's far easier
to have a private, minimal environment for e.g.
booting off of network or mounting rootfs on NFS
without having to modify the configuration header.
omap3: overo: Separate module and expansion board MUX configuration
Separate overo module and expansion board MUX configuration. This allows
an foreign expansion board to use the boot loader without any adaption.
It only needs to save the expansion name in the EEPROM to load a
specific device tree.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Hao Zhang [Wed, 22 Oct 2014 14:47:59 +0000 (17:47 +0300)]
ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr
Add ddr3 commands:
test <start_addr in hex> <end_addr in hex> - test DDR from start\n
address to end address\n
ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n
compare DDR data of (size) bytes from start address to end
address\n
ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n
in DDR data at <addr>, the command will read a 32-bit data\n
from <addr>, and write (data ^ bit_err) back to <addr>\n
Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used
for ddr3 commands and for now it's not needed any more.
Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Vitaly Andrianov [Wed, 22 Oct 2014 14:47:58 +0000 (17:47 +0300)]
keystone2: ecc: add ddr3 error detection and correction support
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Khoronzhuk, Ivan [Wed, 22 Oct 2014 14:47:56 +0000 (17:47 +0300)]
dma: ti-edma3: introduce edma3 driver
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.
Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
accessible via the EDMA3 controller
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan [Fri, 17 Oct 2014 18:01:16 +0000 (21:01 +0300)]
ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan [Fri, 17 Oct 2014 17:44:34 +0000 (20:44 +0300)]
net: keystone_net: register MDIO bus
Currently MDIO framework is not used to configure Ethernet PHY.
As result some of already implemented functions are duplicated.
So register MDIO bus in order to use it. On that stage it's just
registered, it'll be used as we start to use PHY framework.
Use mdio bus read/write/reset functions in the driver.
Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Hao Zhang [Wed, 22 Oct 2014 14:18:23 +0000 (17:18 +0300)]
soc: keystone_serdes: generalize to be used by other sub systems
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan [Wed, 22 Oct 2014 14:18:21 +0000 (17:18 +0300)]
soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan [Mon, 29 Sep 2014 19:17:24 +0000 (22:17 +0300)]
net: keystone_net: remove redundant code from keystone_net.c
Remove unused tx_send_loop variable.
Removes duplicated get_link_status() call from the
keystone2_eth_send_packet().
The emac_gigabit_enable() is called at opening Ethernet and there is no
need to enable it on sending each packet. So remove that call
from keystone2_eth_send_packet() as well.
The calling of power/clock up functions are mostly the responsibility
of SoC/board code, so move these functions to appropriate place.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
With MAC_PHY sgmii configuration, u-boot checks PHY link status before
sending each packet. Increasing MDIO frequency increases overall tftp
speed. We set it to maximum 2.5MHz.
Khoronzhuk, Ivan [Mon, 29 Sep 2014 19:17:22 +0000 (22:17 +0300)]
net: keystone_net: move header file from arch to ti-common
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.
Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan [Mon, 29 Sep 2014 19:17:21 +0000 (22:17 +0300)]
net: keystone_net: add support for NETCP v1.5
Currently the network driver is used only by k2hk evm board.
The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e
contain NETCP v1.5. So driver should be able to work with such kind
of NETCP. This commit adds this opportunity. The main difference in
masks and some registers, the logic is the same, so only definitions
should be changed. To differentiate between versions add KS2_NETCP_V1_0
and KS2_NETCP_V1_5. Also remove unused and no more needed defines.
The port number is specific for each board so move this parameter to
configuration.
net: keystone_net: remove SoC specific emac_regs structure
This patch removes K2HK SOC specifc emac_regs structure, it uses
soc specific register offset to keep the network driver common across
all the Keystone II EVMs.
The usage description of commands refers to headers of sources,
that is not correct. This patch is intended to fix it.
Also generalize code in order to reduce SoC dependent #ifdefs.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Add support of usb xhci. xHCI controls all USB speeds of the Host
mode, that is, the SS through the SS PHY, as well as the HS, FS, and
LS through the USB2 PHY. xHCI replaces and supersedes all previous
host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not
backwards compatible with any of them. The USB3SS’s USB Controller is
fully compliant with xHC.
The keystone_nav driver is general driver intended to be used for
working with queue manager and pktdma for different IPs like NETCP,
AIF, FFTC, etc. So the it's API shouldn't be named like it works only
with one of them, it should be general names. The names with prefix
like netcp_* rather do for drivers/net/keystone_net.c driver. So it's
good to generalize this driver to be used for different IP's and
delete confusion with real NETCP driver.
The current netcp_* functions of keystone navigator can be used for
other settings of pktdma, not only for NETCP. The API of this driver
is used by the keystone_net driver to work with NETCP, so net driver
also should be corrected. For convenience collect pkdma
configurations in drivers/dma/keystone_nav_cfg.c.
Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
dma: keystone_nav: move keystone_nav driver to driver/dma/
The keystone_nav is used by drivers/net/keystone_net.c driver to
send and receive packets, but currently it's placed at keystone
arch sources. So it should be in the drivers directory also.
It's separate driver that can be used for sending and receiving
pktdma packets by others drivers also.
This patch just move this driver to appropriate directory and
doesn't add any functional changes.
Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
keystone2: keystone_nav: don't use hard addresses in netcp_pktdma
Use definitions in netcp_pktdma instead direct addresses.
The definitions can be set specifically for SoC, so there
is no reason to check SoC type while initialization.
Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Simon Glass [Mon, 22 Sep 2014 23:30:57 +0000 (17:30 -0600)]
dm: serial: Tidy up the pl01x driver
Adjust the driver so that leaf functions take a pointer to the serial port
register base. Put all the global configuration in the init function, and
use the same settings from then on.
This makes it much easier to move to driver model without duplicating the
code, since with driver model we use platform data rather than global
settings.
The driver is compiled with either the CONFIG_PL010_SERIAL or
CONFIG_PL011_SERIAL option and this determines the uart type. With driver
model this needs to come in from platform data, so create a new
CONFIG_PL01X_SERIAL config which brings in the driver, and adjust the
driver to support both peripheral variants.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Simon Glass [Thu, 2 Oct 2014 01:57:26 +0000 (19:57 -0600)]
dm: imx: gpio: Support driver model in MXC gpio driver
Add driver model support with this driver. In this case the platform data
is in the driver. It would be better to put this into an SOC-specific file,
but this is best attempted when more boards are moved over to use driver
model.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Nikita Kiryanov [Thu, 2 Oct 2014 14:17:24 +0000 (17:17 +0300)]
arm: mx6: cm_fx6: use gpio request
Use gpio_request for all the gpios that are utilized by various
subsystems in cm-fx6, and refactor the relevant init functions
so that all gpios are requested during board_init(), not during
subsystem init, thus avoiding the need to manage gpio ownership
each time a subsystem is initialized.
The new division of labor is:
During board_init() muxes are setup and gpios are requested.
During subsystem init gpios are toggled.
Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Simon Glass [Thu, 2 Oct 2014 01:57:20 +0000 (19:57 -0600)]
dm: linker_lists: Add a way to declare multiple objects
The existing ll_entry_declare() permits a single element of the list to
be added to a linker list. Sometimes we want to add several objects at
once. To avoid lots of messy declarations, add a macro to support this.
Simon Glass [Tue, 14 Oct 2014 05:42:11 +0000 (23:42 -0600)]
dm: sf: Add tests for SPI flash
Add a simple test for SPI that uses SPI flash. It operates by creating a
SPI flash file and using the 'sf test' command to test that all
operations work correctly.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:42:07 +0000 (23:42 -0600)]
dm: Convert spi_flash_probe() and 'sf probe' to use driver model
We want the SPI flash probing feature to operate as a standard driver.
Add a driver for the basic probing feature used by most boards. This
will be activated by device_probe() as with any other driver.
The 'sf probe' command currently keeps track of the SPI slave that it
last used. This doesn't work with driver model, since some other driver
or system may have probed the device and have access to it too. On the
other hand, if we try to probe a device twice the second probe is a nop
with driver model.
Fix this by searching for the matching device, removing it, and then
probing it again. This should work as expected regardless of other device
activity.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:42:06 +0000 (23:42 -0600)]
dm: sf: Add a uclass for SPI flash
Add a driver model uclass for SPI flash which supports the common
operations (read, write, erase). Since we must keep support for the
non-dm interface, some modification of the spi_flash header is required.
CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:41:59 +0000 (23:41 -0600)]
dm: spi: Remove SPI_INIT feature
This feature provides for init of a single SPI port for the soft SPI
feature. It is not really compatible with driver model since it assumes a
single SPI port. Also, inserting SPI init into the driver by means of
a #define is not very nice.
This feature is not used by any active boards, so let's remove it.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:41:54 +0000 (23:41 -0600)]
dm: Remove spi_init() from board_r.c when using driver model
Driver model does its own init, so we don't need this.
There is still a call in board_f.c but it is only enabled by CONFIG_HARD_SPI.
It is easy enough to disable that option when converting boards which use
it to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:41:53 +0000 (23:41 -0600)]
dm: sandbox: Add a SPI emulation uclass
U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.
Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an emulation, and it should be
possible to add more than one emulation - not just SPI flash.
Add a SPI emulation uclass so that other emulations can be plugged in to
support different types of emulated devices on difference buses/chip
selects.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Tue, 14 Oct 2014 05:41:52 +0000 (23:41 -0600)]
dm: spi: Add a uclass for SPI
Add a uclass which provides access to SPI buses and includes operations
required by SPI.
For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are not available with
driver model.
Boards must define CONFIG_DM_SPI to use driver model for SPI.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
(Discussed some follow-up comments which will address in future add-ons)
Simon Glass [Tue, 14 Oct 2014 05:41:50 +0000 (23:41 -0600)]
dm: core: Allow parents to pass data to children during probe
Buses sometimes want to pass data to their children when they are probed.
For example, a SPI bus may want to tell the slave device about the chip
select it is connected to.
Add a new function to permit the parent data to be supplied to the child.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
projects / u-boot / log