Jon Loeliger [Thu, 14 Sep 2006 13:40:36 +0000 (08:40 -0500)]
Handle 86xx SVR values according to the new Reference Manual.
Both 8641 and 8641D have SVR == 0x8090, and are distinguished
by the byte in bits 16-23 instead.
Thanks to Jason Jin for noticing.
Haiying Wang [Wed, 12 Jul 2006 14:48:05 +0000 (10:48 -0400)]
Add support for reading and writing mac addresses to or from ID EEPROM.
Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.
U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).
If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
When tftp a non-exist file from the tftp server, u-boot will check
the link of all eth port. The original file will return wrong link
state on the no link ports.
signed-off-by: Jason Jin <Jason.Jin@freescale.com>
During the pci scan process, Some devices return bar_reponse with the
highest bytes 0, such as the pci bridge in uli1575 return bar_response
with 0xffffff, So the bar_size should be manually set under 64K.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Jon Loeliger [Wed, 31 May 2006 17:44:44 +0000 (12:44 -0500)]
White space cleanup.
Some 80-column cleanups.
Convert printf() to puts() where possible.
Use #include "spd_sdram.h" as needed.
Enhanced reset command usage message a bit.
Haiying Wang [Tue, 30 May 2006 14:10:32 +0000 (09:10 -0500)]
Improve "reset" command's interaction with watchdog.
"reset altbank" will reset another bank WITHOUT watch dog timer enabled
"reset altbank wd" will reset another bank WITH watch dog enabled
"diswd" will disable watch dog after u-boot boots up successfully
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Jon Loeliger [Tue, 9 May 2006 13:23:49 +0000 (08:23 -0500)]
Get MPC8641HPCN flash images working.
Enable the CFI driver.
Remove bogus LAWBAR7 cruft.
Use correct TEXT_BASE, Fixup load script.
Enable SPD EEPROM during DDR setup.
Use generic RFC 1918 IP addresses by default.
Wolfgang Denk [Tue, 18 Apr 2006 09:05:03 +0000 (11:05 +0200)]
MPC5200: enable snooping of DMA transactions on XLB even if no PCI
is configured; othrwise DMA accesses aren't cache coherent which
causes for example USB to fail.
* Fix dbau1x00 Board
- Fix dbau1x00 boards broken by dbau1550 patch
PLL:s were not set for boards other than 1550.
Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
Default boot is now bootp for cards other than 1550.
Patch by Thomas Lange Aug 10 2005
- fix some compiler/parser error, if using m68k tool chain
- optical fix for protect on/off all messages, if using more
then one bank
Patch by Jens Scharsig, 28 July 2005
Remove dependencies between DoC code and old legacy NAND driver.
Necessary defines and data structures were copied to DoC specific files
so that legacy NAND code could be entirely removed from u-boot tree
in the near future.
Stefan Roese [Sat, 1 Apr 2006 11:41:03 +0000 (13:41 +0200)]
* Changes/fixes for drivers/cfi_flash.c:
- Add Intel legacy lock/unlock support to common CFI driver
On some Intel flash's (e.g. Intel J3) legacy unlocking is
supported, meaning that unlocking of one sector will unlock
all sectors of this bank. Using this feature, unlocking
of all sectors upon startup (via env var "unlock=yes") will
get much faster.
- Fixed problem with multiple reads of envronment variable
"unlock" as pointed out by Reinhard Arlt & Anders Larsen.
- Removed unwanted linefeeds from "protect" command when
CFG_FLASH_PROTECTION is enabled.
- Changed p3p400 board to use CFG_FLASH_PROTECTION
Patch by Stefan Roese, 01 Apr 2006
* Changes/fixes for drivers/cfi_flash.c:
- Correctly handle the cases where CFG_HZ != 1000 (several
XScale-based boards)
- Fix the timeout calculation of buffered writes (off by a
factor of 1000)
Patch by Anders Larsen, 31 Mar 2006
Stefan Roese [Fri, 17 Mar 2006 09:28:24 +0000 (10:28 +0100)]
Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
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