sunxi: Fix gmac not working reliable on the Bananapi

In order for the gmac nic to work reliable on the Bananapi, we need to set
bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register
(0x01c20164) to 3.

Without this about 9 out of 10 ethernet packets get lost, with this setting
there is no packet loss.

So far setting these bits is only necessary on the Bananapi, so this commit
solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we
need to do something similar for other boards, we can create a specific
CONFIG_FOO option for this then.

Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Zoltan HERPAI <wigyori@openwrt.org>
Tested-by: Tony Zhang <tony.zhang@lemaker.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Merge branch 'master' of git://git.denx.de/u-boot-arm

vf610twr: Tune DDR initialization settings

Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.

Changed register settings to comply with JEDEC required values.

Changed timing parameters because they included full clock
periods that were doing nothing.

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>

Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'

Prepare v2014.10-rc3

Signed-off-by: Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-usb

Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga

Fix a trivial conflict in dw_mmc.c after talking with Marek.

Conflicts:
drivers/mmc/dw_mmc.c

Signed-off-by: Tom Rini <trini@ti.com>

usb: gadget: fastboot: terminate commands with NULL

Without NULL termination, various commands will read past the
end of input. In particular, this was noticed with error()
calls in cb_getvar and simple_strtoul() in cb_download.

Since the download callback happens elsewhere, the 4k buffer
should always be sufficient to handle command arguments.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

usb: musb-new: core: set MUSB_POWER_HSENAB in MUSB_POWER for host mode

This bit allows the MUSB controller to negotiate for high-speed mode when
the device is reset by the hub. If unset, Babble errors occur with
high-speed mass storage devices right after the first packet. This condition
is not caught by the interrupt handles in U-Boot, so no recovery is done,
and the USB communication is stuck.

To fix this, set the bit unconditionally, not only for
CONFIG_USB_GADGET_DUALSPEED but also for host-only modes.

Signed-off-by: Daniel Mack <zonque@gmail.com>

arm: socfpga: Use CMD_FS_GENERIC

Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Split SoCFPGA configuration

Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.

This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Clean up SoCFPGA configuration

Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.

Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: Add command to control HPS-FPGA bridges

Add command to enable and disable the bridges between HPS and FPGA.

This patch does have a checkpatch issue with the assembler portion,
checkpatch correctly complains that there should be no whitespace
before quoted newline. I do not agree that fixing this specific
checkpatch issue will improve the readability, thus this one is not
addressed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>

arm: socfpga: Move cache_enable to CPU code

Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot

Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.

Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Enable DWMMC for SOCFPGA

Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: nic301: Add NIC-301 configuration code

Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: pl310: Map SDRAM to 0x0

Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the "remap" register of NIC-301 and sets the
required 'mpuzero' bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: nic301: Add NIC-301 GPV register file

Add register definition for the NIC-301 used on SoCFPGA.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: scu: Add SCU register file

Add the Snoop Control Unit register definition file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: cache: Enable PL310 L2 cache

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: cache: Enable D-Cache

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: cache: Define cacheline size

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: sysmgr: Add FPGA bits into system manager

Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: reset: Add function to reset FPGA bridges

Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: fpga: Add SoCFPGA FPGA programming interface

Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.

arm: socfpga: board: Align checkboard() output

Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: board: Correctly set ATAG position

The bi_boot_params must point to offset 0x100 in DRAM. Make it so.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: misc: Align print_cpuinfo() output

Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: misc: Add SD controller init

Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: misc: Add proper ethernet initialization

Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.

We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: reset: Add EMAC reset functions

Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: timer: Pull the timer reload value from config file

The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: mmc: Pick the clock from clock manager

Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.

Also fix calloc() misuse.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>

arm: socfpga: clock: Sync with reference code

Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Clean up bit definitions

Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Trim down code duplication

Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Add code to read clock configuration

Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
    rocketboards codebase (thanks Dinh for pointing this out)

arm: socfpga: clock: Add missing stubs into board file

Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Drop nonsense inlining from clock manager code

The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Implant order into bit definitions

The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: sysmgr: Clean up system manager

Clean up the system manager register definition and add the missing
register definitions in place.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Add watchdog disable for socfpga

This adds watchdog disable. It is neccessary for running Linux kernel.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
    Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)

arm: socfpga: Clean up base address file

Sort the list of functional block addresses and fix indentation.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>

arm: socfpga: Complete the list of base addresses

Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>

Merge branches 'topic/drivers/fpga-20141006', 'topic/drivers/mmc-20141006', 'topic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD

arm: cache: Add support for write-allocate D-Cache

Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

tools: socfpga: Add socfpga preloader signing to mkimage

Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.

This change automatically creates an appropriately signed preloader
from an SPL image.

The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.

Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.

Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.

Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
V2: - Zap unused constant
    - Explicitly print an error message in case of error
    - Rework the hdr_checksum() function to take the *header directly
      instead of a plan buffer pointer

net: dwc: Make the cache handling less cryptic

Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>

net: dwc: Fix cache alignment issues

Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>

net: phy: Cleanup drivers/net/phy/micrel.c

Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Chin Liang See <clsee@altera.com>

net: Remove unused CONFIG_DW_SEARCH_PHY from configs

Remove this symbol from configs, since it's unused.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Chin Liang See <clsee@altera.com>

mmc: dw_mmc: Fix cache alignment issue

The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.

The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Pavel Machek <pavel@denx.de>

mmc: dw_mmc: cleanups

The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Chin Liang See <clsee@altera.com>

fpga: altera: Turn the switches into table lookup

Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

fpga: altera: Clean up enums in altera.h

Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

fpga: altera: Make altera_validate return normal values

Make the function return either 0 or -EINVAL, that is, normal
expected error codes and success codes instead of true/false
nonsense.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

fpga: altera: Move altera_validate to the top

Move the function to the top of the file to avoid forward declaration.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

fpga: altera: More indentation trimdown

Further improve the indentation in the rest of the file, where
the indentation is initially a bit less brutal. There is no
functional change in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

fpga: altera: Clean up altera_validate function

Boldly go, where no programmer has gone before and just clean up
the indentation mayhem. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

fpga: altera: Clean up the printing and debug

Clean up the printf() statements and get rid of the PRINTF()
macro by replacing it with debug_cond().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

usb: tegra: ULPI regression on tegra20

Trying to enumerate USB devices connected via ULPI to T20 failed as
follows:

USB2:   ULPI integrity check failed

Git bisecting revealed the following commit being at odds:

commit 2d34151f7501ddaa599897f0d89ad576126b03eb
usb: tegra: refactor PHY type selection

Looking at above commit one quickly identifies a copy paste error which
this patch fixes. Happy ULPIing again (;-p).

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>

lsxl: convert to generic board and fix typo

Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo
which accidentally reverted the bootsource to 'hdd' although the default
bootsource should be 'legacy'.

Cc: Tom Rini <trini@ti.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

usb: gadget: fastboot: explicitly set radix of maximum download size

The processing of the max-download-size variable requires a
radix specifier, or the fastboot host tool will interpret
it as an octal number.

See function get_target_sparse_limit() in file fastboot/fastboot.c
in the AOSP:
        https://android.googlesource.com/platform/system/core/+/master

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

usb: gadget: fastboot: add max-download-size variable

Current Android Fastboot seems to use 'max-download-size' instead
of 'downloadsize' variable to indicate the maximum size of sparse
segments.

See function get_target_sparse_limit() in file fastboot/fastboot.c
in the AOSP:
 https://android.googlesource.com/platform/system/core/+/master

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

usb: ci_udc: respect CONFIG_USB_GADGET_DUALSPEED

Force full-speed (12 Mbit/s) operation if CONFIG_USB_GADGET_DUALSPEED
is not defined.

The controller is capable of high-speed (480 Mbit/s) operation,
but some designs may require the use of lower-speed operation.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

usb: gadget: fastboot: improve download progress bar

When download is ongoing, if the actual size of one transfer
is not the same as BYTES_PER_DOT, which will cause the dot
won't print anymore. Then it will let the user thinking it
is stuck, actually it is transfering without dot printed.

So, improve the method to show the progress bar (print dot).

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Marek Vasut <marex@denx.de>

usb: f_mass_storage: set removable flag in do_inquiry based on LUN

Without this flag, tools like Alex Page's USB Image Tool
won't see drives exposed over USB Gadget as removable,
and won't allow access to them.
http://www.alexpage.de/usb-image-tool/

The code was pulled from the main-line kernel:
drivers/usb/gadget/function/f_mass_storage.c

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

arm: am335x: siemens board use in DFU mode fullspeed only

Siemens boards are now using DFU in fullspeed only. For
this CONFIG_USB_GADGET_DUALSPEED is undefined.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Liu Bin <b-liu@ti.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>

usb: dfu: add fullspeed support for DFU

DFU now can use also fullspeed.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Liu Bin <b-liu@ti.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>

usb: dfu: thor: gadget: Remove dead code

This code is not used anymore in the current DFU implementation and
can be safely removed.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>

usb: kbd: Allow "usb reset" to continue when an usb kbd is used

Use the new force parameter to make the stdio_deregister succeed, replacing
stdin with a nulldev, and assume that the usb keyboard will come back after
the reset.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

stdio: Add force parameter to stdio_deregister

In some cases we really want to move forward with a deregister, add a force
parameter to allow this, and replace the dev with a nulldev in this case.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: kbd: Remove check for already being registered

We now always properly deregister the keyboard before calling
drv_usb_kbd_init(), so we can drop the check for already being registered.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: kbd: On a "usb reset" call usb_kbd_deregister() before calling usb_stop()

We need to call usb_kbd_deregister() before calling usb_stop().

usbkbd's stdio_dev->priv points to the usb_device, and usb_kbd_testc
dereferences usb_device->privptr.

usb_stop zeros usb_device, leaving usb_device->privptr NULL, causing
bad things (tm) to happen once control returns to the main loop and
usb_kbd_testc gets called.

Calling usb_kbd_deregister() avoids this. Note that we do not allow
the "usb reset" to continue when the deregister fails. This will be fixed
in a later patch.

For the same reasons always fail "usb stop" if the usb_kbd_deregister() fails,
even in the force path. This can happen when CONFIG_SYS_STDIO_DEREGISTER is
not set.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: kbd: Do not treat -ENODEV as an error for usb_kbd_deregister

ENODEV menas no usb keyboard was registered, threat this as a successful
usb_kbd_deregister.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: kbd: Fix unaligned buffer usage in usb_kbd_setled()

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: ehci: Make periodic_schedules a per controller variable

Periodic schedules tracks how many int_queue-s are active, and decides whether
or not to en/disable the periodic schedule based on this. This is clearly
a per controller thing.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: ehci: poll_int_queue check real qtd, not the overlay

When we first start an int queue, the qh's overlay area is all zeros. This
gets filled by the hc with the actual qtd values as soon as it advances
the queue, but we may call poll_int_queue before then, in which case we
would think the transfer has completed as the hc has not yet copied the
qt_token to the overlay, so the active flag is not set.

This fixes this by checking the actual qtd token, rather then the overlay.
This also fixes a (theoretical) race where we see the completion in the
overlay and free and re-use the qtd before the hc has completed writing back
the overlay to the actual qtd.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: ehci: Add missing cache flush to destroy_int_queue

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

usb: ehci: Properly set hub devnum and portnr with usb-1 hubs in the chain

For full / low speed devices we need to get the devnum and portnr of the tt,
so of the first upstream usb-2 hub, not of the parent device (which may be a
usb-1 hub).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

cfi_flash: don't hide write/erase errors

Partially revert commit 0d01f66d235118 (CFI: cfi_flash write fix for AMD
legacy).

flash_full_status_check() used to skip status register parsing when
flash_status_check() returns OK. This is wrong since flash_status_check()
must return OK for other status bits to be valid.

Cc: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

git-mailrc: add me as a maintainer of UniPhier platform

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

MAINTAINERS: add me as a maintainer of UniPhier platform

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Michal Simek <monstr@monstr.eu>

ARM: UniPhier: add Kconfig and defconfig

This commit allows to build Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

ARM: UniPhier: add UniPhier SoC support code

These are used by Panasonic UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

serial: add UniPhier serial driver

The driver for on-chip UART used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

mtd: denali: add Denali NAND driver for SPL

The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.

This driver requires two CONFIG macros:
 - CONFIG_SPL_NAND_DENALI
     Define to enable this driver.
 - CONFIG_SYS_NAND_BAD_BLOCK_POS
     Specify bad block mark position in the oob space. Typically 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>

mtd: denali: add Denali controller configs to Kconfig

Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081ef (nand/denali: Document CONFIG symbols).

This commit allows users to enable/disable them via Kconfig
with more detailed help docs.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>

dw_mmc: cleanups

dw_mmc driver was responding to errors with debug(). Change that to
prinf so that any errors are immediately obvious. Also adjust english
in comments.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

cmd_mmc: fix bootpart-resize maxarg to 4

sub-command 'bootpart-resize' check for argc == 4,
it will retrun CMD_RET_FAILURE when argc value not matched.

but bootpart-resize's maxarg is 3, which means you never execute
this sub-command successfully.

fix it by change bootpart-resize maxarg to 4.

Signed-off-by: wally.yeh <wally.yeh@atrustcorp.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pierre Aubert <p.aubert@staubli.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

mmc: Fix mmc bus width

After setting the bus width, the extended CSD register is read. Some selected
fields are compared with previously read extended CSD register fields. In this
comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is
previously written under certain circumstances. And then the comparison fails.

Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE
instead of field EXT_CSD_ERASE_GROUP_DEF.

Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

mvebu_mmc: Driver addition

In function mvebu_mmc_write notice command timeout. It is possible that a
command is done, but a timeout occurred.

Enable timeout in set bus function.

Set window registers. Without that I could not use the driver on a Kirkwood
88F6282 SoC.

Set high capacity and 52MHz driver feature.

Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

env_mmc: correct fini partition to match init partition

The code to set the MMC partition uses an weak function to obtain the
correct partition number.  Use that instead of the compile-time default
when deciding whether it needs to switch back.

Fixes: 6e7b7df4df43574 ("env_mmc: support env partition setup in runtime")
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

mmc: restore capacity when switching to partition 0

The capacity and lba for an MMC device with part_num 0 reflects the
whole device.  When mmc_switch_part() successfully switches to a
partition, the capacity is changed to that partition.  As partition 0
does not physically exist, attempts to switch back to the whole device
will indicate an error, but the capacity setting for the whole device
must still be restored to match the partition.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

mmc: fix ERASE_GRP_DEF handling

if we set manually this bit on the eMMC card using mmc_switch(...),
we also have to set it within our (before read) internal structure
'ext_csd'.

Otherwise following checks on this will fail.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

mmc: set correct block size value in bfin sdh driver

Wait data transfer till the data end bit other than the data block end
bit is set.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>

ARM: sheevaplug: add HUSH parser

This patch add HUSH command parser

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
 Changes in v1:
 - add HUSH command parser
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

ARM: sheevaplug: redefine MTDPARTS

This patch redefine MTDPARTS

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
 Changes in v1:
 - redefine MTDPARTS
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

ARM: sheevaplug: add MTD defaults

This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
 Changes in v1:
 - add MTDIDS and MTDPARTS default to sheevaplug
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>