Simon Glass [Wed, 20 Jan 2016 04:32:27 +0000 (21:32 -0700)]
dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:26 +0000 (21:32 -0700)]
dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:25 +0000 (21:32 -0700)]
dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.
As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.
Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:21 +0000 (20:19 -0700)]
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:20 +0000 (20:19 -0700)]
spi: ich: Separate out the read/write trace from normal debugging
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:19 +0000 (20:19 -0700)]
dm: x86: Add a driver for Intel PCH9
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:18 +0000 (20:19 -0700)]
dm: x86: Add a driver for Intel PCH7
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:17 +0000 (20:19 -0700)]
dm: Expand the uclass for Platform Controller Hubs (PCH)
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 22 Jan 2016 02:45:25 +0000 (19:45 -0700)]
rockchip: Update the README
GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.
Simon Glass [Fri, 22 Jan 2016 02:45:19 +0000 (19:45 -0700)]
rockchip: jerry: Enable EDP and HDMI video output
Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.
Simon Glass [Fri, 22 Jan 2016 02:45:08 +0000 (19:45 -0700)]
rockchip: Add a script to parse datasheets
This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.
Simon Glass [Fri, 22 Jan 2016 02:45:05 +0000 (19:45 -0700)]
rockchip: video: Add a video-output driver
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Simon Glass [Fri, 22 Jan 2016 02:45:03 +0000 (19:45 -0700)]
rockchip: video: Add a display driver for rockchip HDMI
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.
Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Simon Glass [Fri, 22 Jan 2016 02:45:00 +0000 (19:45 -0700)]
dm: video: Repurpose the 'displayport' uclass to 'display'
The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.
Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.
Simon Glass [Fri, 22 Jan 2016 02:44:59 +0000 (19:44 -0700)]
video: panel: Add a simple panel driver
Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.
Simon Glass [Fri, 22 Jan 2016 02:44:58 +0000 (19:44 -0700)]
dm: panel: Add a panel uclass
LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.
Simon Glass [Fri, 22 Jan 2016 02:44:56 +0000 (19:44 -0700)]
dm: backlight: Add a backlight uclass
LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.
Simon Glass [Fri, 22 Jan 2016 02:44:51 +0000 (19:44 -0700)]
video: Name consoles by their number
We must use the console name in the 'stdout' variable to select the one
we want. At present the name is formed from the driver name with a suffix
indicating the rotation value.
It seems better to name them sequentially since this can be controlled by
driver order. So adjust the code to use 'vidconsole' for the first,
'vidconsole1' for the second, etc.
Simon Glass [Fri, 22 Jan 2016 02:44:50 +0000 (19:44 -0700)]
gpio: Warn about invalid GPIOs used with the 'gpio' command
At present there is no indication that an invalid GPIO is used except that
the GPIO status is not displayed. Make the error more explicit to avoid
confusion.
Simon Glass [Fri, 22 Jan 2016 02:44:12 +0000 (19:44 -0700)]
rockchip: spi: Remove the explicit pinctrl setting
The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.
Simon Glass [Fri, 22 Jan 2016 02:44:11 +0000 (19:44 -0700)]
rockchip: spi: Correct chip-enable code
At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.
Simon Glass [Fri, 22 Jan 2016 02:44:05 +0000 (19:44 -0700)]
rockchip: clk: Make rkclk_get_clk() SoC-specific
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.
Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.
Simon Glass [Fri, 22 Jan 2016 02:43:59 +0000 (19:43 -0700)]
dm: power: Allow regulators to not implement all operations
Some regulators will not implement any operations (e.g. fixed regulators).
This is not an error, so allow the autoset process to continue when one
of these regulators is found.
Simon Glass [Fri, 22 Jan 2016 02:43:58 +0000 (19:43 -0700)]
dm: power: Tidy up debugging output and return values
The currect PMIC debugging is a little confusing. Adjust it so that it is
clear whether the operation succeeded or failed. Also, avoid creating a new
error return value when a perfectly good one is already available.
Simon Glass [Fri, 22 Jan 2016 02:43:56 +0000 (19:43 -0700)]
dm: pinctrl: Add a way for a GPIO driver to obtain a pin function
GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.
Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.
Simon Glass [Fri, 22 Jan 2016 02:43:55 +0000 (19:43 -0700)]
dm: power: Allow regulators to be omitted from SPL
For some boards the pmic interface is useful but the regulator interface
(which comes with it) is too large. Allow them to be separated such that
SPL can decide which it needs.
Simon Glass [Fri, 22 Jan 2016 02:43:54 +0000 (19:43 -0700)]
spi: Correct device tree usage in spi_flash_decode_fdt()
This function currently searches the entire device tree for a node that
it thinks is relevant. But the node is known and is passed in. Correct the
code and enable it only with driver model, since only driver-model boards
will use it.
This avoids bringing in a large number of strings from fdtdec.
Simon Glass [Fri, 22 Jan 2016 02:43:44 +0000 (19:43 -0700)]
rockchip: spi: Avoid setting the pinctrl twice
If full pinctrl is enabled we don't need to manually set the pinctrl in the
driver. It will happen automatically. Adjust the code to suit - we will
still use manual mode in SPL.
Simon Glass [Fri, 22 Jan 2016 02:43:41 +0000 (19:43 -0700)]
rockchip: clock: Add a function to find a clock by ID
The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.
Simon Glass [Fri, 22 Jan 2016 02:43:38 +0000 (19:43 -0700)]
rockchip: Use a separate clock ID for clocks
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.
Update the clock drivers and the code that uses them.
Simon Glass [Fri, 22 Jan 2016 02:43:26 +0000 (19:43 -0700)]
dm: pinctrl: Add a function to parse PIN_CONFIG flags
Add a function which produces a flags word from a few common PIN_CONFIG
settings. This is useful for simple pinctrl drivers that don't need to worry
about drive strength, etc.