Stefan Roese [Thu, 3 Apr 2008 12:50:34 +0000 (14:50 +0200)]
ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3
This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.
Stefan Roese [Wed, 2 Apr 2008 06:39:33 +0000 (08:39 +0200)]
ppc4xx: Canyonlands: Init SATA/PCIe port correctly
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
correctly configures the SATA/PCIe PHY for SATA usage when this jumper
is installed.
Daniel Hellstrom [Mon, 31 Mar 2008 14:25:00 +0000 (14:25 +0000)]
SPARC: added SMC91111 driver in and out macros for LEON processors.
This patch makes SPARC/LEON processors able to read and write
to the SMC91111 chip using the chip external I/O bus of the memory
controller. This patchs defines the standard in and out macros
expected by the SMC9111 driver.
To access that I/O bus one must set up the memory controller
(MCTRL or FTMCTRL) correctly. It is assumed that the user sets
up this correctly when the other MCTRL parameters are set up. It
can be set up from the board configuration header file.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
TsiChung Liew [Fri, 28 Mar 2008 13:47:45 +0000 (08:47 -0500)]
ColdFire: Fix alignment issue after CONFIG_IDENT_STRING in start.S
When the version_string function in start.S is not 4-byte align,
it will cause the compiler generates "unaligned opcodes detected
in executable segment". This issue affects all ColdFire CPUs.
By adding .align 4 after CONFIG_IDENT_STRING, it will pad 0's if
it is not aligned.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: John Rigby <jrigby@freescale.com>
Mike Frysinger [Sun, 30 Mar 2008 19:46:13 +0000 (15:46 -0400)]
Blackfin: unify cpu and boot modes
All of the duplicated code for Blackfin processors and boot modes have been
unified. After all, the core is the same for all processors, just the
peripheral set differs (which gets handled in the drivers).
Support for the MX31ADS evaluation board from Freescale
This patch adds support for the MX31ADS evaluation board from Freescale,
initialization code is copied from RedBoot sources, also provided by Freescale.
Dirk Behme [Sun, 30 Mar 2008 10:09:01 +0000 (11:09 +0100)]
- Remove *_masked() functions as noted by Wolfgang
- Adapt register naming to recent TI spec (sprue26, March 2007)
- Fix reset_timer() handling
- As reported by Pieter [1] the overflow fix introduced a
delay of factor 16 (e.g 2 seconds became 32). While the
overflow fix is basically okay, it missed to divide udelay by
16, too. Fix this.
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179
- Remove software division of timer count value (DIV(x)
macro) and do it in hardware (TIM_CLK_DIV).
Many thanks to Troy Kisky <troy.kisky@boundarydevices.com>
and Pieter Voorthuijsen <pieter.voorthuijsen@Prodrive.nl> for
the hints & testing!
GRETH is an Ethernet 10/100 or 10/100/1000 MAC with out without
a debug link (EDCL). The GRETH core is documented in GRIP.pdf
available at www.gaisler.com.
If the GRETH has GigaBit support (GBIT, Scatter gather, checksum
offloading etc.) can be determined by a bit in the control register.
The GBIT MAC is supported by operating in GRTEH 10/100 legacy mode.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Aras Vaichas [Tue, 25 Mar 2008 22:43:57 +0000 (09:43 +1100)]
DHCP request fix for Windows Server 2003
Added option CONFIG_BOOTP_DHCP_REQUEST_DELAY. This provides an optional
delay before sending "DHCP Request" in net/bootp.c. Required to overcome
interoperability problems with Windows Server 200x DHCP server when U-Boot
client responds too fast for server to handle.
Signed-off-by: Aras Vaichas <arasv@magtech.com.au> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Daniel Hellstrom [Fri, 28 Mar 2008 19:40:19 +0000 (20:40 +0100)]
MTD/CFI: flash_read64 is defined a weak function (for SPARC)
SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.
For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.
Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
mpc8323erdb: fix EEPROM page size and get MAC from EEPROM
This patch fixes eeprom page size so that you can now write more than
64 bytes at a time.
It also makes the board take MAC addresses, if found, from EEPROM.
User should place up to 4 addresses at offset 0x7f00, for
eth{,1,2,3}addr. Any unused addresses should be zero. This group of
four six-byte values should have it's CRC at the end. crc32 and
eeprom commands can be used to accomplish this.
If CRC fails, MAC addresses come from the environment. If CRC
succeeds, the environment is overwritten at startup.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Kim Phillips [Fri, 28 Mar 2008 15:19:07 +0000 (10:19 -0500)]
mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display. Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Stefan Roese [Fri, 28 Mar 2008 13:09:04 +0000 (14:09 +0100)]
ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revision
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
displays the current configuration upon bootup and changes the PCIe
init loop, to only initialize the availabel PCIe slots.
R2D plus is SH reference board used with SH7751R.
This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface,
one PCI bus, VGA, and two Ethernet controller.
Yusuke Goda [Tue, 11 Mar 2008 03:55:12 +0000 (12:55 +0900)]
sh: Add support Renesas Solutions R7780MP
Renesas Solutions R7780MP is a reference board on SH7780.
This board has serial, 10/100 base Ethernet deivice, CF slot
and VGA devices. This board can set extension board.
Extension board has 10/100/1000 base Ethernet device, PCI slot,
S-ATA, iDVR slot.
Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Markus Brunner [Thu, 27 Mar 2008 09:46:25 +0000 (10:46 +0100)]
ppc4xx: PPC405EP Set EMAC noise filter bits
This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.
Signed-off-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Mike Nuss [Wed, 20 Feb 2008 16:54:20 +0000 (11:54 -0500)]
ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.
Signed-off-by: Mike Nuss <mike@terascala.com> Acked-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 19 Mar 2008 09:23:43 +0000 (10:23 +0100)]
ppc4xx: Add fdt support to Prodrive alpr
Since this board will probably be ported to arch/powerpc in the
near future, we add device tree support now. This way we are
"ready" for arch/powerpc from now on.
Stefan Roese [Wed, 26 Mar 2008 09:14:11 +0000 (10:14 +0100)]
ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
memory area will get subtracted from the top (end) of ram and won't get
"touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
should gets passed the now "corrected" memory size and won't touch it
either. This should work for arch/ppc and arch/powerpc. Only Linux board
ports in arch/powerpc with bootwrapper support, which recalculate the
memory size from the SDRAM controller setup, will have to get fixed
in Linux additionally.
This patch enables this config option on some PPC440EPx boards as a workaround
for the CHIP 11 errata. Here the description from the AMCC documentation:
CHIP_11: End of memory range area restricted access.
Category: 3
Overview:
The 440EPx DDR controller does not acknowledge any
transaction which is determined to be crossing over the
end-of-memory-range boundary, even if the starting address is
within valid memory space. Any such transaction from any PLB4
master will result in a PLB time-out on PLB4 bus.
Impact:
In case of such misaligned bursts, PLB4 masters will not
retrieve any data at all, just the available data up to the
end of memory, especially the 440 CPU. For example, if a CPU
instruction required an operand located in memory within the
last 7 words of memory, the DCU master would burst read 8
words to update the data cache and cross over the
end-of-memory-range boundary. Such a DCU read would not be
answered by the DDR controller, resulting in a PLB4 time-out
and ultimately in a Machine Check interrupt. The data would
be inaccessible to the CPU.
Workaround:
Forbid any application to access the last 256 bytes of DDR
memory. For example, make your operating system believe that
the last 256 bytes of DDR memory are absent. AMCC has a patch
that does this, available for Linux.
This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
lwmon5, korat, sequoia
The other remaining 440EPx board were intentionally not included
since it is not clear to me, if they use the end of ram for some
other purpose. This is unclear, since these boards have CONFIG_PRAM
defined and even comments like this:
PMC440.h:
/* esd expects pram at end of physical memory.
* So no logbuffer at the moment.
*/
It is strongly recommended to not use the last 256 bytes on those
boards too. Patches from the board maintainers are welcome.
Stefan Roese [Tue, 25 Mar 2008 16:51:13 +0000 (17:51 +0100)]
ppc4xx: Correctly pass phyiscal FLASH base address into dtb
The routine ft_board_setup() configures the EBC NOR mappings for the
Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from
0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS
problem, we need to pass the corrected address here too.
Timur Tabi [Fri, 14 Mar 2008 22:45:29 +0000 (17:45 -0500)]
Add support for setting the I2C bus speed in fsl_i2c.c
Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying
the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro,
but fsl_i2c.c ignores it and uses conservative value when programming the
I2C bus speed.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Dave Liu [Wed, 26 Mar 2008 14:55:32 +0000 (22:55 +0800)]
drivers: add the support for Freescale SATA controller
Add the Freescale on-chip SATA controller driver to u-boot,
The SATA controller is used on the 837x and 8315 targets,
The driver can be used to load kernel, fs and dtb.
The features list:
- 1.5/3 Gbps link speed
- LBA48, LBA28 support
- DMA and FPDMA support
- Two ports support
projects / u-boot / log