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8 years agoarm: socfpga: socrates: Remove Micrel PHY configuration
Marek Vasut [Sat, 5 Dec 2015 16:55:36 +0000 (17:55 +0100)]
arm: socfpga: socrates: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agoarm: socfpga: sockit: Remove Micrel PHY configuration
Marek Vasut [Sat, 5 Dec 2015 16:55:54 +0000 (17:55 +0100)]
arm: socfpga: sockit: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agoarm: socfpga: de0_nano: Remove Micrel PHY configuration
Marek Vasut [Sat, 5 Dec 2015 18:00:00 +0000 (19:00 +0100)]
arm: socfpga: de0_nano: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agoarm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration
Marek Vasut [Sat, 5 Dec 2015 16:55:19 +0000 (17:55 +0100)]
arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agoarm: socfpga: arria5-socdk: Remove Micrel PHY configuration
Marek Vasut [Sat, 5 Dec 2015 16:54:35 +0000 (17:54 +0100)]
arm: socfpga: arria5-socdk: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agoarm: socfpga: socrates: Add missing PHY skew config
Marek Vasut [Sat, 5 Dec 2015 16:53:40 +0000 (17:53 +0100)]
arm: socfpga: socrates: Add missing PHY skew config

Add missing KSZ9021 PHY skew configuration for the EBV socrates board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agonet: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF
Marek Vasut [Sat, 5 Dec 2015 16:41:58 +0000 (17:41 +0100)]
net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
V2: - Implement struct ksz90x1_reg_field to describe the skew register
      fields more accurately.
    - Fix RXDV/TXEN skew register default value and offset.

8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Fri, 18 Dec 2015 12:28:24 +0000 (07:28 -0500)]
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

8 years agomicroblaze: Do not handle watchdog and gpio in SPL
Michal Simek [Wed, 9 Dec 2015 10:53:25 +0000 (11:53 +0100)]
microblaze: Do not handle watchdog and gpio in SPL

watchdog and gpio are not validated for SPL that's why do not use them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Enable DM by default
Michal Simek [Wed, 9 Dec 2015 10:44:17 +0000 (11:44 +0100)]
microblaze: Enable DM by default

Enable DM for the whole architecture.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Enable OF_CONTROL by default
Michal Simek [Wed, 2 Dec 2015 13:21:05 +0000 (14:21 +0100)]
microblaze: Enable OF_CONTROL by default

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Remove support for LL_TEMAC
Michal Simek [Wed, 2 Dec 2015 16:22:07 +0000 (17:22 +0100)]
microblaze: Remove support for LL_TEMAC

LL_TEMAC is available at big endian MB and it is not properly tested
that's why the patch removes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Use malloc setting via Kconfig
Michal Simek [Tue, 8 Dec 2015 13:45:54 +0000 (14:45 +0100)]
microblaze: Use malloc setting via Kconfig

Clean board specific file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agomicroblaze: Make room for malloc before ELF
Michal Simek [Tue, 8 Dec 2015 13:34:13 +0000 (14:34 +0100)]
microblaze: Make room for malloc before ELF

Create space below u-boot binary for early malloc.
It means memory layout is stack grows down, space for early malloc,
u-boot code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agodm: net: Fix DM for targets which use MANUAL_RELOC
Michal Simek [Tue, 8 Dec 2015 15:45:30 +0000 (16:45 +0100)]
dm: net: Fix DM for targets which use MANUAL_RELOC

All ethernet operation needs to be updated for architectures which
requires MANUAL_RELOC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: gem: Add driver dependencies to PHYLIB
Michal Simek [Fri, 11 Dec 2015 08:14:31 +0000 (09:14 +0100)]
net: gem: Add driver dependencies to PHYLIB

Clear driver dependecies via Kconfig. Remove PHYLIB dependency from
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agonet: gem: Fix typo in Kconfig entry
Michal Simek [Wed, 9 Dec 2015 15:53:52 +0000 (16:53 +0100)]
net: gem: Fix typo in Kconfig entry

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: gem: Separate recv and free_pkt functions
Michal Simek [Wed, 9 Dec 2015 13:26:48 +0000 (14:26 +0100)]
net: gem: Separate recv and free_pkt functions

Use core to call net_process_received_packet() instead of call inside
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: gem: Fix return value from recv
Michal Simek [Wed, 9 Dec 2015 13:16:32 +0000 (14:16 +0100)]
net: gem: Fix return value from recv

recv function should return 0 instead of frame_len not to
proceed the same packet again in core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: gem: Setup default phy address to -1
Michal Simek [Wed, 9 Dec 2015 08:29:12 +0000 (09:29 +0100)]
net: gem: Setup default phy address to -1

Undefined phy address is -1 not 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoarm: zynq: Update ZYBO config options
Nathan Rossi [Tue, 8 Dec 2015 14:44:42 +0000 (00:44 +1000)]
arm: zynq: Update ZYBO config options

Update the ZYBO device tree and enable config options that relate to the
added devices in the device tree.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agospi: zynq_qspi: Add configuration to disable LQSPI feature
Nathan Rossi [Tue, 8 Dec 2015 14:44:40 +0000 (00:44 +1000)]
spi: zynq_qspi: Add configuration to disable LQSPI feature

When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the
device.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agotools: zynqimage: Clean up check_params
Nathan Rossi [Tue, 8 Dec 2015 14:44:43 +0000 (00:44 +1000)]
tools: zynqimage: Clean up check_params

Clean up the param checking, removing some code paths that will never
happen.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Reported-by: Coverity (CID 133251)
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: zynq: Add default ps7_init_gpl.c/h for ZYBO
Nathan Rossi [Tue, 24 Nov 2015 09:34:09 +0000 (19:34 +1000)]
ARM: zynq: Add default ps7_init_gpl.c/h for ZYBO

Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init
is generated by the Vivado 2015.3 tools using the system configuration
provided by Digilent located on their website.

Update the kconfig so that the defconfig is not overrided to use the
custom init ps7_init_gpl target by default.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: zynq: Enable u-boot,dm-pre-reloc for sdhci
Michal Simek [Tue, 8 Dec 2015 10:56:23 +0000 (11:56 +0100)]
ARM: zynq: Enable u-boot,dm-pre-reloc for sdhci

Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo.
And create aliases for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Fri, 18 Dec 2015 02:46:04 +0000 (21:46 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

8 years agousb: kbd: don't use int xfers when polling via ctrl xfers
Stephen Warren [Fri, 13 Nov 2015 20:34:09 +0000 (13:34 -0700)]
usb: kbd: don't use int xfers when polling via ctrl xfers

When CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP is enabled, use a
GET_REPORT control transfer to retrieve the initial state of the
keyboard. This matches the technique used to poll the keyboard state.
This is useful since it eliminates the remaining use of interrupt
transfers from the USB keyboard driver, which allows it to work with
USB HCD that don't support interrupt transfers.

Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agousb: add support of generic OHCI devices
Alexey Brodkin [Mon, 14 Dec 2015 14:18:50 +0000 (17:18 +0300)]
usb: add support of generic OHCI devices

This driver is meant to be used with any OHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
8 years agousb: host: ehci: samsung: Move hcor initialization after usb phy setup
Lukasz Majewski [Thu, 10 Dec 2015 15:32:25 +0000 (16:32 +0100)]
usb: host: ehci: samsung: Move hcor initialization after usb phy setup

With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.

To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
8 years agousb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h
Marek Vasut [Fri, 4 Dec 2015 01:51:20 +0000 (02:51 +0100)]
usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h

The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.

The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename s3c_udc_probe() function
Marek Vasut [Fri, 4 Dec 2015 01:26:33 +0000 (02:26 +0100)]
usb: s3c-otg: Rename s3c_udc_probe() function

The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.

The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_plat_otg_data
Marek Vasut [Fri, 4 Dec 2015 01:23:29 +0000 (02:23 +0100)]
usb: s3c-otg: Rename struct s3c_plat_otg_data

The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*
Marek Vasut [Wed, 19 Aug 2015 21:27:26 +0000 (23:27 +0200)]
usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*

The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:

  git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
  while read line ; do
    sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
  done

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Tweak the comments
Marek Vasut [Fri, 4 Dec 2015 01:55:37 +0000 (02:55 +0100)]
usb: s3c-otg: Tweak the comments

The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename remaining macros
Marek Vasut [Fri, 4 Dec 2015 01:44:33 +0000 (02:44 +0100)]
usb: s3c-otg: Rename remaining macros

The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename sources to dwc2_*c
Marek Vasut [Fri, 4 Dec 2015 01:34:46 +0000 (02:34 +0100)]
usb: s3c-otg: Rename sources to dwc2_*c

The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename local headers to dwc2_*h
Marek Vasut [Fri, 4 Dec 2015 01:32:22 +0000 (02:32 +0100)]
usb: s3c-otg: Rename local headers to dwc2_*h

The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Change the driver name to dwc2-udc
Marek Vasut [Fri, 4 Dec 2015 01:28:40 +0000 (02:28 +0100)]
usb: s3c-otg: Change the driver name to dwc2-udc

Just change the driver name.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Zap useless externs
Marek Vasut [Fri, 4 Dec 2015 01:21:41 +0000 (02:21 +0100)]
usb: s3c-otg: Zap useless externs

The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename remaining local s3c_*() functions
Marek Vasut [Fri, 4 Dec 2015 01:17:40 +0000 (02:17 +0100)]
usb: s3c-otg: Rename remaining local s3c_*() functions

The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename s3c_udc_*() functions
Marek Vasut [Fri, 4 Dec 2015 01:03:45 +0000 (02:03 +0100)]
usb: s3c-otg: Rename s3c_udc_*() functions

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename s3c_ep_*() functions
Marek Vasut [Fri, 4 Dec 2015 01:13:42 +0000 (02:13 +0100)]
usb: s3c-otg: Rename s3c_ep_*() functions

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename s3c_ep0_*() functions
Marek Vasut [Fri, 4 Dec 2015 00:59:12 +0000 (01:59 +0100)]
usb: s3c-otg: Rename s3c_ep0_*() functions

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.c
Marek Vasut [Fri, 4 Dec 2015 00:56:30 +0000 (01:56 +0100)]
usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.c

Just staticize the functions, they are not used outside of the file.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Staticize s3c_udc_ep_set_stall
Marek Vasut [Fri, 4 Dec 2015 00:52:03 +0000 (01:52 +0100)]
usb: s3c-otg: Staticize s3c_udc_ep_set_stall

This function is local to s3c_udc_otg_xfer_dma.c , staticize it.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_request
Marek Vasut [Fri, 4 Dec 2015 00:51:07 +0000 (01:51 +0100)]
usb: s3c-otg: Rename struct s3c_request

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_ep
Marek Vasut [Fri, 4 Dec 2015 00:48:57 +0000 (01:48 +0100)]
usb: s3c-otg: Rename struct s3c_ep

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_dev_*_ep
Marek Vasut [Fri, 4 Dec 2015 00:46:15 +0000 (01:46 +0100)]
usb: s3c-otg: Rename struct s3c_dev_*_ep

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy
Marek Vasut [Fri, 4 Dec 2015 00:44:41 +0000 (01:44 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Split private bits from s3c_udc.h
Marek Vasut [Fri, 4 Dec 2015 00:36:36 +0000 (01:36 +0100)]
usb: s3c-otg: Split private bits from s3c_udc.h

Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg
Marek Vasut [Fri, 4 Dec 2015 00:11:45 +0000 (01:11 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename struct s3c_udc to dwc2_udc
Marek Vasut [Thu, 3 Dec 2015 23:57:58 +0000 (00:57 +0100)]
usb: s3c-otg: Rename struct s3c_udc to dwc2_udc

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agousb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h
Marek Vasut [Thu, 3 Dec 2015 23:54:16 +0000 (00:54 +0100)]
usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h

Rename the header file, so it's obvious which driver it's part of.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Thu, 17 Dec 2015 12:52:56 +0000 (07:52 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agonet: fm: disables unused FM1-DTSEC1 MAC node in DTS
Shaohui Xie [Fri, 4 Dec 2015 02:22:03 +0000 (10:22 +0800)]
net: fm: disables unused FM1-DTSEC1 MAC node in DTS

We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since it is
used by MDIO. For FMAN v3, MDIO uses dedicated controller, so we
can disable unused FM1-DTSEC1 MAC node to avoid being probed in
Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043aqds/rcw: change core frequency to 1600MHz
Mingkai Hu [Mon, 7 Dec 2015 08:58:56 +0000 (16:58 +0800)]
armv8/ls1043aqds/rcw: change core frequency to 1600MHz

Change RCW for SD boot and NAND boot.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb/rcw: change core frequency to 1600MHz
Mingkai Hu [Mon, 7 Dec 2015 08:58:55 +0000 (16:58 +0800)]
armv8/ls1043ardb/rcw: change core frequency to 1600MHz

Change RCW for SD boot and NAND boot.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043a: Implement workaround for PEX erratum A009929
Mingkai Hu [Mon, 7 Dec 2015 08:58:54 +0000 (16:58 +0800)]
armv8/ls1043a: Implement workaround for PEX erratum A009929

Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/fsl_lsch2: fix DCSR_DCFG address
Mingkai Hu [Mon, 7 Dec 2015 08:58:53 +0000 (16:58 +0800)]
armv8/fsl_lsch2: fix DCSR_DCFG address

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043a: remove print info
Mingkai Hu [Mon, 7 Dec 2015 08:58:52 +0000 (16:58 +0800)]
armv8/ls1043a: remove print info

Remove verbose message for FMan port.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
[York Sun: Added commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodriver: net: fsl-mc: remove MC firmware version check
Stuart Yoder [Thu, 3 Dec 2015 21:14:04 +0000 (15:14 -0600)]
driver: net: fsl-mc: remove MC firmware version check

The MC version numbers provide no meaningful information
about binary interface compatibility, so remove the
check which refuses to start the MC unless a specific
version is found.

Version checking is supposed to be done at the individual
object level, and individual drivers are responsible
for their own version checking.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Wed, 16 Dec 2015 19:50:03 +0000 (14:50 -0500)]
Merge git://git.denx.de/u-boot-rockchip

8 years agoeeprom: fix eeprom write procedure
Alexey Brodkin [Mon, 14 Dec 2015 15:45:34 +0000 (18:45 +0300)]
eeprom: fix eeprom write procedure

This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b:
----------------------->8--------------------
eeprom: Pull out the RW loop

Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
----------------------->8--------------------

where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.

That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
8 years agoRevert "include/linux: move typdef for uintptr_t"
York Sun [Wed, 16 Dec 2015 06:12:24 +0000 (14:12 +0800)]
Revert "include/linux: move typdef for uintptr_t"

This reverts commit e8f954a756a825130d11b9c8fca70101dd8b3ac5, which
causes compiling errors on 32-bit hosts.

Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 15 Dec 2015 01:27:23 +0000 (20:27 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agoarmv8: Add sata support on Layerscape ARMv8 board
Tang Yuantian [Wed, 9 Dec 2015 07:32:18 +0000 (15:32 +0800)]
armv8: Add sata support on Layerscape ARMv8 board

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agodrivers/crypto/fsl: fix endianness issue in RNG
Aneesh Bansal [Tue, 8 Dec 2015 08:24:30 +0000 (13:54 +0530)]
drivers/crypto/fsl: fix endianness issue in RNG

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb: add SECURE BOOT target for NOR
Aneesh Bansal [Tue, 8 Dec 2015 08:24:29 +0000 (13:54 +0530)]
armv8/ls1043ardb: add SECURE BOOT target for NOR

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoinclude/linux: move typdef for uintptr_t
Aneesh Bansal [Tue, 8 Dec 2015 08:24:28 +0000 (13:54 +0530)]
include/linux: move typdef for uintptr_t

uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.

The typdef has been moved from include/compiler.h to include/linux/types.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: Make SEC read/write as snoopable for LS1043
Aneesh Bansal [Tue, 8 Dec 2015 08:24:27 +0000 (13:54 +0530)]
armv8: Make SEC read/write as snoopable for LS1043

For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: define usec2ticks function
Aneesh Bansal [Tue, 8 Dec 2015 08:24:26 +0000 (13:54 +0530)]
armv8: define usec2ticks function

usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agofsl_qspi: Pet the watchdog while reading/writing
Alexander Stein [Wed, 4 Nov 2015 08:19:10 +0000 (09:19 +0100)]
fsl_qspi: Pet the watchdog while reading/writing

When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
York Sun [Mon, 7 Dec 2015 19:08:58 +0000 (11:08 -0800)]
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agocommon: Rewrite hiding the end of memory
York Sun [Mon, 7 Dec 2015 19:05:29 +0000 (11:05 -0800)]
common: Rewrite hiding the end of memory

As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoarmv8: fsl-layerscape: Make DDR non secure in MMU tables
York Sun [Fri, 4 Dec 2015 19:57:08 +0000 (11:57 -0800)]
armv8: fsl-layerscape: Make DDR non secure in MMU tables

DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agoReserve secure memory
York Sun [Fri, 4 Dec 2015 19:57:07 +0000 (11:57 -0800)]
Reserve secure memory

Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.

"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agomove erratum a008336 and a008514 to soc specific file
Yao Yuan [Sat, 5 Dec 2015 06:59:14 +0000 (14:59 +0800)]
move erratum a008336 and a008514 to soc specific file

As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv7/fsl-ls102xa: Workaround for DDR erratum A008514
Yao Yuan [Sat, 5 Dec 2015 06:59:13 +0000 (14:59 +0800)]
armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv7: ls102xa: cci-400: Enable snoop and DVM message requests.
Yao Yuan [Sat, 5 Dec 2015 06:59:12 +0000 (14:59 +0800)]
armv7: ls102xa: cci-400: Enable snoop and DVM message requests.

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv7: omap-common: Rework SPL board_mmc_init()
Tom Rini [Mon, 14 Dec 2015 16:08:38 +0000 (11:08 -0500)]
armv7: omap-common: Rework SPL board_mmc_init()

Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional.  For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC).  A further rework and consolidation of the
functions should be done at a later date.

Tested on Beaglebone Black (SD and eMMC boot).

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agospl: mmc: use block device number, not hard-coded 0
Eric Nelson [Sat, 5 Dec 2015 19:32:28 +0000 (12:32 -0700)]
spl: mmc: use block device number, not hard-coded 0

In order to support boot from multiple devices through board_boot_order,
it's necessary to use the block number of a device.

The use of a hard-coded 0 for the device number also creates a need
to re-order block devices for use in SPL like this:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195

Signed-off-by: Eric Nelson <eric@nelint.com>
8 years agorockchip: Add basic support for kylin board
huang lin [Mon, 7 Dec 2015 03:08:57 +0000 (11:08 +0800)]
rockchip: Add basic support for kylin board

kylin board use rk3036 SOC, 512M sdram, 8G emmc.
This add some basic files required to allow the board
to output serial message and can run command(mmc info etc).

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036 sdram setting cs1_row when rank larger than 1
huang lin [Mon, 7 Dec 2015 03:08:56 +0000 (11:08 +0800)]
rockchip: rk3036 sdram setting cs1_row when rank larger than 1

only rank large than 1, we will use cs1_row, so check rank, when
rank larger than 1, we set the cs1_row.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoarm: ls102xa: enable all the snoop signal for masters.
Yao Yuan [Sat, 5 Dec 2015 06:59:11 +0000 (14:59 +0800)]
arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarm: ls1021a: merge SoC specific code in a separate file
Yao Yuan [Sat, 5 Dec 2015 06:59:10 +0000 (14:59 +0800)]
arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoqbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit
Tom Rini [Sat, 28 Nov 2015 13:04:42 +0000 (08:04 -0500)]
qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit

With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
becomes BUG_ON((!a) != b).  In this case reading of the function leads to
us wanting to rewrite this as BUG_ON(a != b).

Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Cc: Haiying Wang <Haiying.Wang@freescale.com>
Cc: Roy Pledge <Roy.Pledge@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agofsl_*_serdes.c: Modify memset call in serdes_init
Tom Rini [Sat, 28 Nov 2015 13:04:41 +0000 (08:04 -0500)]
fsl_*_serdes.c: Modify memset call in serdes_init

GCC 5.x does not like sizeof(array_variable) and errors out.  Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoEnable console log from earlyconsole in Linux bootargs
Pratiyush Mohan Srivastava [Sat, 31 Oct 2015 10:20:18 +0000 (15:50 +0530)]
Enable console log from earlyconsole in Linux bootargs

Remove 115200 from "earlycon" to avoid loss of initial
log messages during linux kernel 4.1  bootup

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls1043ardb: Add support for >2GB memory
Shaohui Xie [Mon, 23 Nov 2015 07:23:48 +0000 (15:23 +0800)]
armv8/ls1043ardb: Add support for >2GB memory

This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agofsl/ddr: updated ddr errata-A008378 for arm and power SoCs
Shengzhou Liu [Fri, 20 Nov 2015 07:52:04 +0000 (15:52 +0800)]
fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agofsl/errata: move fsl_errata.h to common directory
Shengzhou Liu [Fri, 20 Nov 2015 07:52:03 +0000 (15:52 +0800)]
fsl/errata: move fsl_errata.h to common directory

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarm: ls102x: add get_svr and IS_SVR_REV helper
Shengzhou Liu [Fri, 20 Nov 2015 07:52:02 +0000 (15:52 +0800)]
arm: ls102x: add get_svr and IS_SVR_REV helper

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agofreescale: fman: make sure phy-handle property is big endian
Shaohui Xie [Tue, 10 Nov 2015 11:20:16 +0000 (19:20 +0800)]
freescale: fman: make sure phy-handle property is big endian

When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls2080ardb: Update DDR settings for four chip-select case
York Sun [Wed, 4 Nov 2015 18:03:23 +0000 (10:03 -0800)]
armv8/ls2080ardb: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agoarmv8/ls2080aqds: Update DDR settings for four chip-select case
York Sun [Wed, 4 Nov 2015 18:03:22 +0000 (10:03 -0800)]
armv8/ls2080aqds: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodriver/ddr/fsl: Update timing config for heavy load
York Sun [Wed, 4 Nov 2015 18:03:21 +0000 (10:03 -0800)]
driver/ddr/fsl: Update timing config for heavy load

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodriver/ddr/fsl: Update workaround for A008511 for vref range
York Sun [Wed, 4 Nov 2015 18:03:20 +0000 (10:03 -0800)]
driver/ddr/fsl: Update workaround for A008511 for vref range

The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodriver/ddr/fsl: Update MR5 RTT park
York Sun [Wed, 4 Nov 2015 18:03:19 +0000 (10:03 -0800)]
driver/ddr/fsl: Update MR5 RTT park

For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodriver/ddr/fsl: Update DDR4 MR6 for Vref range
York Sun [Wed, 4 Nov 2015 18:03:18 +0000 (10:03 -0800)]
driver/ddr/fsl: Update DDR4 MR6 for Vref range

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
8 years agodriver/ddr/fsl: Update DDR4 RTT values
York Sun [Wed, 4 Nov 2015 18:03:17 +0000 (10:03 -0800)]
driver/ddr/fsl: Update DDR4 RTT values

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>