Simon Glass [Thu, 13 Dec 2012 20:49:13 +0000 (20:49 +0000)]
Only use fb_base if we have a display
The ideal of having a frame buffer when there isn't a display is not
that useful. Change the bdinfo command to expect this only when we
have an lcd or video display.
Simon Glass [Thu, 13 Dec 2012 20:49:08 +0000 (20:49 +0000)]
mips: Move per_clk and dev_clk to arch_global_data
Move these field into arch_global_data and tidy up. The other
CONFIG_JZSOC fields are used by various architectures, so just remove
the #ifdef bracketing for these.
Simon Glass [Thu, 13 Dec 2012 20:48:46 +0000 (20:48 +0000)]
ppc: Move clock fields to arch_global_data
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.
Simon Glass [Thu, 13 Dec 2012 20:48:45 +0000 (20:48 +0000)]
ppc: Remove extra pci_clk fields from global_data
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.
Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.
Simon Glass [Thu, 13 Dec 2012 20:48:42 +0000 (20:48 +0000)]
x86: Set up the global data pointer in C instead of asm
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.
Remove the asm code and add equivalent code in C.
This idea was proposed by Graeme Russ here:
http://patchwork.ozlabs.org/patch/199741/
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order] Signed-off-by: Tom Rini <trini@ti.com>
Marek Vasut [Fri, 11 Jan 2013 03:35:48 +0000 (03:35 +0000)]
vfat: Fix mkcksum argument sizes
In case a function argument is known/fixed size array in C, the argument is
still decoyed as pointer instead ( T f(U n[k]) ~= T fn(U *n) ) and therefore
calling sizeof on the function argument will result in the size of the pointer,
not the size of the array.
The VFAT code contains such a bug, this patch fixes it.
Reported-by: Aaron Williams <Aaron.Williams@cavium.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <tom.rini@gmail.com> Cc: Aaron Williams <Aaron.Williams@cavium.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Gabor Juhos [Wed, 30 Jan 2013 04:31:52 +0000 (04:31 +0000)]
MIPS: add unified u-boot.lds file
The patch adds an unified linker script file which
can be used for all currently supported MIPS targets.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Stefan Roese <sr@denx.de>
Gabor Juhos [Wed, 30 Jan 2013 02:22:51 +0000 (02:22 +0000)]
MIPS: remove OUTPUT_FORMAT from linker scripts
The OUTPUT_FORMAT command in linker scripts
was always misused due to some endianess and
toolchain problems.
Use GCC flags to ensure proper output format,
and get rid of the OUTPUT_FORMAT commands in
the board specific u-boot.lds files.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.
The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.
This approach makes the code a bit simpler because
it needs two instructions only.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
The difference between the address of the original
and the relocated _GLOBAL_OFFSET_TABLE_ is always
the same as the relocation offset.
The relocation offset is already computed and it is
available in the 's1/t6' register. Use that to adjust
the relocated _G_O_T_ address, instead of calculating
the offset again from the _gp value.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Andy Fleming [Thu, 24 Jan 2013 07:55:11 +0000 (01:55 -0600)]
corenet: Disable video on P2020DS
The P2020DS build had grown too large, and video support isn't enabled
in almost any other Freescale board. Disabling it allows us to keep
building, and provides options for reenabling it later.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Shengzhou Liu [Wed, 23 Jan 2013 19:56:23 +0000 (19:56 +0000)]
powerpc/t4240: Adding workaround errata A-005871
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.
This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.
The Workaround is for the T4240 silicon rev 1.0.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Vakul Garg [Wed, 23 Jan 2013 22:52:31 +0000 (22:52 +0000)]
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.
Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
BSC9132QDS is a Freescale reference design board for BSC9132 SoC.
BSC9132 SOC is an integrated device that targets the evolving Microcell,
Picocell, and Enterprise-Femto base station market subsegments.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
BSC9132QDS Overview
--------------------
2Gbyte DDR3 (on board DDR), Dual Ranki
32Mbyte 16bit NOR flash
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
SD slot
USB-ULPI
eTSEC1: Connected to SGMII PHY
eTSEC2: Connected to SGMII PHY
PCIe
CPRI
SerDes
I2C RTC
DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
James Yang [Mon, 7 Jan 2013 14:01:03 +0000 (14:01 +0000)]
powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable. Commands are separated using ';'.
ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
James Yang [Fri, 4 Jan 2013 08:14:01 +0000 (08:14 +0000)]
Fix data stage name matching issue
This fix allows the name of the stage to be specifed after the
controler and DIMM is specified. Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 4 Jan 2013 08:13:59 +0000 (08:13 +0000)]
powerpc/mpc8xxx: Enable entering DDR debugging by key press
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.
CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
All the dev boards of Freescale's QorIQ family have a RCW that is
supported by the u-boot.pbl build target. This patch adds one for the
P2041 dev board.
This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the
P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Qixis FPGA has tag data contains image name and build date.
It is helpful to identify the FPGA image precisely.
Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaveta Leekha [Sun, 23 Dec 2012 19:25:35 +0000 (19:25 +0000)]
powerpc/qixis: enable qixis dump command and add switch dumping command
Remove #ifdef so that "qixis dump" command is always available
Add "qixis_reset switch" command to dump switch settings
Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from
registers to figure out switch settings. Not all bits are available.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Sun, 23 Dec 2012 19:25:27 +0000 (19:25 +0000)]
powerpc/b4860qds: Added Support for B4860QDS
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.
B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".
EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.
board/freescale/common:Add support of QTAG register
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.
Add support to parse these fields to have complete FPGA image information.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Poonam Aggrwal [Sun, 23 Dec 2012 19:24:16 +0000 (19:24 +0000)]
powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.
Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G
Poonam Aggrwal [Sun, 23 Dec 2012 19:22:33 +0000 (19:22 +0000)]
powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
serdes1= 0x2c, 0x2d, 0x2e
serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Hongtao Jia [Thu, 20 Dec 2012 19:36:12 +0000 (19:36 +0000)]
powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs
The controller interleaving only takes the usable memory mapped to cs0. In
the case of bank interleaving not enabled, only half of dual-rank DIMM will
be used.
For single-rank DIMM bank interleaving will be auto disabled.
Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
projects / u-boot / log