Anton Vorontsov [Thu, 8 Jan 2009 01:26:12 +0000 (04:26 +0300)]
mpc83xx: Add support for MPC83xx PCI-E controllers
This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.
The patch is based on Tony Li and Dave Liu work[1].
Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.
To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.
Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ira Snyder [Mon, 12 Jan 2009 21:33:17 +0000 (13:33 -0800)]
MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent mode
When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do
not enable them. See the MPC8349EA Reference Manual, Section 4.4.2
"Clocking in PCI Agent Mode".
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ira Snyder [Mon, 12 Jan 2009 21:32:26 +0000 (13:32 -0800)]
83xx: PCI agent mode fixes for multi-board systems
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode,
the boards will lock up the PCI bus by scanning against each other.
The boards lock against each other by trying to access the PCI bus before
clearing their configuration lock bit. Both boards end up in a loop,
sending and receiving "Target Not Ready" messages forever.
When running in PCI agent mode, the scanning now takes place after the
boards have cleared their configuration lock bit.
Also, add a missing declaration to the mpc83xx.h header file, fixing a
build warning.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ron Madrid [Fri, 12 Dec 2008 21:12:45 +0000 (13:12 -0800)]
mpc83xx: Size optimization of start.S
Currently there are in excess of 100 bytes located at the beginning of the image
built by start.S that are not being utilized. This patch moves a few functions
into this part of the image. This will create a greater number of *available*
bytes that can be used by board specific code in NAND builds and will decrease
the size of the assembled code in other builds.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Peter Korsgaard [Wed, 14 Jan 2009 12:52:24 +0000 (13:52 +0100)]
fdt_resize(): fix actualsize calculations with unaligned blobs
The code in fdt_resize() to extend the fdt size to end on a page boundary
is wrong for fdt's not located at an address aligned on a page boundary.
What's even worse, the code would make actualsize shrink rather than grow
if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
causing fdt_add_mem_rsv to fail.
Fix it by aligning end address (blob + size) to a page boundary instead.
For aligned fdt's this is equivalent to what we had before.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.
Matthias Fuchs [Fri, 2 Jan 2009 11:16:35 +0000 (12:16 +0100)]
ppc4xx: Enable auto RS485 mode on PLU405 boards
This patch turns on the auto RS485 mode in the 2nd external
uart on PLU405 boards. This is a special mode of the used
Exar XR16C2850 uart. Because these boards only have a 485 physical
layer connected it's a good idea to turn it on by default.
Signed-off-by: Matthias Fuchs <mf@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
Haiying Wang [Tue, 13 Jan 2009 21:29:28 +0000 (16:29 -0500)]
Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Roy Zang [Fri, 9 Jan 2009 08:02:35 +0000 (16:02 +0800)]
Change PCIE1&2 deciide logic on MPC8544DS board more readable
The IO port selection for MPC8544DS board:
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Roy Zang [Fri, 9 Jan 2009 08:01:52 +0000 (16:01 +0800)]
PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Roy Zang [Fri, 9 Jan 2009 08:00:55 +0000 (16:00 +0800)]
Fix IO port selection issue on MPC8544DS and MPC8572DS boards
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
This patch fixes this issue.
For MPC8572
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf
PCIE2 0x3, 0x7
PCIE3 0x7
For MPC8544
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Becky Bruce [Thu, 4 Dec 2008 04:36:44 +0000 (22:36 -0600)]
mpc8610hpcd: Fix PCI mapping concepts
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Becky Bruce [Thu, 4 Dec 2008 04:36:26 +0000 (22:36 -0600)]
sbc8641d: Fix PCI mapping concepts
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Trent Piepho [Wed, 3 Dec 2008 23:16:37 +0000 (15:16 -0800)]
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
Trent Piepho [Wed, 3 Dec 2008 23:16:35 +0000 (15:16 -0800)]
mpc8568: Double local bus clock divider
The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.
Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.
Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
Dave Liu [Tue, 16 Dec 2008 04:09:27 +0000 (12:09 +0800)]
85xx: Fix the boot window issue
If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.
It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.
For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.
So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.
Paul Gortmaker [Thu, 11 Dec 2008 20:47:50 +0000 (15:47 -0500)]
sbc8548: use proper PHY address
The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would not auto negotiate
down to 100M or 10M.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Haiying Wang [Wed, 3 Dec 2008 15:08:19 +0000 (10:08 -0500)]
Set IVPR to kenrel entry point in second core boot page
Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Trent Piepho [Wed, 3 Dec 2008 23:16:38 +0000 (15:16 -0800)]
mpc8[56]xx: Put localbus clock in device tree
Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.
Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.
Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be. So it seems no
one was quite sure what to put in their dts files.
Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code. The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.
For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code. On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.
Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
Kumar Gala [Tue, 16 Dec 2008 20:59:22 +0000 (14:59 -0600)]
NAND FSL elbc: Use virt_to_phys to determine which bank is in use
The current code that determines which bank/chipselect is used for a
given NAND instance only worked for 32-bit addresses and assumed
a 1:1 mapping. This breaks in 36-bit physical configs.
The proper way to handle this is to use the virt_to_phys() and
BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
with the the virtual address the NAND code uses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Scott Wood <scottwood@freescale.com>
Peter Tyser [Wed, 17 Dec 2008 22:36:21 +0000 (16:36 -0600)]
Add support for PCA953x I2C gpio devices
Initial support for NXP's 4 and 8 bit I2C gpio expanders
(eg pca9537, pca9557, etc). The CONFIG_PCA953X define
enables support for the devices while the CONFIG_CMD_PCA953X
define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO
define enables an 'info' sub-command which provides summary
information for the given pca953x device.
Wolfgang Denk [Tue, 16 Dec 2008 21:32:25 +0000 (22:32 +0100)]
board/trab/memory.c: Fix compile problems.
Apply changes from commit 44b4dbed to board/trab/memory.c, too.
Actually we'd need a major cleanup here - as it turns out,
board/trab/memory.c is more or less a verbatim copy of
post/drivers/memory.c ... but then, trab is EOL anyway,r
so this is not worth the effort.
Scott Wood [Tue, 16 Dec 2008 20:24:16 +0000 (14:24 -0600)]
NAND: Mark the BBT as scanned prior to calling scan_bbt.
Otherwise, recursion can occur if scan_bbt does not find a bad block
table, and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Becky Bruce [Thu, 4 Dec 2008 05:04:37 +0000 (23:04 -0600)]
powerpc: fix io.h build warning with CONFIG_PHYS_64BIT
Casting a pointer to a phys_addr_t when it's an unsigned long long
on a 32-bit system without first casting to a non-pointer type
generates a compiler warning. Fix this.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Wolfgang Denk [Tue, 16 Dec 2008 13:44:06 +0000 (14:44 +0100)]
post/Makefile: fix dependency problem with parallel builds
Parallel builds (using "make -jN") would occasionally fail with error
messages like
ppc_4xxFP-objdump: string.o: File format not recognized
or
post/libpost.a(cpu.o): In function `cpu_post_test':
/home/wd/git/u-boot/work/post/lib_ppc/cpu.c:130: undefined reference to `cpu_post_test_string'
or similar. We now make sure to run the 'postdeps" step before
attempting to build the specific POST libraries.
Wolfgang Denk [Tue, 16 Dec 2008 13:41:02 +0000 (14:41 +0100)]
Makefile: fix dependency problem with parallel builds
Parallel builds (using "make -jN") would occasionally fail with error
messages like
include/autoconf.mk:212: *** missing separator. Stop.
Line numbers and affected boards were changing. Obviously some
Makefiles included autoconf.mk while it was still being written to.
As a fix, we now write to a temporary file first and then rename it,
so that it is really ready to use as soon as it appears.
Mike Frysinger [Thu, 11 Dec 2008 23:39:08 +0000 (18:39 -0500)]
spi/stmicro: fix debug() display of cmd
The stmicro_wait_ready() func tries to show the actual opcode that was sent
to the device, but instead it displays the array pointer. Fix it to pull
out the opcode from the start of the array.
Mike Frysinger [Thu, 11 Dec 2008 11:23:37 +0000 (06:23 -0500)]
env_sf: support embedded environments
If both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE are defined, and the sect
size is larger than the env size, then it means the env is embedded in a
block. So we have to save/restore the part of the sector which is not the
environment. Previously, saving the environment in SPI flash in this
setup would probably brick the board as the rest of the sector tends to
contain actual U-Boot data/code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Timur Tabi [Wed, 3 Dec 2008 17:28:30 +0000 (11:28 -0600)]
i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Kumar Gala [Sat, 13 Dec 2008 23:20:28 +0000 (17:20 -0600)]
Introduce addr_map library
Add a library that helps in translating between virtual and physical
addresses. This library can be useful as a simple means to implement
map_physmem() and virt_to_phys() for platforms that need functionality
beyond the simple 1:1 mapping.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 13 Dec 2008 23:20:27 +0000 (17:20 -0600)]
Introduce virt_to_phys()
virt_to_phys() returns the physical address given a virtual. In most
cases this will be just the input value as the vast majority of
systems run in a 1:1 mode.
However in systems that are not running this way it should report the
physical address or ~0 if no mapping exists for the given virtual
address.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
projects / u-boot / log