/* */
/* */
/* */
-/* (w) 2015 Groepaz/Hitmen (groepaz@gmx.net) */
+/* (w) 2015 Groepaz/Hitmen (groepaz@gmx.net) */
/* based on technical reference by PeT (mess@utanet.at) */
/* */
/* This software is provided 'as-is', without any expressed or implied */
/*
base clock cpu clock/32 ?
-0/1: 1. channel(right): 12 bit frequency: right frequency 0 nothing, 1 high; 3 23khz; 4 17,3; 10 6,9; 15 4.6; $60 720hz; $eff 18,0; $fff 16,9 hz)
+0/1: 1. channel(right): 12 bit frequency: right frequency 0 nothing, 1 high;
+ 3 23khz; 4 17,3; 10 6,9; 15 4.6; $60 720hz; $eff 18,0; $fff 16,9 hz)
(delay clock/32)
2/3: 2. channel(left): 12 bit frequency
4/5: 3. channel(both): 12 bit frequency
bit 3:
*/
-#define JOY_DATA 0x4400
-
-#define JOY_DATA_UP 0x01
-#define JOY_DATA_DOWN 0x02
-#define JOY_DATA_LEFT 0x04
-#define JOY_DATA_RIGHT 0x08
-#define JOY_DATA_FIRE_A 0x10
-#define JOY_DATA_FIRE_B 0x20
-#define JOY_DATA_START 0x40
-#define JOY_DATA_SELECT 0x80
-
/* LCD
resolution 160x152 in 4 greys/greens
#define LCD_READ 0x5006 /* read from RAM (no auto inc?) */
#define LCD_DATA 0x5007 /* write to RAM */
+/* BIOS zeropage usage */
+
+/* locations 0x0a-0x0c, 0x0e-0x11 and 0xe8 are in use by the BIOS IRQ/NMI handlers */
+#define ZP_NMI_4800 0x0a /* content of I/O reg 4800 gets copied here each NMI */
+
+#define ZP_IRQ_COUNT 0x0b /* increments once per IRQ, used elsewhere in the
+ BIOS for synchronisation purposes */
+#define ZP_IRQ_CTRL 0x0c /* if 0 then cartridge irq stubs will not get called */
+
+/* each of the following 4 increments by 1 per IRQ - it is _not_ a 32bit
+ counter (see code at $ffa6 in BIOS)
+ these are not used elsewhere in the bios and can be (re)set as needed by
+ the user.
+*/
+#define ZP_IRQ_CNT1 0x0e
+#define ZP_IRQ_CNT2 0x0f
+#define ZP_IRQ_CNT3 0x10
+#define ZP_IRQ_CNT4 0x11
+
+#define ZP_NMI_FLAG 0xe8 /* set to 0xff each NMI */
/* constants for the conio implementation */
#define COLOR_BLACK 0x03
#define COLOR_WHITE 0x00
-#define CH_HLINE 1
-#define CH_VLINE 2
-#define CH_CROSS 3
-#define CH_ULCORNER 4
-#define CH_URCORNER 5
-#define CH_LLCORNER 6
-#define CH_LRCORNER 7
-#define CH_TTEE 8
-#define CH_BTEE 9
+#define CH_HLINE 1
+#define CH_VLINE 2
+#define CH_CROSS 3
+#define CH_ULCORNER 4
+#define CH_URCORNER 5
+#define CH_LLCORNER 6
+#define CH_LRCORNER 7
+#define CH_TTEE 8
+#define CH_BTEE 9
-#define CH_RTEE 11
-#define CH_LTEE 12
+#define CH_RTEE 11
+#define CH_LTEE 12
-#define CH_ENTER 13
-#define CH_PI 18
+#define CH_ENTER 13
+#define CH_PI 18
-#define TV_NTSC 0
-#define TV_PAL 1
-#define TV_OTHER 2
+#define TV_NTSC 0
+#define TV_PAL 1
+#define TV_OTHER 2
/* No support for dynamically loadable drivers */
#define DYN_DRV 0
+/* Masks for joy_read */
+#define JOY_UP_MASK 0x01
+#define JOY_DOWN_MASK 0x02
+#define JOY_LEFT_MASK 0x04
+#define JOY_RIGHT_MASK 0x08
+#define JOY_BTN_1_MASK 0x10
+#define JOY_BTN_2_MASK 0x20
+#define JOY_BTN_3_MASK 0x40
+#define JOY_BTN_4_MASK 0x80
+
+#define JOY_BTN_A_MASK JOY_BTN_1_MASK
+#define JOY_BTN_B_MASk JOY_BTN_2_MASK
+#define JOY_START_MASK JOY_BTN_3_MASK
+#define JOY_SELECT_MASK JOY_BTN_4_MASK
+
+#define JOY_BTN_A(v) ((v) & JOY_BTN_A_MASK)
+#define JOY_BTN_B(v) ((v) & JOY_BTN_B_MASK)
+#define JOY_START(v) ((v) & JOY_START_MASK)
+#define JOY_SELECT(v) ((v) & JOY_SELECT_MASK)
+
/* The addresses of the static drivers */
extern void gamate_stdjoy_joy[]; /* Referred to by joy_static_stddrv[] */
-#define JOY_FIRE_B 5
-#define JOY_START 6
-#define JOY_SELECT 7
-
-void waitvblank (void);
-/* Wait for the vertical blanking */
+void waitvsync (void);
+/* Wait for start of next frame */
/* NOTE: all Gamate are "NTSC" */
-#define get_tv() TV_NTSC
+#define get_tv() TV_NTSC
/* Return the video mode the machine is using. */
/* End of gamate.h */
projects / cc65 / blobdiff