1 /******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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2 * File Name : 75x_mrcc.c
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3 * Author : MCD Application Team
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4 * Date First Issued : 03/10/2006
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5 * Description : This file provides all the MRCC software functions.
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6 ********************************************************************************
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10 ********************************************************************************
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11 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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13 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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14 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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15 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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16 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 *******************************************************************************/
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19 /* Includes ------------------------------------------------------------------*/
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20 #include "75x_mrcc.h"
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22 /* Private typedef -----------------------------------------------------------*/
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23 /* Private define ------------------------------------------------------------*/
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24 #define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */
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26 /* MRCC_PWRCTRL mask bits */
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27 #define MRCC_LP_Set_Mask 0x00000001
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28 #define MRCC_LP_Reset_Mask 0xFFFFFFFE
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29 #define MRCC_SWRESET_Mask 0x00000002
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30 #define MRCC_WFI_Mask 0x00000004
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31 #define MRCC_STANDBY_Mask 0x00000006
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32 #define MRCC_LPMC_Reset_Mask 0xFFFFFFF9
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33 #define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F
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34 #define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF
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35 #define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF
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36 #define MRCC_CKRTCSEL_Set_Mask 0x03000000
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37 #define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF
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38 #define MRCC_CKRTCOK_Mask 0x08000000
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39 #define MRCC_LPOSCEN_Mask 0x10000000
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40 #define MRCC_OSC32KEN_Mask 0x20000000
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42 /* MRCC_CLKCTL mask bits */
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43 #define MRCC_PPRESC_Set_Mask 0x00000003
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44 #define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC
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45 #define MRCC_PPRESC2_Mask 0x00000004
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46 #define MRCC_HPRESC_Set_Mask 0x00000018
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47 #define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7
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48 #define MRCC_MCOS_Reset_Mask 0xFFFFFF3F
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49 #define MRCC_XTDIV2_Set_Mask 0x00008000
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50 #define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF
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51 #define MRCC_OSC4MBYP_Set_Mask 0x00010000
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52 #define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF
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53 #define MRCC_OSC4MOFF_Set_Mask 0x00020000
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54 #define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF
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55 #define MRCC_NCKDF_Set_Mask 0x00040000
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56 #define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF
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57 #define MRCC_CKOSCSEL_Set_Mask 0x00200000
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58 #define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF
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59 #define MRCC_CKUSBSEL_Mask 0x00400000
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60 #define MRCC_CKSEL_Set_Mask 0x00800000
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61 #define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF
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62 #define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000
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63 #define MRCC_PLLEN_Set_Mask 0x01000000
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64 #define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF
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65 #define MRCC_PLL2EN_Set_Mask 0x02000000
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66 #define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF
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67 #define MRCC_MX_Set_Mask 0x18000000
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68 #define MRCC_MX_Reset_Mask 0xE7FFFFFF
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69 #define MRCC_LOCK_Mask 0x80000000
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70 #define MRCC_PLLEN_LOCK_Mask 0x81000000
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72 /* Typical Value of the OSC4M in Hz */
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73 #define OSC4M_Value 4000000
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75 /* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */
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76 #define OSC4M_Div128_Value 31250
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78 /* Typical Value of the OS32K Oscillator Frequency in Hz */
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79 #define OSC32K_Value 32768
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81 /* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */
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82 #define LPOSC_Value 245000
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84 /* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */
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85 #define FREEOSC_Value 5000000
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87 /* Time out for OSC4M start up */
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88 #define OSC4MStartUp_TimeOut 0xFE
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90 /* Private macro -------------------------------------------------------------*/
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91 /* Private variables ---------------------------------------------------------*/
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92 /* Private function prototypes -----------------------------------------------*/
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93 static ErrorStatus SetCKSYS_FREEOSC(void);
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94 static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State);
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95 static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul);
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96 static ErrorStatus SetCKSYS_RTC(u32 PLL_State);
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97 static void WriteLPBit(void);
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98 static void WriteCKOSCSELBit(void);
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100 /* Private functions ---------------------------------------------------------*/
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102 /*******************************************************************************
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103 * Function Name : MRCC_DeInit
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104 * Description : Deinitializes the MRCC peripheral registers to their default
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106 * - Depending on the system clock state, some bits in MRCC_CLKCTL
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107 * register can
\92t be reset.
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108 * - The OSC32K, LPOSC and RTC clock selection configuration
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109 * bits in MRCC_PWRCTRL register are not cleared by this
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110 * function. To reset those bits, use the dedicated functions
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111 * available within this driver.
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112 * - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not
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113 * reset by this function.
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117 *******************************************************************************/
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118 void MRCC_DeInit(void)
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120 /* Try to clear NCKDF bit */
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121 MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask;
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123 if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET)
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124 {/* No clock detected on OSC4M */
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126 /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0],
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127 MCOP, HPRESC[1:0], PPRES[2:0] bits */
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128 MRCC->CLKCTL &= 0x9FB40000;
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130 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
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132 /* Clear CKOSCSEL bit --------------------------------------------------*/
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133 /* Execute CKOSCSEL bit writing sequence */
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134 WriteCKOSCSELBit();
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138 {/* Clock present on OSC4M */
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140 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
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142 /* Reset CKSEL bit */
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143 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
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145 /* Clear CKOSCSEL bit --------------------------------------------------*/
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146 /* Execute CKOSCSEL bit writing sequence */
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147 WriteCKOSCSELBit();
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150 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)
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152 /* Set CKSEL bit */
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153 MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
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157 MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;
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159 /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP,
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160 HPRESC[1:0], PPRES[2:0] bits */
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161 MRCC->CLKCTL &= 0x87B70000;
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163 /* Reset CKSEL bit */
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164 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
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166 /* Reset OSC4MOFF and OSC4MBYP bits */
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167 MRCC->CLKCTL &= 0xFFFCFFFF;
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170 /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */
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171 MRCC->PWRCTRL &= 0xFBFE1FE1;
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173 /* Reset PCLKEN register bits */
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174 MRCC->PCLKEN = 0x00;
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176 /* Reset PSWRES register bits */
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177 MRCC->PSWRES = 0x00;
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179 /* Clear NCKDF bit */
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180 MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask;
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183 /*******************************************************************************
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184 * Function Name : MRCC_XTDIV2Config
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185 * Description : Enables or disables the oscillator divider by 2. This function
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186 * must not be used when the PLL is enabled.
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187 * Input : - MRCC_XTDIV2: specifies the new state of the oscillator
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189 * This parameter can be one of the following values:
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190 * - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled
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191 * - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled
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194 *******************************************************************************/
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195 void MRCC_XTDIV2Config(u32 MRCC_XTDIV2)
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197 if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable)
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199 MRCC->CLKCTL |= MRCC_XTDIV2_Enable;
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203 MRCC->CLKCTL &= MRCC_XTDIV2_Disable;
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207 /*******************************************************************************
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208 * Function Name : MRCC_CKSYSConfig
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209 * Description : Configures the system clock (CK_SYS).
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210 * Input : - MRCC_CKSYS: specifies the clock source used as system clock.
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211 * This parameter can be one of the following values:
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212 * - MRCC_CKSYS_FREEOSC
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213 * - MRCC_CKSYS_OSC4M
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214 * - MRCC_CKSYS_OSC4MPLL
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215 * - MRCC_CKSYS_RTC (RTC clock source must be previously
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216 * configured using MRCC_CKRTCConfig() function)
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217 * : - MRCC_PLL: specifies the PLL configuration.
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218 * This parameter can be one of the following values:
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219 * - MRCC_PLL_Disabled: PLL disabled
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220 * - MRCC_PLL_NoChange: No change on PLL configuration
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221 * - MRCC_PLL_Mul_12: Multiplication by 12
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222 * - MRCC_PLL_Mul_14: Multiplication by 14
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223 * - MRCC_PLL_Mul_15: Multiplication by 15
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224 * - MRCC_PLL_Mul_16: Multiplication by 16
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226 * Return : An ErrorStatus enumuration value:
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227 * - SUCCESS: Clock configuration succeeded
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228 * - ERROR: Clock configuration failed
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229 *******************************************************************************/
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230 ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL)
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232 ErrorStatus Status = ERROR;
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236 case MRCC_CKSYS_FREEOSC:
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237 if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))
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239 Status = SetCKSYS_FREEOSC();
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243 case MRCC_CKSYS_OSC4M:
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244 if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))
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246 Status = SetCKSYS_OSC4M(MRCC_PLL);
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250 case MRCC_CKSYS_OSC4MPLL:
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251 if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) ||
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252 (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16))
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254 Status = SetCKSYS_OSC4MPLL(MRCC_PLL);
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258 case MRCC_CKSYS_RTC:
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259 if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))
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261 Status = SetCKSYS_RTC(MRCC_PLL);
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272 /*******************************************************************************
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273 * Function Name : MRCC_HCLKConfig
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274 * Description : Configures the AHB clock (HCLK).
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275 * Input : - MRCC_HCLK: defines the AHB clock. This clock is derived
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276 * from the system clock(CK_SYS).
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277 * This parameter can be one of the following values:
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278 * - MRCC_CKSYS_Div1: AHB clock = CK_SYS
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279 * - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2
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280 * - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4
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281 * - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8
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284 *******************************************************************************/
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285 void MRCC_HCLKConfig(u32 MRCC_HCLK)
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289 /* Clear HPRESC[1:0] bits */
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290 Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask;
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292 /* Set HPRESC[1:0] bits according to MRCC_HCLK value */
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295 /* Store the new value */
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296 MRCC->CLKCTL = Temp;
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299 /*******************************************************************************
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300 * Function Name : MRCC_CKTIMConfig
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301 * Description : Configures the TIM clock (CK_TIM).
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302 * Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived
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303 * from the AHB clock(HCLK).
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304 * This parameter can be one of the following values:
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305 * - MRCC_HCLK_Div1: TIM clock = HCLK
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306 * - MRCC_HCLK_Div2: TIM clock = HCLK/2
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307 * - MRCC_HCLK_Div4: TIM clock = HCLK/4
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308 * - MRCC_HCLK_Div8: TIM clock = HCLK/8
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311 *******************************************************************************/
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312 void MRCC_CKTIMConfig(u32 MRCC_CKTIM)
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316 /* Clear PPRESC[1:0] bits */
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317 Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask;
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319 /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */
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320 Temp |= MRCC_CKTIM;
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322 /* Store the new value */
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323 MRCC->CLKCTL = Temp;
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326 /*******************************************************************************
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327 * Function Name : MRCC_PCLKConfig
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328 * Description : Configures the APB clock (PCLK).
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329 * Input : - MRCC_PCLK: defines the APB clock. This clock is derived
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330 * from the TIM clock(CK_TIM).
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331 * This parameter can be one of the following values:
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332 * - MRCC_CKTIM_Div1: APB clock = CKTIM
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333 * - MRCC_CKTIM_Div2: APB clock = CKTIM/2
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336 *******************************************************************************/
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337 void MRCC_PCLKConfig(u32 MRCC_PCLK)
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339 if(MRCC_PCLK == MRCC_CKTIM_Div2)
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341 MRCC->CLKCTL |= MRCC_CKTIM_Div2;
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345 MRCC->CLKCTL &= MRCC_CKTIM_Div1;
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349 /*******************************************************************************
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350 * Function Name : MRCC_CKRTCConfig
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351 * Description : Configures the RTC clock (CK_RTC).
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352 * Input : - MRCC_CKRTC: specifies the clock source to be used as RTC
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354 * This parameter can be one of the following values:
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355 * - MRCC_CKRTC_OSC4M_Div128
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356 * - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled
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357 * using MRCC_OSC32KConfig() function)
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358 * - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled
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359 * using MRCC_LPOSCConfig() function)
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361 * Return : An ErrorStatus enumuration value:
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362 * - SUCCESS: Clock configuration succeeded
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363 * - ERROR: Clock configuration failed
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364 *******************************************************************************/
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365 ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC)
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369 if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) &&
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370 ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET))
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372 /* CK_RTC used as CK_SYS clock source */
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377 /* Clear CKRTCSEL[1:0] bits */
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378 Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask;
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380 /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */
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383 /* Store the new value */
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384 MRCC->PWRCTRL = Tmp;
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390 /*******************************************************************************
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391 * Function Name : MRCC_CKUSBConfig
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392 * Description : Configures the USB clock(CK_USB).
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393 * Input : - MRCC_CKUSB: specifies the clock source to be used as USB
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395 * This parameter can be one of the following values:
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396 * - MRCC_CKUSB_Internal(CK_PLL2 enabled)
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397 * - MRCC_CKUSB_External(CK_PLL2 disabled)
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399 * Return : An ErrorStatus enumuration value:
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400 * - SUCCESS: Clock configuration succeeded
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401 * - ERROR: Clock configuration failed
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402 *******************************************************************************/
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403 ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB)
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405 if(MRCC_CKUSB == MRCC_CKUSB_External)
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407 /* Disable CK_PLL2 */
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408 MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask;
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410 /* External USB clock selected */
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411 MRCC->CLKCTL |= MRCC_CKUSB_External;
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415 if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET)
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416 { /* PLL enabled and locked */
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418 /* Enable CK_PLL2 */
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419 MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask;
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421 /* Internal USB clock selected */
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422 MRCC->CLKCTL &= MRCC_CKUSB_Internal;
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426 /* PLL not enabled */
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434 /*******************************************************************************
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435 * Function Name : MRCC_ITConfig
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436 * Description : Enables or disables the specified MRCC interrupts.
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437 * Input : - MRCC_IT: specifies the MRCC interrupts sources to be
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438 * enabled or disabled. This parameter can be any combination
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439 * of the following values:
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440 * - MRCC_IT_LOCK: PLL lock interrupt
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441 * - MRCC_IT_NCKD: No Clock detected interrupt
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442 * - NewState: new state of the MRCC interrupts.
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443 * This parameter can be: ENABLE or DISABLE.
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446 *******************************************************************************/
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447 void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState)
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449 if(NewState == ENABLE)
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451 MRCC->CLKCTL |= MRCC_IT;
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455 MRCC->CLKCTL &= ~MRCC_IT;
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459 /*******************************************************************************
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460 * Function Name : MRCC_PeripheralClockConfig
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461 * Description : Enables or disables the specified peripheral clock.
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462 * Input : - MRCC_Peripheral: specifies the peripheral to gates its
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463 * clock. More than one peripheral can be selected using
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464 * the
\93|
\94 operator.
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465 * - NewState: new state of the specified peripheral clock.
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466 * This parameter can be one of the following values:
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467 * - ENABLE: the selected peripheral clock is enabled
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468 * - DISABLE: the selected peripheral clock is disabled
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471 *******************************************************************************/
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472 void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState)
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474 if(NewState == ENABLE)
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476 MRCC->PCLKEN |= MRCC_Peripheral;
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480 MRCC->PCLKEN &= ~MRCC_Peripheral;
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484 /*******************************************************************************
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485 * Function Name : MRCC_PeripheralSWResetConfig
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486 * Description : Forces or releases peripheral software reset.
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487 * Input : - MRCC_Peripheral: specifies the peripheral to reset. More
\r
488 * than one peripheral can be selected using the
\93|
\94 operator.
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489 * - NewState: new state of the specified peripheral software
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490 * reset. This parameter can be one of the following values:
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491 * - ENABLE: the selected peripheral is kept under reset
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492 * - DISABLE: the selected peripheral exits from reset
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495 *******************************************************************************/
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496 void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState)
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498 if(NewState == ENABLE)
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500 MRCC->PSWRES |= MRCC_Peripheral;
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504 MRCC->PSWRES &= ~MRCC_Peripheral;
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508 /*******************************************************************************
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509 * Function Name : MRCC_GetClocksStatus
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510 * Description : Returns the status and frequencies of different on chip clocks.
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511 * Don
\92t use this function when CK_SYS is clocked by an external
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512 * clock source (OSC4M bypassed).
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513 * Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure
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514 * which will hold the clocks information.
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517 *******************************************************************************/
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518 void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus)
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524 /* Get the Status of PLL */
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525 if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)
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527 MRCC_ClocksStatus->PLL_Status = OFF;
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531 MRCC_ClocksStatus->PLL_Status = ON;
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534 /* Get the Status of OSC4M */
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535 if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)
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537 MRCC_ClocksStatus->OSC4M_Status = ON;
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541 MRCC_ClocksStatus->OSC4M_Status = OFF;
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544 /* Get the Status of LPOSC */
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545 if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET)
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547 MRCC_ClocksStatus->LPOSC_Status = OFF;
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551 MRCC_ClocksStatus->LPOSC_Status = ON;
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554 /* Get the Status of OSC32K */
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555 if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET)
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557 MRCC_ClocksStatus->OSC32K_Status = OFF;
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561 MRCC_ClocksStatus->OSC32K_Status = ON;
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564 /* Get CKU_SB source ---------------------------------------------------------*/
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565 if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET)
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567 MRCC_ClocksStatus->CKUSB_Source = External;
\r
571 if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET)
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573 MRCC_ClocksStatus->CKUSB_Source = Internal;
\r
578 MRCC_ClocksStatus->CKUSB_Source = Disabled;
\r
582 /* Get CK_RTC source ---------------------------------------------------------*/
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583 Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask;
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589 MRCC_ClocksStatus->CKRTC_Source = Disabled;
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593 MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128;
\r
597 MRCC_ClocksStatus->CKRTC_Source = OSC32K;
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601 MRCC_ClocksStatus->CKRTC_Source = LPOSC;
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605 MRCC_ClocksStatus->CKRTC_Source = Disabled;
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609 /* Get CK_SYS source ---------------------------------------------------------*/
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610 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)
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611 {/* CK_OSC used as CK_SYS clock source */
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613 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
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614 { /* CK_RTC used as CK_OSC clock source */
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615 MRCC_ClocksStatus->CKSYS_Source = CKRTC;
\r
617 if(MRCC_ClocksStatus->CKRTC_Source == OSC32K)
\r
619 /* CK_SYS clock frequency */
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620 MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value;
\r
622 else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC)
\r
625 /* CK_SYS clock frequency */
\r
626 MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value;
\r
628 else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128)
\r
631 /* CK_SYS clock frequency */
\r
632 MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value;
\r
636 { /* OSC4M used as CK_OSC clock source */
\r
637 MRCC_ClocksStatus->CKSYS_Source = OSC4M;
\r
639 if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET)
\r
641 /* CK_SYS clock frequency */
\r
642 MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1;
\r
646 /* CK_SYS clock frequency */
\r
647 MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator;
\r
652 {/* CK_PLL1 used as CK_SYS clock */
\r
654 if(MRCC_ClocksStatus->PLL_Status == OFF)
\r
655 { /* FREEOSC used as CK_PLL1 clock source */
\r
656 MRCC_ClocksStatus->CKSYS_Source = FREEOSC;
\r
658 /* CK_SYS clock frequency */
\r
659 MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value;
\r
662 { /* OSC4M followed by PLL used as CK_PLL1 clock source */
\r
663 MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL;
\r
665 /* Get PLL factor ------------------------------------------------------*/
\r
666 Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask;
\r
692 /* CK_SYS clock frequency */
\r
693 MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul;
\r
697 /* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/
\r
698 /* Get HCLK prescaler */
\r
699 Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask;
\r
700 Presc = Presc >> 3;
\r
701 /* HCLK clock frequency */
\r
702 MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc;
\r
704 /* Get CK_TIM prescaler */
\r
705 Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask;
\r
706 /* CK_TIM clock frequency */
\r
707 MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc;
\r
709 /* Get PCLK prescaler */
\r
710 Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask;
\r
711 Presc = Presc >> 2;
\r
712 /* PCLK clock frequency */
\r
713 MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc;
\r
716 /*******************************************************************************
\r
717 * Function Name : MRCC_LPMC_DBGonfig
\r
718 * Description : Enables or disables the Low Power Debug Mode.
\r
719 * Input : - MRCC_LPDM: specifies the LPDM new state value.
\r
720 * This parameter can be one of the following values:
\r
721 * - MRCC_LPDM_Disable
\r
722 * - MRCC_LPDM_Enable
\r
725 *******************************************************************************/
\r
726 void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM)
\r
728 if(MRCC_LPDM == MRCC_LPDM_Enable)
\r
730 MRCC->PWRCTRL |= MRCC_LPDM_Enable;
\r
734 MRCC->PWRCTRL &= MRCC_LPDM_Disable;
\r
738 /*******************************************************************************
\r
739 * Function Name : MRCC_EnterWFIMode
\r
740 * Description : Enters WFI mode.
\r
741 * If the Flash is used in Burst mode, it must be kept enabled
\r
742 * in WFI mode(use MRCC_WFIParam_FLASHOn as parameter)
\r
743 * Input : - MRCC_WFIParam: specifies the WFI mode control parameters.
\r
744 * This parameter can be one of the following values:
\r
745 * - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI)
\r
746 * - MRCC_WFIParam_FLASHOn(DMA allowed during WFI)
\r
747 * - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI)
\r
750 *******************************************************************************/
\r
751 void MRCC_EnterWFIMode(u32 MRCC_WFIParam)
\r
753 /* Low Power mode configuration ----------------------------------------------*/
\r
754 /* Clear LPMC[1:0] bits */
\r
755 MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;
\r
757 /* Select WFI mode */
\r
758 MRCC->PWRCTRL |= MRCC_WFI_Mask;
\r
760 /* Low Power mode control parameters configuration ---------------------------*/
\r
761 /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */
\r
762 MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask;
\r
764 if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown)
\r
766 /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */
\r
767 MRCC->PWRCTRL |= MRCC_WFIParam;
\r
770 /* Execute the Low Power bit writing sequence --------------------------------*/
\r
774 /*******************************************************************************
\r
775 * Function Name : MRCC_EnterSTOPMode
\r
776 * Description : Enters STOP mode.
\r
777 * Input : - MRCC_STOPParam: specifies the STOP mode control parameters.
\r
778 * This parameter can be one of the following values:
\r
779 * - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On)
\r
780 * - MRCC_STOPParam_OSC4MOff
\r
781 * - MRCC_STOPParam_FLASHOff
\r
782 * - MRCC_STOPParam_MVREGOff
\r
785 *******************************************************************************/
\r
786 void MRCC_EnterSTOPMode(u32 MRCC_STOPParam)
\r
788 /* Low Power mode configuration ----------------------------------------------*/
\r
789 /* Clear LPMC[1:0] bits (STOP mode is selected) */
\r
790 MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;
\r
792 /* Low Power mode control parameters configuration ---------------------------*/
\r
793 /* Clear LP_PARAM[15:13] bits */
\r
794 MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask;
\r
796 if(MRCC_STOPParam != MRCC_STOPParam_Default)
\r
798 /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */
\r
799 MRCC->PWRCTRL |= MRCC_STOPParam;
\r
802 /* Execute the Low Power bit writing sequence --------------------------------*/
\r
806 /*******************************************************************************
\r
807 * Function Name : MRCC_EnterSTANDBYMode
\r
808 * Description : Enters STANDBY mode.
\r
809 * Make sure that WKPF flag is cleared before using this function.
\r
813 *******************************************************************************/
\r
814 void MRCC_EnterSTANDBYMode(void)
\r
816 /* Low Power mode configuration ----------------------------------------------*/
\r
817 /* Clear LPMC[1:0] bits */
\r
818 MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;
\r
820 /* Select STANDBY mode */
\r
821 MRCC->PWRCTRL |= MRCC_STANDBY_Mask;
\r
823 /* Execute the Low Power bit writing sequence --------------------------------*/
\r
827 /*******************************************************************************
\r
828 * Function Name : MRCC_GenerateSWReset
\r
829 * Description : Generates a system software reset.
\r
833 *******************************************************************************/
\r
834 void MRCC_GenerateSWReset(void)
\r
836 /* Low Power mode configuration ----------------------------------------------*/
\r
837 /* Clear LPMC[1:0] bits */
\r
838 MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;
\r
840 /* Select software reset */
\r
841 MRCC->PWRCTRL |= MRCC_SWRESET_Mask;
\r
843 /* Execute the Low Power bit writing sequence --------------------------------*/
\r
847 /*******************************************************************************
\r
848 * Function Name : MRCC_WriteBackupRegister
\r
849 * Description : Writes user data to the specified backup register.
\r
850 * Input : - MRCC_BKP: specifies the backup register.
\r
851 * This parameter can be one of the following values:
\r
854 * - Data: data to write.
\r
857 *******************************************************************************/
\r
858 void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data)
\r
860 if(MRCC_BKP == MRCC_BKP0)
\r
870 /*******************************************************************************
\r
871 * Function Name : MRCC_ReadBackupRegister
\r
872 * Description : Reads data from the specified backup register.
\r
873 * Input : - MRCC_BKP: specifies the backup register.
\r
874 * This parameter can be one of the following values:
\r
878 * Return : The content of the specified backup register.
\r
879 *******************************************************************************/
\r
880 u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP)
\r
882 if(MRCC_BKP == MRCC_BKP0)
\r
884 return(MRCC->BKP0);
\r
888 return(MRCC->BKP1);
\r
892 /*******************************************************************************
\r
893 * Function Name : MRCC_IOVoltageRangeConfig
\r
894 * Description : Configures the I/O pins voltage range.
\r
895 * Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range.
\r
896 * This parameter can be one of the following values:
\r
897 * - MRCC_IOVoltageRange_5V
\r
898 * - MRCC_IOVoltageRange_3V3
\r
901 *******************************************************************************/
\r
902 void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange)
\r
904 if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3)
\r
906 MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3;
\r
910 MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V;
\r
914 /*******************************************************************************
\r
915 * Function Name : MRCC_MCOConfig
\r
916 * Description : Selects the clock source to output on MCO pin (P0.1).
\r
917 * To output the clock, the associated alternate function must
\r
918 * be enabled in the I/O port controller.
\r
919 * Input : - MRCC_MCO: specifies the clock source to output.
\r
920 * This parameter can be one of the following values:
\r
924 * - MRCC_MCO_CKPLL2
\r
925 * - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2,
\r
926 * is applied to this clock before outputting it to MCO pin.
\r
927 * This parameter can be one of the following values:
\r
928 * - MRCC_MCOPrescaler_1
\r
929 * - MRCC_MCOPrescaler_2
\r
932 *******************************************************************************/
\r
933 void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler)
\r
936 /* MCO prescaler configuration -----------------------------------------------*/
\r
937 if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2)
\r
939 MRCC->CLKCTL |= MRCC_MCOPrescaler_2;
\r
943 MRCC->CLKCTL &= MRCC_MCOPrescaler_1;
\r
946 /* MCO selection configuration -----------------------------------------------*/
\r
948 /* Clear MCOS[1:0] bits */
\r
949 Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask;
\r
951 /* Set MCOS[1:0] bits according to MRCC_MCO value */
\r
954 /* Store the new value */
\r
955 MRCC->CLKCTL = Temp;
\r
958 /*******************************************************************************
\r
959 * Function Name : MRCC_OSC4MConfig
\r
960 * Description : Configures the 4MHz main oscillator (OSC4M).
\r
961 * This function must be used when the CK_SYS is not clocked
\r
962 * by the OSC4M and the PLL is not enabled.
\r
963 * Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator.
\r
964 * This parameter can be one of the following values:
\r
965 * - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled
\r
966 * - MRCC_OSC4M_Disable: OSC4M disabled
\r
967 * - MRCC_OSC4M_Bypass: OSC4M bypassed
\r
969 * Return : An ErrorStatus enumuration value:
\r
970 * - SUCCESS: Clock configuration succeeded
\r
971 * - ERROR: Clock configuration failed
\r
972 *******************************************************************************/
\r
973 ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M)
\r
975 ErrorStatus Status = SUCCESS;
\r
977 /* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/
\r
978 if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) ||
\r
979 (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) &&
\r
980 ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))||
\r
981 ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET))
\r
985 /* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/
\r
990 case MRCC_OSC4M_Default:
\r
991 MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask;
\r
994 case MRCC_OSC4M_Disable:
\r
995 MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask;
\r
996 MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask;
\r
999 case MRCC_OSC4M_Bypass:
\r
1000 MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask;
\r
1001 MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask;
\r
1013 /*******************************************************************************
\r
1014 * Function Name : MRCC_OSC32KConfig
\r
1015 * Description : Configures the OSC32K oscillator.
\r
1016 * This function must be used when the CK_SYS is not clocked by
\r
1018 * Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator.
\r
1019 * This parameter can be one of the following values:
\r
1020 * - MRCC_OSC32K_Disable: OSC32K disabled
\r
1021 * - MRCC_OSC32K_Enable: OSC32K enabled
\r
1022 * - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is
\r
1023 * bypassed or not.
\r
1024 * This parameter can be one of the following values:
\r
1025 * - MRCC_OSC32KBypass_Disable: OSC32K selected
\r
1026 * - MRCC_OSC32KBypass_Enable: OSC32K bypassed
\r
1028 * Return : An ErrorStatus enumuration value:
\r
1029 * - SUCCESS: Clock configuration succeeded
\r
1030 * - ERROR: Clock configuration failed
\r
1031 *******************************************************************************/
\r
1032 ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass)
\r
1034 /* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/
\r
1035 if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) &&
\r
1036 ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET))
\r
1040 /* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/
\r
1043 /* Configure OSC32KEN bit */
\r
1044 if(MRCC_OSC32K == MRCC_OSC32K_Enable)
\r
1046 MRCC->PWRCTRL |= MRCC_OSC32K_Enable;
\r
1050 MRCC->PWRCTRL &= MRCC_OSC32K_Disable;
\r
1053 /* Configure OSC32KBYP bit */
\r
1054 if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable)
\r
1056 MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable;
\r
1060 MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable;
\r
1067 /*******************************************************************************
\r
1068 * Function Name : MRCC_LPOSCConfig
\r
1069 * Description : Enables or disables the LPOSC oscillator.
\r
1070 * This function must be used when the CK_SYS is not clocked by
\r
1072 * Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator.
\r
1073 * This parameter can be one of the following values:
\r
1074 * - MRCC_LPOSC_Disable: LPOSC disabled
\r
1075 * - MRCC_LPOSC_Enable: LPOSC enabled
\r
1077 * Return : An ErrorStatus enumuration value:
\r
1078 * - SUCCESS: Clock configuration succeeded
\r
1079 * - ERROR: Clock configuration failed
\r
1080 *******************************************************************************/
\r
1081 ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC)
\r
1083 /* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/
\r
1084 if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) &&
\r
1085 ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) ||
\r
1086 ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC))
\r
1090 /* Else configure the LPOSCEN bit --------------------------------------------*/
\r
1093 if(MRCC_LPOSC == MRCC_LPOSC_Enable)
\r
1095 MRCC->PWRCTRL |= MRCC_LPOSC_Enable;
\r
1099 MRCC->PWRCTRL &= MRCC_LPOSC_Disable;
\r
1106 /*******************************************************************************
\r
1107 * Function Name : MRCC_RTCMConfig
\r
1108 * Description : Enables or disables RTC clock measurement.
\r
1109 * Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB
\r
1110 * timer IC1 or not.
\r
1111 * This parameter can be one of the following values:
\r
1112 * - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1
\r
1113 * - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1
\r
1116 *******************************************************************************/
\r
1117 void MRCC_RTCMConfig(u32 MRCC_RTCM)
\r
1119 if(MRCC_RTCM == MRCC_RTCM_Enable)
\r
1121 MRCC->PWRCTRL |= MRCC_RTCM_Enable;
\r
1125 MRCC->PWRCTRL &= MRCC_RTCM_Disable;
\r
1129 /*******************************************************************************
\r
1130 * Function Name : MRCC_SetBuilderCounter
\r
1131 * Description : Sets the builder counter value which defines the delay for
\r
1132 * the 4MHz main oscillator (OSC4M) clock to be stabilized.
\r
1133 * Input : - BuilderCounter: defines the delay for the OSC4M oscillator
\r
1134 * clock to be stabilized.
\r
1137 *******************************************************************************/
\r
1138 void MRCC_SetBuilderCounter(u8 BuilderCounter)
\r
1140 *(u8 *) 0x60000026 = BuilderCounter;
\r
1143 /*******************************************************************************
\r
1144 * Function Name : MRCC_GetCKSYSCounter
\r
1145 * Description : Gets the result of the delay applied to CK_SYS before
\r
1146 * starting the CPU.
\r
1149 * Return : SCOUNT value.
\r
1150 *******************************************************************************/
\r
1151 u16 MRCC_GetCKSYSCounter(void)
\r
1153 return((u16)(MRCC->RFSR & 0x0FFF));
\r
1156 /*******************************************************************************
\r
1157 * Function Name : MRCC_GetFlagStatus
\r
1158 * Description : Checks whether the specified MRCC flag is set or not.
\r
1159 * Input : - MRCC_FLAG: specifies the flag to check.
\r
1160 * This parameter can be one of the following values:
\r
1161 * - MRCC_FLAG_LOCK: PLL Locked flag
\r
1162 * - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag
\r
1163 * - MRCC_FLAG_CKSEL: CK_SYS source staus flag
\r
1164 * - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag
\r
1165 * - MRCC_FLAG_NCKD: No Clock Detected flag
\r
1166 * - MRCC_FLAG_SWR: Software Reset flag
\r
1167 * - MRCC_FLAG_WDGR: Watchdog Reset flag
\r
1168 * - MRCC_FLAG_EXTR: External Reset flag
\r
1169 * - MRCC_FLAG_WKP: Wake-Up flag
\r
1170 * - MRCC_FLAG_STDB: STANDBY flag
\r
1171 * - MRCC_FLAG_BCOUNT: Builder Counter Flag
\r
1172 * - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready
\r
1173 * - MRCC_FLAG_CKRTCOK: CK_RTC OK
\r
1174 * - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed
\r
1175 * - MRCC_FLAG_LP: Low Power Mode Entry
\r
1177 * Return : The new state of MRCC_FLAG (SET or RESET).
\r
1178 *******************************************************************************/
\r
1179 FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG)
\r
1181 u32 MRCCReg = 0, FlagPos = 0;
\r
1182 u32 StatusReg = 0;
\r
1184 /* Get the MRCC register index */
\r
1185 MRCCReg = MRCC_FLAG >> 5;
\r
1187 /* Get the flag position */
\r
1188 FlagPos = MRCC_FLAG & MRCC_FLAG_Mask;
\r
1190 if(MRCCReg == 1) /* The flag to check is in CLKCTL register */
\r
1192 StatusReg = MRCC->CLKCTL;
\r
1194 else if (MRCCReg == 2) /* The flag to check is in RFSR register */
\r
1196 StatusReg = MRCC->RFSR;
\r
1198 else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */
\r
1200 StatusReg = MRCC->PWRCTRL;
\r
1203 if((StatusReg & (1 << FlagPos))!= RESET)
\r
1213 /*******************************************************************************
\r
1214 * Function Name : MRCC_ClearFlag
\r
1215 * Description : Clears the MRCC
\92s pending flags.
\r
1216 * Input : - MRCC_FLAG: specifies the flag to clear.
\r
1217 * This parameter can be one of the following values:
\r
1218 * - MRCC_FLAG_NCKD: No Clock Detected flag
\r
1219 * - MRCC_FLAG_SWR: Software Reset flag
\r
1220 * - MRCC_FLAG_WDGR: Watchdog Reset flag
\r
1221 * - MRCC_FLAG_EXTR: External Reset flag
\r
1222 * - MRCC_FLAG_WKP: Wake-Up flag
\r
1223 * - MRCC_FLAG_STDB: STANDBY flag
\r
1224 * - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed
\r
1227 *******************************************************************************/
\r
1228 void MRCC_ClearFlag(u8 MRCC_FLAG)
\r
1230 u32 MRCCReg = 0, FlagPos = 0;
\r
1232 /* Get the MRCC register index */
\r
1233 MRCCReg = MRCC_FLAG >> 5;
\r
1235 /* Get the flag position */
\r
1236 FlagPos = MRCC_FLAG & MRCC_FLAG_Mask;
\r
1238 if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */
\r
1240 MRCC->CLKCTL &= ~(1 << FlagPos);
\r
1242 else if (MRCCReg == 2) /* The flag to clear is in RFSR register */
\r
1244 MRCC->RFSR &= ~(1 << FlagPos);
\r
1246 else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */
\r
1248 MRCC->PWRCTRL &= ~(1 << FlagPos);
\r
1252 /*******************************************************************************
\r
1253 * Function Name : MRCC_GetITStatus
\r
1254 * Description : Checks whether the specified MRCC interrupt has occurred or not.
\r
1255 * Input : - MRCC_IT: specifies the MRCC interrupt source to check.
\r
1256 * This parameter can be one of the following values:
\r
1257 * - MRCC_IT_LOCK: PLL lock interrupt
\r
1258 * - MRCC_IT_NCKD: No Clock detected interrupt
\r
1260 * Return : The new state of MRCC_IT (SET or RESET).
\r
1261 *******************************************************************************/
\r
1262 ITStatus MRCC_GetITStatus(u32 MRCC_IT)
\r
1264 /* Check the specified interrupt pending bit */
\r
1265 if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET)
\r
1275 /*******************************************************************************
\r
1276 * Function Name : MRCC_ClearITPendingBit
\r
1277 * Description : Clears the MRCC
\92s interrupt pending bits.
\r
1278 * Input : - MRCC_IT: specifies the interrupt pending bit to clear.
\r
1279 * This parameter can be any combination of the following
\r
1281 * - MRCC_IT_LOCK: PLL lock interrupt
\r
1282 * - MRCC_IT_NCKD: No Clock detected interrupt
\r
1285 *******************************************************************************/
\r
1286 void MRCC_ClearITPendingBit(u32 MRCC_IT)
\r
1288 /* Clear the specified interrupt pending bit */
\r
1289 MRCC->CLKCTL &= ~(MRCC_IT >> 1);
\r
1292 /*******************************************************************************
\r
1293 * Function Name : MRCC_WaitForOSC4MStartUp
\r
1294 * Description : Waits for OSC4M start-up.
\r
1297 * Return : An ErrorStatus enumuration value:
\r
1298 * - SUCCESS: OSC4M oscillator is stable and ready to use
\r
1299 * - ERROR: no clock is detected on OSC4M
\r
1300 *******************************************************************************/
\r
1301 ErrorStatus MRCC_WaitForOSC4MStartUp(void)
\r
1303 u32 StartUpCounter = 0;
\r
1307 /* Clear No Clock Detected flag */
\r
1308 if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET)
\r
1310 MRCC_ClearFlag(MRCC_FLAG_NCKD);
\r
1315 }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&&
\r
1316 (StartUpCounter != OSC4MStartUp_TimeOut));
\r
1318 if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET)
\r
1328 /*******************************************************************************
\r
1329 * Function Name : SetCKSYS_FREEOSC
\r
1330 * Description : Selects FREEOSC as CK_SYS clock source.
\r
1333 * Return : An ErrorStatus enumuration value:
\r
1334 * - SUCCESS: Clock configuration succeeded
\r
1335 * - ERROR: Clock configuration failed
\r
1336 *******************************************************************************/
\r
1337 static ErrorStatus SetCKSYS_FREEOSC(void)
\r
1339 /* Check if the PLL is enabled */
\r
1340 if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)
\r
1342 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)
\r
1343 { /* CK_PLL1 used as Ck_SYS clock source*/
\r
1345 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
\r
1346 {/* Check if CK_RTC source clock is present*/
\r
1347 if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET)
\r
1349 /* CK_RTC disabled*/
\r
1354 /* Select CK_OSC as CK_SYS clock source */
\r
1355 MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
\r
1359 MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;
\r
1362 /* Select CK_PLL1 as CK_SYS clock source */
\r
1363 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1365 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)
\r
1375 /*******************************************************************************
\r
1376 * Function Name : SetCKSYS_OSC4M
\r
1377 * Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source.
\r
1378 * Input : PLL_State: specifies the PLL state.
\r
1380 * Return : An ErrorStatus enumuration value:
\r
1381 * - SUCCESS: Clock configuration succeeded
\r
1382 * - ERROR: Clock configuration failed
\r
1383 *******************************************************************************/
\r
1384 static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State)
\r
1386 /* If OSC4M is not present, exit ---------------------------------------------*/
\r
1387 if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) ||
\r
1388 ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) )
\r
1390 /* OSC4M disabled or OSC4M clock is not present*/
\r
1394 /* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/
\r
1395 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
\r
1396 { /* CK_RTC used as CK_OSC clock */
\r
1398 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)
\r
1400 /* Select CK_PLL1 as CK_SYS clock source */
\r
1401 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1404 /* Clear CKOSCSEL bit ----------------------------------------------------*/
\r
1405 /* Execute CKOSCSEL bit writing sequence */
\r
1406 WriteCKOSCSELBit();
\r
1408 /* Check if CKOSCSEL is set to 0 */
\r
1409 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
\r
1415 /* Select CK_OSC as CK_SYS clock source */
\r
1416 MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
\r
1418 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)
\r
1420 if(PLL_State == MRCC_PLL_Disabled)
\r
1423 MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;
\r
1434 /*******************************************************************************
\r
1435 * Function Name : SetCKSYS_OSC4MPLL
\r
1436 * Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as
\r
1437 * CK_SYS clock source.
\r
1438 * Input : PLL_Mul: specifies the PLL factor.
\r
1440 * Return : An ErrorStatus enumuration value:
\r
1441 * - SUCCESS: Clock configuration succeeded
\r
1442 * - ERROR: Clock configuration failed
\r
1443 *******************************************************************************/
\r
1444 static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul)
\r
1446 /* Check if 4MHz main oscillator clock is present */
\r
1447 if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) &&
\r
1448 ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET))
\r
1450 if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) &&
\r
1451 ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul))
\r
1453 /* Select CK_PLL1 as CK_SYS clock source */
\r
1454 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1456 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)
\r
1467 /* If CK_RTC is selected as CK_OSC clock source */
\r
1468 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
\r
1470 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)
\r
1472 /* Clear CKSEL bit */
\r
1473 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1476 /* Clear CKOSCSEL bit ------------------------------------------------*/
\r
1477 /* Execute CKOSCSEL bit writing sequence */
\r
1478 WriteCKOSCSELBit();
\r
1480 /* Check if CKOSCSEL is set to 0 */
\r
1481 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
\r
1487 /* Select CK_OSC as CK_SYS clock source */
\r
1488 MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
\r
1491 MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;
\r
1493 /* Configure PLL factor */
\r
1494 if(PLL_Mul == MRCC_PLL_Mul_16)
\r
1496 MRCC->CLKCTL &= MRCC_MX_Reset_Mask;
\r
1498 else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) ||
\r
1499 (PLL_Mul == MRCC_PLL_Mul_12))
\r
1501 /* Clear MX[1:0] bits */
\r
1502 MRCC->CLKCTL &= MRCC_MX_Reset_Mask;
\r
1503 /* Set MX[1:0] bits according to PLL_Mul value */
\r
1504 MRCC->CLKCTL |= PLL_Mul;
\r
1507 if(Main_Oscillator == 4000000)
\r
1508 {/* 4 MHz external Quartz oscillator used as main oscillator */
\r
1509 /* Disable Oscillator Divider by 2 */
\r
1510 MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask;
\r
1512 else if(Main_Oscillator == 8000000)
\r
1513 {/* 8 MHz external Quartz oscillator used as main oscillator */
\r
1514 /* Enable Oscillator Divider by 2 */
\r
1515 MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask;
\r
1519 MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask;
\r
1521 /* Wait until the PLL is locked */
\r
1522 while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET)
\r
1524 /* If OSC4M clock disapear or the PLL is disabled, exit */
\r
1525 if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) ||
\r
1526 ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET))
\r
1532 /* Select CK_PLL1 as CK_SYS clock source */
\r
1533 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1535 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)
\r
1547 /* OSC4M disabled or OSC4M clock is not present*/
\r
1552 /*******************************************************************************
\r
1553 * Function Name : SetCKSYS_RTC
\r
1554 * Description : Selects RTC clock (CK_RTC) as CK_SYS clock source.
\r
1555 * Input : PLL_State: specifies the PLL state.
\r
1557 * Return : An ErrorStatus enumuration value:
\r
1558 * - SUCCESS: Clock configuration succeeded
\r
1559 * - ERROR: Clock configuration failed
\r
1560 *******************************************************************************/
\r
1561 static ErrorStatus SetCKSYS_RTC(u32 PLL_State)
\r
1563 /* Check if CK_RTC clock is enabled and ready to use */
\r
1564 if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)||
\r
1565 ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET))
\r
1567 /* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/
\r
1568 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET)
\r
1570 /* Select CK_PLL1 as CK_SYS clock source */
\r
1571 MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
\r
1573 /* Set CKOSCSEL bit ----------------------------------------------------*/
\r
1574 /* Execute CKOSCSEL bit writing sequence */
\r
1575 WriteCKOSCSELBit();
\r
1577 /* Check if CKOSCSEL is set to 1 */
\r
1578 if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET)
\r
1584 /* Select CK_OSC as CK_SYS clock source */
\r
1585 MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
\r
1587 if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)
\r
1589 if(PLL_State == MRCC_PLL_Disabled)
\r
1592 MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;
\r
1604 /* CK_RTC disabled */
\r
1609 /*******************************************************************************
\r
1610 * Function Name : WriteLPBit
\r
1611 * Description : Executes the Low Power bit writing sequence.
\r
1615 *******************************************************************************/
\r
1616 static void WriteLPBit(void)
\r
1618 u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0;
\r
1620 /* Clear LP_DONE flag */
\r
1621 MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask;
\r
1623 Tmp = MRCC->PWRCTRL;
\r
1624 Tmp1 = Tmp | MRCC_LP_Set_Mask;
\r
1625 Tmp2 = Tmp & MRCC_LP_Reset_Mask;
\r
1628 MRCC->PWRCTRL = Tmp1;
\r
1631 MRCC->PWRCTRL = Tmp1;
\r
1633 /* Reset LP bit */
\r
1634 MRCC->PWRCTRL = Tmp2;
\r
1637 MRCC->PWRCTRL = Tmp1;
\r
1640 Tmp = MRCC->PWRCTRL;
\r
1643 /*******************************************************************************
\r
1644 * Function Name : WriteCKOSCSELBit
\r
1645 * Description : Executes the CKOSCSEL bit writing sequence.
\r
1649 *******************************************************************************/
\r
1650 static void WriteCKOSCSELBit(void)
\r
1652 u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0;
\r
1654 Tmp = MRCC->CLKCTL;
\r
1655 Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask;
\r
1656 Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask;
\r
1658 /* Set CKOSCSEL bit */
\r
1659 MRCC->CLKCTL = Tmp1;
\r
1661 /* Set CKOSCSEL bit */
\r
1662 MRCC->CLKCTL = Tmp1;
\r
1664 /* Reset CKOSCSEL bit */
\r
1665 MRCC->CLKCTL = Tmp2;
\r
1667 /* Set CKOSCSEL bit */
\r
1668 MRCC->CLKCTL = Tmp1;
\r
1670 /* Read CKOSCSEL bit */
\r
1671 Tmp = MRCC->CLKCTL;
\r
1673 /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
\r