1 /* ----------------------------------------------------------------------------
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2 * ATMEL Microcontroller Software Support
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2008, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 //------------------------------------------------------------------------------
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35 /// Interface for configuration the Two Wire Interface (TWI) peripheral.
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39 /// -# Configures a TWI peripheral to operate in master mode, at the given
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40 /// frequency (in Hz) using TWI_Configure().
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41 /// -# Sends a STOP condition on the TWI using TWI_Stop().
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42 /// -# Starts a read operation on the TWI bus with the specified slave using
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43 /// TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever
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44 /// a byte is available (poll using TWI_ByteReceived()).
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45 /// -# Starts a write operation on the TWI to access the selected slave using
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46 /// TWI_StartWrite(). A byte of data must be provided to start the write;
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47 /// other bytes are written next.
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48 /// -# Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().
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49 /// This function must be called once before TWI_StartWrite() with the first byte of data
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50 /// to send, then it shall be called repeatedly after that to send the remaining bytes.
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51 /// -# Check if a byte has been received and can be read on the given TWI
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52 /// peripheral using TWI_ByteReceived().
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53 /// Check if a byte has been sent using TWI_ByteSent().
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54 /// -# Check if the current transmission is complete (the STOP has been sent)
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55 /// using TWI_TransferComplete().
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56 /// -# Enables & disable the selected interrupts sources on a TWI peripheral
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57 /// using TWI_EnableIt() and TWI_DisableIt().
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58 /// -# Get current status register of the given TWI peripheral using
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59 /// TWI_GetStatus(). Get current status register of the given TWI peripheral, but
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60 /// masking interrupt sources which are not currently enabled using
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61 /// TWI_GetMaskedStatus().
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62 //------------------------------------------------------------------------------
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65 //------------------------------------------------------------------------------
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67 //------------------------------------------------------------------------------
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70 #include <utility/math.h>
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71 #include <utility/assert.h>
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72 #include <utility/trace.h>
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74 //------------------------------------------------------------------------------
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76 //------------------------------------------------------------------------------
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78 //------------------------------------------------------------------------------
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79 /// Configures a TWI peripheral to operate in master mode, at the given
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80 /// frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
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81 /// \param pTwi Pointer to an AT91S_TWI instance.
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82 /// \param twck Desired TWI clock frequency.
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83 /// \param mck Master clock frequency.
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84 //------------------------------------------------------------------------------
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85 void TWI_ConfigureMaster(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck)
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87 unsigned int ckdiv = 0;
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89 unsigned char ok = 0;
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91 TRACE_DEBUG("TWI_ConfigureMaster()\n\r");
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94 #ifdef AT91C_TWI_SVEN // TWI slave
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95 // SVEN: TWI Slave Mode Enabled
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96 pTwi->TWI_CR = AT91C_TWI_SVEN;
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99 pTwi->TWI_CR = AT91C_TWI_SWRST;
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102 // TWI Slave Mode Disabled, TWI Master Mode Disabled
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103 #ifdef AT91C_TWI_SVEN // TWI slave
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104 pTwi->TWI_CR = AT91C_TWI_SVDIS;
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106 pTwi->TWI_CR = AT91C_TWI_MSDIS;
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109 pTwi->TWI_CR = AT91C_TWI_MSEN;
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113 cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);
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114 if (cldiv <= 255) {
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124 ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");
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125 TRACE_DEBUG("Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);
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126 pTwi->TWI_CWGR = 0;
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127 pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;
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132 #ifdef AT91C_TWI_SVEN // TWI slave
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133 //------------------------------------------------------------------------------
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134 /// Configures a TWI peripheral to operate in slave mode
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135 /// \param pTwi Pointer to an AT91S_TWI instance.
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136 //------------------------------------------------------------------------------
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137 void TWI_ConfigureSlave(AT91S_TWI *pTwi, unsigned char slaveAddress)
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141 // TWI software reset
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142 pTwi->TWI_CR = AT91C_TWI_SWRST;
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145 // Wait at least 10 ms
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146 for (i=0; i < 1000000; i++);
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148 // TWI Slave Mode Disabled, TWI Master Mode Disabled
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149 pTwi->TWI_CR = AT91C_TWI_SVDIS | AT91C_TWI_MSDIS;
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153 pTwi->TWI_SMR = (slaveAddress << 16) & AT91C_TWI_SADR;
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155 // SVEN: TWI Slave Mode Enabled
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156 pTwi->TWI_CR = AT91C_TWI_SVEN;
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158 // Wait at least 10 ms
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159 for (i=0; i < 1000000; i++);
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160 ASSERT( (pTwi->TWI_CR & AT91C_TWI_SVDIS)!=AT91C_TWI_SVDIS, "Problem slave mode");
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164 //------------------------------------------------------------------------------
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165 /// Sends a STOP condition on the TWI.
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166 /// \param pTwi Pointer to an AT91S_TWI instance.
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167 //------------------------------------------------------------------------------
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168 void TWI_Stop(AT91S_TWI *pTwi)
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170 SANITY_CHECK(pTwi);
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172 pTwi->TWI_CR = AT91C_TWI_STOP;
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175 //------------------------------------------------------------------------------
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176 /// Starts a read operation on the TWI bus with the specified slave, and returns
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177 /// immediately. Data must then be read using TWI_ReadByte() whenever a byte is
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178 /// available (poll using TWI_ByteReceived()).
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179 /// \param pTwi Pointer to an AT91S_TWI instance.
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180 /// \param address Slave address on the bus.
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181 /// \param iaddress Optional internal address bytes.
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182 /// \param isize Number of internal address bytes.
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183 //-----------------------------------------------------------------------------
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184 void TWI_StartRead(
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186 unsigned char address,
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187 unsigned int iaddress,
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188 unsigned char isize)
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190 //TRACE_DEBUG("TWI_StartRead()\n\r");
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191 SANITY_CHECK(pTwi);
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192 SANITY_CHECK((address & 0x80) == 0);
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193 SANITY_CHECK((iaddress & 0xFF000000) == 0);
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194 SANITY_CHECK(isize < 4);
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196 // Set slave address and number of internal address bytes
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198 pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16);
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200 // Set internal address bytes
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201 pTwi->TWI_IADR = 0;
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202 pTwi->TWI_IADR = iaddress;
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204 // Send START condition
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205 pTwi->TWI_CR = AT91C_TWI_START;
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208 //-----------------------------------------------------------------------------
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209 /// Reads a byte from the TWI bus. The read operation must have been started
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210 /// using TWI_StartRead() and a byte must be available (check with
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211 /// TWI_ByteReceived()).
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212 /// Returns the byte read.
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213 /// \param pTwi Pointer to an AT91S_TWI instance.
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214 //-----------------------------------------------------------------------------
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215 unsigned char TWI_ReadByte(AT91S_TWI *pTwi)
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217 SANITY_CHECK(pTwi);
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219 return pTwi->TWI_RHR;
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222 //-----------------------------------------------------------------------------
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223 /// Sends a byte of data to one of the TWI slaves on the bus. This function
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224 /// must be called once before TWI_StartWrite() with the first byte of data
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225 /// to send, then it shall be called repeatedly after that to send the
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226 /// remaining bytes.
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227 /// \param pTwi Pointer to an AT91S_TWI instance.
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228 /// \param byte Byte to send.
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229 //-----------------------------------------------------------------------------
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230 void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte)
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232 SANITY_CHECK(pTwi);
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234 pTwi->TWI_THR = byte;
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237 //-----------------------------------------------------------------------------
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238 /// Starts a write operation on the TWI to access the selected slave, then
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239 /// returns immediately. A byte of data must be provided to start the write;
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240 /// other bytes are written next.
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241 /// \param pTwi Pointer to an AT91S_TWI instance.
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242 /// \param address Address of slave to acccess on the bus.
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243 /// \param iaddress Optional slave internal address.
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244 /// \param isize Number of internal address bytes.
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245 /// \param byte First byte to send.
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246 //-----------------------------------------------------------------------------
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247 void TWI_StartWrite(
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249 unsigned char address,
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250 unsigned int iaddress,
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251 unsigned char isize,
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252 unsigned char byte)
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254 //TRACE_DEBUG("TWI_StartWrite()\n\r");
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255 SANITY_CHECK(pTwi);
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256 SANITY_CHECK((address & 0x80) == 0);
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257 SANITY_CHECK((iaddress & 0xFF000000) == 0);
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258 SANITY_CHECK(isize < 4);
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260 // Set slave address and number of internal address bytes
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262 pTwi->TWI_MMR = (isize << 8) | (address << 16);
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264 // Set internal address bytes
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265 pTwi->TWI_IADR = 0;
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266 pTwi->TWI_IADR = iaddress;
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268 // Write first byte to send
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269 TWI_WriteByte(pTwi, byte);
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272 //-----------------------------------------------------------------------------
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273 /// Returns 1 if a byte has been received and can be read on the given TWI
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274 /// peripheral; otherwise, returns 0. This function resets the status register
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276 /// \param pTwi Pointer to an AT91S_TWI instance.
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277 //-----------------------------------------------------------------------------
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278 unsigned char TWI_ByteReceived(AT91S_TWI *pTwi)
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280 return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY);
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283 //-----------------------------------------------------------------------------
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284 /// Returns 1 if a byte has been sent, so another one can be stored for
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285 /// transmission; otherwise returns 0. This function clears the status register
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287 /// \param pTwi Pointer to an AT91S_TWI instance.
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288 //-----------------------------------------------------------------------------
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289 unsigned char TWI_ByteSent(AT91S_TWI *pTwi)
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291 return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY);
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294 //-----------------------------------------------------------------------------
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295 /// Returns 1 if the current transmission is complete (the STOP has been sent);
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296 /// otherwise returns 0.
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297 /// \param pTwi Pointer to an AT91S_TWI instance.
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298 //-----------------------------------------------------------------------------
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299 unsigned char TWI_TransferComplete(AT91S_TWI *pTwi)
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301 return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP);
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304 //-----------------------------------------------------------------------------
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305 /// Enables the selected interrupts sources on a TWI peripheral.
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306 /// \param pTwi Pointer to an AT91S_TWI instance.
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307 /// \param sources Bitwise OR of selected interrupt sources.
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308 //-----------------------------------------------------------------------------
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309 void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources)
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311 SANITY_CHECK(pTwi);
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312 SANITY_CHECK((sources & 0xFFFFF088) == 0);
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314 pTwi->TWI_IER = sources;
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317 //-----------------------------------------------------------------------------
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318 /// Disables the selected interrupts sources on a TWI peripheral.
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319 /// \param pTwi Pointer to an AT91S_TWI instance.
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320 /// \param sources Bitwise OR of selected interrupt sources.
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321 //-----------------------------------------------------------------------------
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322 void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources)
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324 SANITY_CHECK(pTwi);
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325 SANITY_CHECK((sources & 0xFFFFF088) == 0);
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327 pTwi->TWI_IDR = sources;
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330 //-----------------------------------------------------------------------------
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331 /// Returns the current status register of the given TWI peripheral. This
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332 /// resets the internal value of the status register, so further read may yield
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333 /// different values.
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334 /// \param pTwi Pointer to an AT91S_TWI instance.
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335 //-----------------------------------------------------------------------------
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336 unsigned int TWI_GetStatus(AT91S_TWI *pTwi)
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338 SANITY_CHECK(pTwi);
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340 return pTwi->TWI_SR;
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343 //-----------------------------------------------------------------------------
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344 /// Returns the current status register of the given TWI peripheral, but
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345 /// masking interrupt sources which are not currently enabled.
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346 /// This resets the internal value of the status register, so further read may
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347 /// yield different values.
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348 /// \param pTwi Pointer to an AT91S_TWI instance.
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349 //-----------------------------------------------------------------------------
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350 unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi)
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352 unsigned int status;
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354 SANITY_CHECK(pTwi);
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356 status = pTwi->TWI_SR;
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357 status &= pTwi->TWI_IMR;
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361 //-----------------------------------------------------------------------------
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362 /// Sends a STOP condition. STOP Condition is sent just after completing
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363 /// the current byte transmission in master read mode.
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364 /// \param pTwi Pointer to an AT91S_TWI instance.
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365 //-----------------------------------------------------------------------------
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366 void TWI_SendSTOPCondition(AT91S_TWI *pTwi)
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368 SANITY_CHECK(pTwi);
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370 pTwi->TWI_CR |= AT91C_TWI_STOP;
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