1 //*****************************************************************************
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3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 523 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_WATCHDOG_H__
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29 #define __HW_WATCHDOG_H__
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31 //*****************************************************************************
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33 // The following define the offsets of the Watchdog Timer registers.
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35 //*****************************************************************************
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36 #define WDT_O_LOAD 0x00000000 // Load register
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37 #define WDT_O_VALUE 0x00000004 // Current value register
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38 #define WDT_O_CTL 0x00000008 // Control register
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39 #define WDT_O_ICR 0x0000000C // Interrupt clear register
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40 #define WDT_O_RIS 0x00000010 // Raw interrupt status register
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41 #define WDT_O_MIS 0x00000014 // Masked interrupt status register
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42 #define WDT_O_TEST 0x00000418 // Test register
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43 #define WDT_O_CAUSE 0x0000041C // Cause register
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44 #define WDT_O_LOCK 0x00000C00 // Lock register
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46 //*****************************************************************************
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48 // The following define the bit fields in the WDT_CTL register.
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50 //*****************************************************************************
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51 #define WDT_CTL_RESEN 0x00000002 // Enable reset output
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52 #define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
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54 //*****************************************************************************
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56 // The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
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59 //*****************************************************************************
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60 #define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
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62 //*****************************************************************************
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64 // The following define the bit fields in the WDT_TEST register.
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66 //*****************************************************************************
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67 #define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
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68 #define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test
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70 //*****************************************************************************
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72 // The following define the bit fields in the WDT_CAUSE register.
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74 //*****************************************************************************
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75 #define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred
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76 #define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred
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78 //*****************************************************************************
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80 // The following define the bit fields in the WDT_LOCK register.
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82 //*****************************************************************************
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83 #define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
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84 #define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
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85 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
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87 //*****************************************************************************
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89 // The following define the reset values for the WDT registers.
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91 //*****************************************************************************
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92 #define WDT_RV_LOAD 0xFFFFFFFF // Load register
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93 #define WDT_RV_VALUE 0xFFFFFFFF // Current value register
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94 #define WDT_RV_CTL 0x00000000 // Control register
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95 #define WDT_RV_RIS 0x00000000 // Raw interrupt status register
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96 #define WDT_RV_MIS 0x00000000 // Masked interrupt status register
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97 #define WDT_RV_LOCK 0x00000000 // Lock register
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99 #endif // __HW_WATCHDOG_H__
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