1 //*****************************************************************************
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3 // watchdog.c - Driver for the Watchdog Timer Module.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup watchdog_api
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33 //*****************************************************************************
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35 #include "../hw_ints.h"
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36 #include "../hw_memmap.h"
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37 #include "../hw_types.h"
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38 #include "../hw_watchdog.h"
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40 #include "interrupt.h"
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41 #include "watchdog.h"
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43 //*****************************************************************************
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45 //! Determines if the watchdog timer is enabled.
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47 //! \param ulBase is the base address of the watchdog timer module.
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49 //! This will check to see if the watchdog timer is enabled.
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51 //! \return Returns \b true if the watchdog timer is enabled, and \b false
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54 //*****************************************************************************
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55 #if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN)
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57 WatchdogRunning(unsigned long ulBase)
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60 // Check the arguments.
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62 ASSERT(ulBase == WATCHDOG_BASE);
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65 // See if the watchdog timer module is enabled, and return.
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67 return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
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71 //*****************************************************************************
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73 //! Enables the watchdog timer.
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75 //! \param ulBase is the base address of the watchdog timer module.
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77 //! This will enable the watchdog timer counter and interrupt.
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79 //! \note This function will have no effect if the watchdog timer has
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82 //! \sa WatchdogLock(), WatchdogUnlock()
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86 //*****************************************************************************
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87 #if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
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89 WatchdogEnable(unsigned long ulBase)
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92 // Check the arguments.
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94 ASSERT(ulBase == WATCHDOG_BASE);
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97 // Enable the watchdog timer module.
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99 HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
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103 //*****************************************************************************
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105 //! Enables the watchdog timer reset.
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107 //! \param ulBase is the base address of the watchdog timer module.
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109 //! Enables the capability of the watchdog timer to issue a reset to the
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110 //! processor upon a second timeout condition.
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112 //! \note This function will have no effect if the watchdog timer has
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115 //! \sa WatchdogLock(), WatchdogUnlock()
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119 //*****************************************************************************
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120 #if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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122 WatchdogResetEnable(unsigned long ulBase)
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125 // Check the arguments.
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127 ASSERT(ulBase == WATCHDOG_BASE);
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130 // Enable the watchdog reset.
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132 HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
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136 //*****************************************************************************
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138 //! Disables the watchdog timer reset.
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140 //! \param ulBase is the base address of the watchdog timer module.
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142 //! Disables the capability of the watchdog timer to issue a reset to the
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143 //! processor upon a second timeout condition.
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145 //! \note This function will have no effect if the watchdog timer has
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148 //! \sa WatchdogLock(), WatchdogUnlock()
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152 //*****************************************************************************
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153 #if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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155 WatchdogResetDisable(unsigned long ulBase)
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158 // Check the arguments.
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160 ASSERT(ulBase == WATCHDOG_BASE);
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163 // Disable the watchdog reset.
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165 HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
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169 //*****************************************************************************
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171 //! Enables the watchdog timer lock mechanism.
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173 //! \param ulBase is the base address of the watchdog timer module.
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175 //! Locks out write access to the watchdog timer configuration registers.
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179 //*****************************************************************************
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180 #if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN)
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182 WatchdogLock(unsigned long ulBase)
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185 // Check the arguments.
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187 ASSERT(ulBase == WATCHDOG_BASE);
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190 // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
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191 // register causes the lock to go into effect.
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193 HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
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197 //*****************************************************************************
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199 //! Disables the watchdog timer lock mechanism.
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201 //! \param ulBase is the base address of the watchdog timer module.
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203 //! Enables write access to the watchdog timer configuration registers.
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207 //*****************************************************************************
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208 #if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN)
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210 WatchdogUnlock(unsigned long ulBase)
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213 // Check the arguments.
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215 ASSERT(ulBase == WATCHDOG_BASE);
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218 // Unlock watchdog register writes.
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220 HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
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224 //*****************************************************************************
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226 //! Gets the state of the watchdog timer lock mechanism.
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228 //! \param ulBase is the base address of the watchdog timer module.
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230 //! Returns the lock state of the watchdog timer registers.
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232 //! \return Returns \b true if the watchdog timer registers are locked, and
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233 //! \b false if they are not locked.
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235 //*****************************************************************************
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236 #if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN)
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238 WatchdogLockState(unsigned long ulBase)
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241 // Check the arguments.
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243 ASSERT(ulBase == WATCHDOG_BASE);
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246 // Get the lock state.
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248 return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
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252 //*****************************************************************************
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254 //! Sets the watchdog timer reload value.
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256 //! \param ulBase is the base address of the watchdog timer module.
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257 //! \param ulLoadVal is the load value for the watchdog timer.
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259 //! This function sets the value to load into the watchdog timer when the count
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260 //! reaches zero for the first time; if the watchdog timer is running when this
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261 //! function is called, then the value will be immediately loaded into the
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262 //! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an
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263 //! interrupt is immediately generated.
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265 //! \note This function will have no effect if the watchdog timer has
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268 //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
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272 //*****************************************************************************
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273 #if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN)
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275 WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
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278 // Check the arguments.
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280 ASSERT(ulBase == WATCHDOG_BASE);
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283 // Set the load register.
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285 HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
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289 //*****************************************************************************
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291 //! Gets the watchdog timer reload value.
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293 //! \param ulBase is the base address of the watchdog timer module.
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295 //! This function gets the value that is loaded into the watchdog timer when
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296 //! the count reaches zero for the first time.
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298 //! \sa WatchdogReloadSet()
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302 //*****************************************************************************
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303 #if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN)
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305 WatchdogReloadGet(unsigned long ulBase)
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308 // Check the arguments.
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310 ASSERT(ulBase == WATCHDOG_BASE);
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313 // Get the load register.
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315 return(HWREG(ulBase + WDT_O_LOAD));
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319 //*****************************************************************************
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321 //! Gets the current watchdog timer value.
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323 //! \param ulBase is the base address of the watchdog timer module.
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325 //! This function reads the current value of the watchdog timer.
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327 //! \return Returns the current value of the watchdog timer.
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329 //*****************************************************************************
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330 #if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)
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332 WatchdogValueGet(unsigned long ulBase)
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335 // Check the arguments.
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337 ASSERT(ulBase == WATCHDOG_BASE);
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340 // Get the current watchdog timer register value.
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342 return(HWREG(ulBase + WDT_O_VALUE));
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346 //*****************************************************************************
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348 //! Registers an interrupt handler for watchdog timer interrupt.
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350 //! \param ulBase is the base address of the watchdog timer module.
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351 //! \param pfnHandler is a pointer to the function to be called when the
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352 //! watchdog timer interrupt occurs.
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354 //! This function does the actual registering of the interrupt handler. This
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355 //! will enable the global interrupt in the interrupt controller; the watchdog
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356 //! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
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357 //! handler's responsibility to clear the interrupt source via
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358 //! WatchdogIntClear().
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360 //! \sa IntRegister() for important information about registering interrupt
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365 //*****************************************************************************
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366 #if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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368 WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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371 // Check the arguments.
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373 ASSERT(ulBase == WATCHDOG_BASE);
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376 // Register the interrupt handler.
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378 IntRegister(INT_WATCHDOG, pfnHandler);
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381 // Enable the watchdog timer interrupt.
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383 IntEnable(INT_WATCHDOG);
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387 //*****************************************************************************
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389 //! Unregisters an interrupt handler for the watchdog timer interrupt.
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391 //! \param ulBase is the base address of the watchdog timer module.
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393 //! This function does the actual unregistering of the interrupt handler. This
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394 //! function will clear the handler to be called when a watchdog timer
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395 //! interrupt occurs. This will also mask off the interrupt in the interrupt
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396 //! controller so that the interrupt handler no longer is called.
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398 //! \sa IntRegister() for important information about registering interrupt
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403 //*****************************************************************************
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404 #if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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406 WatchdogIntUnregister(unsigned long ulBase)
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409 // Check the arguments.
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411 ASSERT(ulBase == WATCHDOG_BASE);
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414 // Disable the interrupt.
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416 IntDisable(INT_WATCHDOG);
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419 // Unregister the interrupt handler.
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421 IntUnregister(INT_WATCHDOG);
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425 //*****************************************************************************
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427 //! Enables the watchdog timer interrupt.
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429 //! \param ulBase is the base address of the watchdog timer module.
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431 //! Enables the watchdog timer interrupt.
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433 //! \note This function will have no effect if the watchdog timer has
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436 //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
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440 //*****************************************************************************
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441 #if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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443 WatchdogIntEnable(unsigned long ulBase)
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446 // Check the arguments.
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448 ASSERT(ulBase == WATCHDOG_BASE);
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451 // Enable the watchdog interrupt.
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453 HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
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457 //*****************************************************************************
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459 //! Gets the current watchdog timer interrupt status.
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461 //! \param ulBase is the base address of the watchdog timer module.
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462 //! \param bMasked is \b false if the raw interrupt status is required and
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463 //! \b true if the masked interrupt status is required.
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465 //! This returns the interrupt status for the watchdog timer module. Either
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466 //! the raw interrupt status or the status of interrupt that is allowed to
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467 //! reflect to the processor can be returned.
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469 //! \return The current interrupt status, where a 1 indicates that the watchdog
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470 //! interrupt is active, and a 0 indicates that it is not active.
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472 //*****************************************************************************
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473 #if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
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475 WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
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478 // Check the arguments.
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480 ASSERT(ulBase == WATCHDOG_BASE);
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483 // Return either the interrupt status or the raw interrupt status as
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488 return(HWREG(ulBase + WDT_O_MIS));
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492 return(HWREG(ulBase + WDT_O_RIS));
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497 //*****************************************************************************
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499 //! Clears the watchdog timer interrupt.
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501 //! \param ulBase is the base address of the watchdog timer module.
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503 //! The watchdog timer interrupt source is cleared, so that it no longer
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508 //*****************************************************************************
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509 #if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
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511 WatchdogIntClear(unsigned long ulBase)
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514 // Check the arguments.
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516 ASSERT(ulBase == WATCHDOG_BASE);
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519 // Clear the interrupt source.
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521 HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
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525 //*****************************************************************************
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527 //! Enables stalling of the watchdog timer during debug events.
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529 //! \param ulBase is the base address of the watchdog timer module.
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531 //! This function allows the watchdog timer to stop counting when the processor
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532 //! is stopped by the debugger. By doing so, the watchdog is prevented from
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533 //! expiring (typically almost immediately from a human time perspective) and
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534 //! resetting the system (if reset is enabled). The watchdog will instead
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535 //! expired after the appropriate number of processor cycles have been executed
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536 //! while debugging (or at the appropriate time after the processor has been
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541 //*****************************************************************************
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542 #if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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544 WatchdogStallEnable(unsigned long ulBase)
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547 // Check the arguments.
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549 ASSERT(ulBase == WATCHDOG_BASE);
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552 // Enable timer stalling.
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554 HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
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558 //*****************************************************************************
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560 //! Disables stalling of the watchdog timer during debug events.
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562 //! \param ulBase is the base address of the watchdog timer module.
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564 //! This function disables the debug mode stall of the watchdog timer. By
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565 //! doing so, the watchdog timer continues to count regardless of the processor
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570 //*****************************************************************************
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571 #if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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573 WatchdogStallDisable(unsigned long ulBase)
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576 // Check the arguments.
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578 ASSERT(ulBase == WATCHDOG_BASE);
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581 // Disable timer stalling.
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583 HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
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587 //*****************************************************************************
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589 // Close the Doxygen group.
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592 //*****************************************************************************
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