2 ******************************************************************************
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3 * @file stm32f0xx_tim.c
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4 * @author MCD Application Team
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6 * @date 27-January-2012
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7 * @brief This file provides firmware functions to manage the following
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8 * functionalities of the TIM peripheral:
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9 * + TimeBase management
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10 * + Output Compare management
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11 * + Input Capture management
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12 * + Interrupts, DMA and flags management
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13 * + Clocks management
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14 * + Synchronization management
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15 * + Specific interface management
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16 * + Specific remapping management
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20 ===============================================================================
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21 ##### How to use this driver #####
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22 ===============================================================================
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23 [..] This driver provides functions to configure and program the TIM
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24 of all STM32F0xx devices These functions are split in 8 groups:
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25 (#) TIM TimeBase management: this group includes all needed functions
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26 to configure the TM Timebase unit:
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27 (++) Set/Get Prescaler.
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28 (++) Set/Get Autoreload.
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29 (++) Counter modes configuration.
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30 (++) Set Clock division.
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31 (++) Select the One Pulse mode.
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32 (++) Update Request Configuration.
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33 (++) Update Disable Configuration.
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34 (++) Auto-Preload Configuration.
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35 (++) Enable/Disable the counter.
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37 (#) TIM Output Compare management: this group includes all needed
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38 functions to configure the Capture/Compare unit used in Output
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40 (++) Configure each channel, independently, in Output Compare mode.
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41 (++) Select the output compare modes.
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42 (++) Select the Polarities of each channel.
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43 (++) Set/Get the Capture/Compare register values.
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44 (++) Select the Output Compare Fast mode.
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45 (++) Select the Output Compare Forced mode.
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46 (++) Output Compare-Preload Configuration.
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47 (++) Clear Output Compare Reference.
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48 (++) Select the OCREF Clear signal.
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49 (++) Enable/Disable the Capture/Compare Channels.
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51 (#) TIM Input Capture management: this group includes all needed
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52 functions to configure the Capture/Compare unit used in
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54 (++) Configure each channel in input capture mode.
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55 (++) Configure Channel1/2 in PWM Input mode.
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56 (++) Set the Input Capture Prescaler.
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57 (++) Get the Capture/Compare values.
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59 (#) Advanced-control timers (TIM1) specific features
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60 (++) Configures the Break input, dead time, Lock level, the OSSI,
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61 the OSSR State and the AOE(automatic output enable)
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62 (++) Enable/Disable the TIM peripheral Main Outputs
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63 (++) Select the Commutation event
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64 (++) Set/Reset the Capture Compare Preload Control bit
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66 (#) TIM interrupts, DMA and flags management.
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67 (++) Enable/Disable interrupt sources.
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68 (++) Get flags status.
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69 (++) Clear flags/ Pending bits.
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70 (++) Enable/Disable DMA requests.
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71 (++) Configure DMA burst mode.
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72 (++) Select CaptureCompare DMA request.
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74 (#) TIM clocks management: this group includes all needed functions
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75 to configure the clock controller unit:
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76 (++) Select internal/External clock.
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77 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
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79 (#) TIM synchronization management: this group includes all needed.
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80 functions to configure the Synchronization unit:
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81 (++) Select Input Trigger.
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82 (++) Select Output Trigger.
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83 (++) Select Master Slave Mode.
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84 (++) ETR Configuration when used as external trigger.
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86 (#) TIM specific interface management, this group includes all
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87 needed functions to use the specific TIM interface:
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88 (++) Encoder Interface Configuration.
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89 (++) Select Hall Sensor.
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91 (#) TIM specific remapping management includes the Remapping
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92 configuration of specific timers
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96 ******************************************************************************
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99 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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100 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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101 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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102 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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103 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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104 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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106 * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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107 * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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109 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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110 ******************************************************************************
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113 /* Includes ------------------------------------------------------------------*/
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114 #include "stm32f0xx_tim.h"
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115 #include "stm32f0xx_rcc.h"
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117 /** @addtogroup STM32F0xx_StdPeriph_Driver
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122 * @brief TIM driver modules
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126 /* Private typedef -----------------------------------------------------------*/
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127 /* Private define ------------------------------------------------------------*/
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129 /* ---------------------- TIM registers bit mask ------------------------ */
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130 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
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131 #define CCMR_OFFSET ((uint16_t)0x0018)
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132 #define CCER_CCE_SET ((uint16_t)0x0001)
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133 #define CCER_CCNE_SET ((uint16_t)0x0004)
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135 /* Private macro -------------------------------------------------------------*/
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136 /* Private variables ---------------------------------------------------------*/
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137 /* Private function prototypes -----------------------------------------------*/
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139 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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140 uint16_t TIM_ICFilter);
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141 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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142 uint16_t TIM_ICFilter);
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143 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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144 uint16_t TIM_ICFilter);
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145 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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146 uint16_t TIM_ICFilter);
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147 /* Private functions ---------------------------------------------------------*/
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149 /** @defgroup TIM_Private_Functions
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153 /** @defgroup TIM_Group1 TimeBase management functions
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154 * @brief TimeBase management functions
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157 ===============================================================================
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158 ##### TimeBase management functions #####
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159 ===============================================================================
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161 *** TIM Driver: how to use it in Timing(Time base) Mode ***
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162 ===============================================================================
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163 [..] To use the Timer in Timing(Time base) mode, the following steps are
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165 (#) Enable TIM clock using
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166 RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
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167 (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
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168 (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
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169 the Time Base unit with the corresponding configuration.
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170 (#) Enable the NVIC if you need to generate the update interrupt.
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171 (#) Enable the corresponding interrupt using the function
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172 TIM_ITConfig(TIMx, TIM_IT_Update).
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173 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
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175 (@) All other functions can be used seperatly to modify, if needed,
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176 a specific feature of the Timer.
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183 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
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184 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
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188 void TIM_DeInit(TIM_TypeDef* TIMx)
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190 /* Check the parameters */
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191 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
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196 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
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198 else if (TIMx == TIM2)
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200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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201 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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203 else if (TIMx == TIM3)
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205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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206 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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208 else if (TIMx == TIM6)
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210 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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213 else if (TIMx == TIM14)
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215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
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216 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
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218 else if (TIMx == TIM15)
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220 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
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221 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
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223 else if (TIMx == TIM16)
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225 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
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226 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
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232 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
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233 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
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240 * @brief Initializes the TIMx Time Base Unit peripheral according to
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241 * the specified parameters in the TIM_TimeBaseInitStruct.
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242 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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244 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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245 * structure that contains the configuration information for
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246 * the specified TIM peripheral.
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249 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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251 uint16_t tmpcr1 = 0;
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253 /* Check the parameters */
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254 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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255 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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256 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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258 tmpcr1 = TIMx->CR1;
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260 if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))
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262 /* Select the Counter Mode */
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263 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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264 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
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269 /* Set the clock division */
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270 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
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271 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
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274 TIMx->CR1 = tmpcr1;
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276 /* Set the Autoreload value */
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277 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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279 /* Set the Prescaler value */
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280 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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282 if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
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284 /* Set the Repetition Counter value */
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285 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
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288 /* Generate an update event to reload the Prescaler and the Repetition counter
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289 values immediately */
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290 TIMx->EGR = TIM_PSCReloadMode_Immediate;
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294 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
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295 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
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296 * structure which will be initialized.
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299 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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301 /* Set the default configuration */
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302 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
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303 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
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304 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
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305 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
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306 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
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310 * @brief Configures the TIMx Prescaler.
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311 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
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312 * @param Prescaler: specifies the Prescaler Register value
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313 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
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314 * This parameter can be one of the following values:
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315 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
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316 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
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319 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
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321 /* Check the parameters */
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322 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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323 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
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325 /* Set the Prescaler value */
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326 TIMx->PSC = Prescaler;
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327 /* Set or reset the UG Bit */
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328 TIMx->EGR = TIM_PSCReloadMode;
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332 * @brief Specifies the TIMx Counter Mode to be used.
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333 * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.
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334 * @param TIM_CounterMode: specifies the Counter Mode to be used
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335 * This parameter can be one of the following values:
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336 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
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337 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
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338 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
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339 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
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340 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
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343 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
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345 uint16_t tmpcr1 = 0;
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347 /* Check the parameters */
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348 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
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349 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
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351 tmpcr1 = TIMx->CR1;
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352 /* Reset the CMS and DIR Bits */
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353 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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354 /* Set the Counter Mode */
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355 tmpcr1 |= TIM_CounterMode;
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356 /* Write to TIMx CR1 register */
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357 TIMx->CR1 = tmpcr1;
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361 * @brief Sets the TIMx Counter Register value
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362 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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364 * @param Counter: specifies the Counter register new value.
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367 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
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369 /* Check the parameters */
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370 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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372 /* Set the Counter Register value */
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373 TIMx->CNT = Counter;
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377 * @brief Sets the TIMx Autoreload Register value
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378 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
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379 * @param Autoreload: specifies the Autoreload register new value.
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382 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
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384 /* Check the parameters */
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385 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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387 /* Set the Autoreload Register value */
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388 TIMx->ARR = Autoreload;
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392 * @brief Gets the TIMx Counter value.
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393 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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395 * @retval Counter Register value.
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397 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
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399 /* Check the parameters */
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400 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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402 /* Get the Counter Register value */
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407 * @brief Gets the TIMx Prescaler value.
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408 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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410 * @retval Prescaler Register value.
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412 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
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414 /* Check the parameters */
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415 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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417 /* Get the Prescaler Register value */
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422 * @brief Enables or Disables the TIMx Update event.
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423 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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425 * @param NewState: new state of the TIMx UDIS bit
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426 * This parameter can be: ENABLE or DISABLE.
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429 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
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431 /* Check the parameters */
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432 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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433 assert_param(IS_FUNCTIONAL_STATE(NewState));
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435 if (NewState != DISABLE)
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437 /* Set the Update Disable Bit */
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438 TIMx->CR1 |= TIM_CR1_UDIS;
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442 /* Reset the Update Disable Bit */
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443 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
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448 * @brief Configures the TIMx Update Request Interrupt source.
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449 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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451 * @param TIM_UpdateSource: specifies the Update source.
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452 * This parameter can be one of the following values:
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453 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
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454 or the setting of UG bit, or an update generation
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455 through the slave mode controller.
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456 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
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459 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
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461 /* Check the parameters */
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462 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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463 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
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465 if (TIM_UpdateSource != TIM_UpdateSource_Global)
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467 /* Set the URS Bit */
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468 TIMx->CR1 |= TIM_CR1_URS;
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472 /* Reset the URS Bit */
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473 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
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478 * @brief Enables or disables TIMx peripheral Preload register on ARR.
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479 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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481 * @param NewState: new state of the TIMx peripheral Preload register
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482 * This parameter can be: ENABLE or DISABLE.
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485 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
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487 /* Check the parameters */
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488 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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489 assert_param(IS_FUNCTIONAL_STATE(NewState));
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491 if (NewState != DISABLE)
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493 /* Set the ARR Preload Bit */
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494 TIMx->CR1 |= TIM_CR1_ARPE;
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498 /* Reset the ARR Preload Bit */
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499 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
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504 * @brief Selects the TIMx's One Pulse Mode.
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505 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM
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507 * @param TIM_OPMode: specifies the OPM Mode to be used.
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508 * This parameter can be one of the following values:
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509 * @arg TIM_OPMode_Single
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510 * @arg TIM_OPMode_Repetitive
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513 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
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515 /* Check the parameters */
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516 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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517 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
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519 /* Reset the OPM Bit */
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520 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
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521 /* Configure the OPM Mode */
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522 TIMx->CR1 |= TIM_OPMode;
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526 * @brief Sets the TIMx Clock Division value.
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527 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
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528 * @param TIM_CKD: specifies the clock division value.
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529 * This parameter can be one of the following value:
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530 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
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531 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
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532 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
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535 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
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537 /* Check the parameters */
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538 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
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539 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
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541 /* Reset the CKD Bits */
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542 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
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543 /* Set the CKD value */
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544 TIMx->CR1 |= TIM_CKD;
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548 * @brief Enables or disables the specified TIM peripheral.
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549 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17to select the TIMx
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551 * @param NewState: new state of the TIMx peripheral.
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552 * This parameter can be: ENABLE or DISABLE.
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555 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
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557 /* Check the parameters */
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558 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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559 assert_param(IS_FUNCTIONAL_STATE(NewState));
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561 if (NewState != DISABLE)
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563 /* Enable the TIM Counter */
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564 TIMx->CR1 |= TIM_CR1_CEN;
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568 /* Disable the TIM Counter */
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569 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
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577 /** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features
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578 * @brief Advanced-control timers (TIM1) specific features
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581 ===============================================================================
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582 ##### Advanced-control timers (TIM1) specific features #####
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583 ===============================================================================
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585 ===================================================================
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586 *** TIM Driver: how to use the Break feature ***
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587 ===================================================================
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588 [..] After configuring the Timer channel(s) in the appropriate Output Compare mode:
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590 (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
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591 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
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592 AOE(automatic output enable).
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594 (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
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596 (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
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598 (#) Once the break even occurs, the Timer's output signals are put in reset
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599 state or in a known state (according to the configuration made in
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600 TIM_BDTRConfig() function).
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606 * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
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607 * the OSSR State and the AOE(automatic output enable).
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608 * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM
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609 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
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610 * contains the BDTR Register configuration information for the TIM peripheral.
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613 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
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615 /* Check the parameters */
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616 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
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617 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
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618 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
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619 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
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620 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
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621 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
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622 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
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623 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
\r
624 the OSSI State, the dead time value and the Automatic Output Enable Bit */
\r
625 TIMx->BDTR |= (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
\r
626 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
\r
627 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
\r
628 TIM_BDTRInitStruct->TIM_AutomaticOutput;
\r
632 * @brief Fills each TIM_BDTRInitStruct member with its default value.
\r
633 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
\r
634 * will be initialized.
\r
637 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
\r
639 /* Set the default configuration */
\r
640 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
\r
641 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
\r
642 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
\r
643 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
\r
644 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
\r
645 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
\r
646 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
\r
650 * @brief Enables or disables the TIM peripheral Main Outputs.
\r
651 * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.
\r
652 * @param NewState: new state of the TIM peripheral Main Outputs.
\r
653 * This parameter can be: ENABLE or DISABLE.
\r
656 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
658 /* Check the parameters */
\r
659 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
660 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
661 if (NewState != DISABLE)
\r
663 /* Enable the TIM Main Output */
\r
664 TIMx->BDTR |= TIM_BDTR_MOE;
\r
668 /* Disable the TIM Main Output */
\r
669 TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
\r
677 /** @defgroup TIM_Group3 Output Compare management functions
\r
678 * @brief Output Compare management functions
\r
681 ===============================================================================
\r
682 ##### Output Compare management functions #####
\r
683 ===============================================================================
\r
684 *** TIM Driver: how to use it in Output Compare Mode ***
\r
685 ===============================================================================
\r
686 [..] To use the Timer in Output Compare mode, the following steps are mandatory:
\r
687 (#) Enable TIM clock using
\r
688 RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
\r
689 (#) Configure the TIM pins by configuring the corresponding GPIO pins
\r
690 (#) Configure the Time base unit as described in the first part of this
\r
691 driver, if needed, else the Timer will run with the default
\r
693 (++) Autoreload value = 0xFFFF.
\r
694 (++) Prescaler value = 0x0000.
\r
695 (++) Counter mode = Up counting.
\r
696 (++) Clock Division = TIM_CKD_DIV1.
\r
697 (#) Fill the TIM_OCInitStruct with the desired parameters including:
\r
698 (++) The TIM Output Compare mode: TIM_OCMode.
\r
699 (++) TIM Output State: TIM_OutputState.
\r
700 (++) TIM Pulse value: TIM_Pulse.
\r
701 (++) TIM Output Compare Polarity : TIM_OCPolarity.
\r
702 (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
\r
703 channel with the corresponding configuration.
\r
704 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
\r
706 (@) All other functions can be used separately to modify, if needed,
\r
707 a specific feature of the Timer.
\r
708 (@) In case of PWM mode, this function is mandatory:
\r
709 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
\r
710 (@) If the corresponding interrupt or DMA request are needed, the user should:
\r
711 (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
\r
712 (#@) Enable the corresponding interrupt (or DMA request) using the function
\r
713 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
\r
720 * @brief Initializes the TIMx Channel1 according to the specified
\r
721 * parameters in the TIM_OCInitStruct.
\r
722 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
\r
723 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
724 * that contains the configuration information for the specified TIM
\r
728 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
730 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\r
732 /* Check the parameters */
\r
733 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
734 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
735 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
736 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
737 /* Disable the Channel 1: Reset the CC1E Bit */
\r
738 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
\r
739 /* Get the TIMx CCER register value */
\r
740 tmpccer = TIMx->CCER;
\r
741 /* Get the TIMx CR2 register value */
\r
742 tmpcr2 = TIMx->CR2;
\r
744 /* Get the TIMx CCMR1 register value */
\r
745 tmpccmrx = TIMx->CCMR1;
\r
747 /* Reset the Output Compare Mode Bits */
\r
748 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
\r
749 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
\r
751 /* Select the Output Compare Mode */
\r
752 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\r
754 /* Reset the Output Polarity level */
\r
755 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
\r
756 /* Set the Output Compare Polarity */
\r
757 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
\r
759 /* Set the Output State */
\r
760 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
\r
762 if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
\r
764 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
\r
765 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
\r
766 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
\r
767 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
769 /* Reset the Output N Polarity level */
\r
770 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
\r
771 /* Set the Output N Polarity */
\r
772 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
\r
774 /* Reset the Output N State */
\r
775 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
\r
776 /* Set the Output N State */
\r
777 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
\r
779 /* Reset the Ouput Compare and Output Compare N IDLE State */
\r
780 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
\r
781 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
\r
783 /* Set the Output Idle state */
\r
784 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
\r
785 /* Set the Output N Idle state */
\r
786 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
\r
788 /* Write to TIMx CR2 */
\r
789 TIMx->CR2 = tmpcr2;
\r
791 /* Write to TIMx CCMR1 */
\r
792 TIMx->CCMR1 = tmpccmrx;
\r
794 /* Set the Capture Compare Register value */
\r
795 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\r
797 /* Write to TIMx CCER */
\r
798 TIMx->CCER = tmpccer;
\r
802 * @brief Initializes the TIMx Channel2 according to the specified
\r
803 * parameters in the TIM_OCInitStruct.
\r
804 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
805 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
806 * that contains the configuration information for the specified TIM
\r
810 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
812 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\r
814 /* Check the parameters */
\r
815 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
816 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
817 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
818 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
819 /* Disable the Channel 2: Reset the CC2E Bit */
\r
820 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
\r
822 /* Get the TIMx CCER register value */
\r
823 tmpccer = TIMx->CCER;
\r
824 /* Get the TIMx CR2 register value */
\r
825 tmpcr2 = TIMx->CR2;
\r
827 /* Get the TIMx CCMR1 register value */
\r
828 tmpccmrx = TIMx->CCMR1;
\r
830 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
831 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
\r
832 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
\r
834 /* Select the Output Compare Mode */
\r
835 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
837 /* Reset the Output Polarity level */
\r
838 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
\r
839 /* Set the Output Compare Polarity */
\r
840 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
\r
842 /* Set the Output State */
\r
843 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
\r
847 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
\r
848 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
\r
849 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
\r
850 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
852 /* Reset the Output N Polarity level */
\r
853 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
\r
854 /* Set the Output N Polarity */
\r
855 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
\r
857 /* Reset the Output N State */
\r
858 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
\r
859 /* Set the Output N State */
\r
860 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
\r
862 /* Reset the Ouput Compare and Output Compare N IDLE State */
\r
863 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
\r
864 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
\r
866 /* Set the Output Idle state */
\r
867 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
\r
868 /* Set the Output N Idle state */
\r
869 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
\r
871 /* Write to TIMx CR2 */
\r
872 TIMx->CR2 = tmpcr2;
\r
874 /* Write to TIMx CCMR1 */
\r
875 TIMx->CCMR1 = tmpccmrx;
\r
877 /* Set the Capture Compare Register value */
\r
878 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\r
880 /* Write to TIMx CCER */
\r
881 TIMx->CCER = tmpccer;
\r
885 * @brief Initializes the TIMx Channel3 according to the specified
\r
886 * parameters in the TIM_OCInitStruct.
\r
887 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
888 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
889 * that contains the configuration information for the specified TIM
\r
893 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
895 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\r
897 /* Check the parameters */
\r
898 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
899 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
900 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
901 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
902 /* Disable the Channel 2: Reset the CC2E Bit */
\r
903 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
\r
905 /* Get the TIMx CCER register value */
\r
906 tmpccer = TIMx->CCER;
\r
907 /* Get the TIMx CR2 register value */
\r
908 tmpcr2 = TIMx->CR2;
\r
910 /* Get the TIMx CCMR2 register value */
\r
911 tmpccmrx = TIMx->CCMR2;
\r
913 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
914 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
\r
915 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
\r
916 /* Select the Output Compare Mode */
\r
917 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\r
919 /* Reset the Output Polarity level */
\r
920 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
\r
921 /* Set the Output Compare Polarity */
\r
922 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
\r
924 /* Set the Output State */
\r
925 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
\r
929 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
\r
930 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
\r
931 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
\r
932 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
934 /* Reset the Output N Polarity level */
\r
935 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
\r
936 /* Set the Output N Polarity */
\r
937 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
\r
938 /* Reset the Output N State */
\r
939 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
\r
941 /* Set the Output N State */
\r
942 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
\r
943 /* Reset the Ouput Compare and Output Compare N IDLE State */
\r
944 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
\r
945 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
\r
946 /* Set the Output Idle state */
\r
947 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
\r
948 /* Set the Output N Idle state */
\r
949 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
\r
951 /* Write to TIMx CR2 */
\r
952 TIMx->CR2 = tmpcr2;
\r
954 /* Write to TIMx CCMR2 */
\r
955 TIMx->CCMR2 = tmpccmrx;
\r
957 /* Set the Capture Compare Register value */
\r
958 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
\r
960 /* Write to TIMx CCER */
\r
961 TIMx->CCER = tmpccer;
\r
965 * @brief Initializes the TIMx Channel4 according to the specified
\r
966 * parameters in the TIM_OCInitStruct.
\r
967 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
968 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
969 * that contains the configuration information for the specified TIM
\r
973 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
975 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\r
977 /* Check the parameters */
\r
978 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
979 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
980 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
981 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
982 /* Disable the Channel 2: Reset the CC4E Bit */
\r
983 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
\r
985 /* Get the TIMx CCER register value */
\r
986 tmpccer = TIMx->CCER;
\r
987 /* Get the TIMx CR2 register value */
\r
988 tmpcr2 = TIMx->CR2;
\r
990 /* Get the TIMx CCMR2 register value */
\r
991 tmpccmrx = TIMx->CCMR2;
\r
993 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
994 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
\r
995 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
\r
997 /* Select the Output Compare Mode */
\r
998 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
1000 /* Reset the Output Polarity level */
\r
1001 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
\r
1002 /* Set the Output Compare Polarity */
\r
1003 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
\r
1005 /* Set the Output State */
\r
1006 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
\r
1010 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
1011 /* Reset the Ouput Compare IDLE State */
\r
1012 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
\r
1013 /* Set the Output Idle state */
\r
1014 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
\r
1016 /* Write to TIMx CR2 */
\r
1017 TIMx->CR2 = tmpcr2;
\r
1019 /* Write to TIMx CCMR2 */
\r
1020 TIMx->CCMR2 = tmpccmrx;
\r
1022 /* Set the Capture Compare Register value */
\r
1023 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
\r
1025 /* Write to TIMx CCER */
\r
1026 TIMx->CCER = tmpccer;
\r
1030 * @brief Fills each TIM_OCInitStruct member with its default value.
\r
1031 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
\r
1035 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
1037 /* Set the default configuration */
\r
1038 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
\r
1039 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
\r
1040 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
\r
1041 TIM_OCInitStruct->TIM_Pulse = 0x0000000;
\r
1042 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
\r
1043 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
\r
1044 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
\r
1045 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
\r
1049 * @brief Selects the TIM Output Compare Mode.
\r
1050 * @note This function disables the selected channel before changing the Output
\r
1052 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
\r
1053 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1054 * @param TIM_Channel: specifies the TIM Channel
\r
1055 * This parameter can be one of the following values:
\r
1056 * @arg TIM_Channel_1: TIM Channel 1
\r
1057 * @arg TIM_Channel_2: TIM Channel 2
\r
1058 * @arg TIM_Channel_3: TIM Channel 3
\r
1059 * @arg TIM_Channel_4: TIM Channel 4
\r
1060 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
\r
1061 * This parameter can be one of the following values:
\r
1062 * @arg TIM_OCMode_Timing
\r
1063 * @arg TIM_OCMode_Active
\r
1064 * @arg TIM_OCMode_Toggle
\r
1065 * @arg TIM_OCMode_PWM1
\r
1066 * @arg TIM_OCMode_PWM2
\r
1067 * @arg TIM_ForcedAction_Active
\r
1068 * @arg TIM_ForcedAction_InActive
\r
1071 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
\r
1074 uint16_t tmp1 = 0;
\r
1076 /* Check the parameters */
\r
1077 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1078 assert_param(IS_TIM_OCM(TIM_OCMode));
\r
1080 tmp = (uint32_t) TIMx;
\r
1081 tmp += CCMR_OFFSET;
\r
1083 tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
\r
1085 /* Disable the Channel: Reset the CCxE Bit */
\r
1086 TIMx->CCER &= (uint16_t) ~tmp1;
\r
1088 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
\r
1090 tmp += (TIM_Channel>>1);
\r
1092 /* Reset the OCxM bits in the CCMRx register */
\r
1093 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
\r
1095 /* Configure the OCxM bits in the CCMRx register */
\r
1096 *(__IO uint32_t *) tmp |= TIM_OCMode;
\r
1100 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
\r
1102 /* Reset the OCxM bits in the CCMRx register */
\r
1103 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
\r
1105 /* Configure the OCxM bits in the CCMRx register */
\r
1106 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
\r
1111 * @brief Sets the TIMx Capture Compare1 Register value
\r
1112 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1113 * @param Compare1: specifies the Capture Compare1 register new value.
\r
1116 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
\r
1118 /* Check the parameters */
\r
1119 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1121 /* Set the Capture Compare1 Register value */
\r
1122 TIMx->CCR1 = Compare1;
\r
1126 * @brief Sets the TIMx Capture Compare2 Register value
\r
1127 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
1128 * @param Compare2: specifies the Capture Compare2 register new value.
\r
1131 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
\r
1133 /* Check the parameters */
\r
1134 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1136 /* Set the Capture Compare2 Register value */
\r
1137 TIMx->CCR2 = Compare2;
\r
1141 * @brief Sets the TIMx Capture Compare3 Register value
\r
1142 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1143 * @param Compare3: specifies the Capture Compare3 register new value.
\r
1146 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
\r
1148 /* Check the parameters */
\r
1149 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1151 /* Set the Capture Compare3 Register value */
\r
1152 TIMx->CCR3 = Compare3;
\r
1156 * @brief Sets the TIMx Capture Compare4 Register value
\r
1157 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1158 * @param Compare4: specifies the Capture Compare4 register new value.
\r
1161 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
\r
1163 /* Check the parameters */
\r
1164 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1166 /* Set the Capture Compare4 Register value */
\r
1167 TIMx->CCR4 = Compare4;
\r
1171 * @brief Forces the TIMx output 1 waveform to active or inactive level.
\r
1172 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1173 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1174 * This parameter can be one of the following values:
\r
1175 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
\r
1176 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
\r
1179 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1181 uint16_t tmpccmr1 = 0;
\r
1182 /* Check the parameters */
\r
1183 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1184 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1185 tmpccmr1 = TIMx->CCMR1;
\r
1186 /* Reset the OC1M Bits */
\r
1187 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
\r
1188 /* Configure The Forced output Mode */
\r
1189 tmpccmr1 |= TIM_ForcedAction;
\r
1190 /* Write to TIMx CCMR1 register */
\r
1191 TIMx->CCMR1 = tmpccmr1;
\r
1195 * @brief Forces the TIMx output 2 waveform to active or inactive level.
\r
1196 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM
\r
1198 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1199 * This parameter can be one of the following values:
\r
1200 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
\r
1201 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
\r
1204 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1206 uint16_t tmpccmr1 = 0;
\r
1208 /* Check the parameters */
\r
1209 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1210 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1212 tmpccmr1 = TIMx->CCMR1;
\r
1213 /* Reset the OC2M Bits */
\r
1214 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
\r
1215 /* Configure The Forced output Mode */
\r
1216 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1217 /* Write to TIMx CCMR1 register */
\r
1218 TIMx->CCMR1 = tmpccmr1;
\r
1222 * @brief Forces the TIMx output 3 waveform to active or inactive level.
\r
1223 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1224 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1225 * This parameter can be one of the following values:
\r
1226 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
\r
1227 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
\r
1230 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1232 uint16_t tmpccmr2 = 0;
\r
1234 /* Check the parameters */
\r
1235 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1236 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1238 tmpccmr2 = TIMx->CCMR2;
\r
1239 /* Reset the OC1M Bits */
\r
1240 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
\r
1241 /* Configure The Forced output Mode */
\r
1242 tmpccmr2 |= TIM_ForcedAction;
\r
1243 /* Write to TIMx CCMR2 register */
\r
1244 TIMx->CCMR2 = tmpccmr2;
\r
1248 * @brief Forces the TIMx output 4 waveform to active or inactive level.
\r
1249 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1250 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1251 * This parameter can be one of the following values:
\r
1252 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
\r
1253 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
\r
1256 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1258 uint16_t tmpccmr2 = 0;
\r
1259 /* Check the parameters */
\r
1260 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1261 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1263 tmpccmr2 = TIMx->CCMR2;
\r
1264 /* Reset the OC2M Bits */
\r
1265 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
\r
1266 /* Configure The Forced output Mode */
\r
1267 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1268 /* Write to TIMx CCMR2 register */
\r
1269 TIMx->CCMR2 = tmpccmr2;
\r
1273 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
\r
1274 * @param TIMx: where x can be 1, 2, 3 or 15
\r
1275 * to select the TIMx peripheral
\r
1276 * @param NewState: new state of the Capture Compare Preload Control bit
\r
1277 * This parameter can be: ENABLE or DISABLE.
\r
1280 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1282 /* Check the parameters */
\r
1283 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1284 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1285 if (NewState != DISABLE)
\r
1287 /* Set the CCPC Bit */
\r
1288 TIMx->CR2 |= TIM_CR2_CCPC;
\r
1292 /* Reset the CCPC Bit */
\r
1293 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
\r
1299 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
\r
1300 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
\r
1301 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1302 * This parameter can be one of the following values:
\r
1303 * @arg TIM_OCPreload_Enable
\r
1304 * @arg TIM_OCPreload_Disable
\r
1307 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1309 uint16_t tmpccmr1 = 0;
\r
1310 /* Check the parameters */
\r
1311 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1312 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1314 tmpccmr1 = TIMx->CCMR1;
\r
1315 /* Reset the OC1PE Bit */
\r
1316 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
\r
1317 /* Enable or Disable the Output Compare Preload feature */
\r
1318 tmpccmr1 |= TIM_OCPreload;
\r
1319 /* Write to TIMx CCMR1 register */
\r
1320 TIMx->CCMR1 = tmpccmr1;
\r
1324 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
\r
1325 * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.
\r
1326 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1327 * This parameter can be one of the following values:
\r
1328 * @arg TIM_OCPreload_Enable
\r
1329 * @arg TIM_OCPreload_Disable
\r
1332 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1334 uint16_t tmpccmr1 = 0;
\r
1335 /* Check the parameters */
\r
1336 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1337 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1339 tmpccmr1 = TIMx->CCMR1;
\r
1340 /* Reset the OC2PE Bit */
\r
1341 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
\r
1342 /* Enable or Disable the Output Compare Preload feature */
\r
1343 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
\r
1344 /* Write to TIMx CCMR1 register */
\r
1345 TIMx->CCMR1 = tmpccmr1;
\r
1349 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
\r
1350 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1351 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1352 * This parameter can be one of the following values:
\r
1353 * @arg TIM_OCPreload_Enable
\r
1354 * @arg TIM_OCPreload_Disable
\r
1357 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1359 uint16_t tmpccmr2 = 0;
\r
1361 /* Check the parameters */
\r
1362 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1363 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1365 tmpccmr2 = TIMx->CCMR2;
\r
1366 /* Reset the OC3PE Bit */
\r
1367 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
\r
1368 /* Enable or Disable the Output Compare Preload feature */
\r
1369 tmpccmr2 |= TIM_OCPreload;
\r
1370 /* Write to TIMx CCMR2 register */
\r
1371 TIMx->CCMR2 = tmpccmr2;
\r
1375 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
\r
1376 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1377 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1378 * This parameter can be one of the following values:
\r
1379 * @arg TIM_OCPreload_Enable
\r
1380 * @arg TIM_OCPreload_Disable
\r
1383 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1385 uint16_t tmpccmr2 = 0;
\r
1387 /* Check the parameters */
\r
1388 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1389 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1391 tmpccmr2 = TIMx->CCMR2;
\r
1392 /* Reset the OC4PE Bit */
\r
1393 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
\r
1394 /* Enable or Disable the Output Compare Preload feature */
\r
1395 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
\r
1396 /* Write to TIMx CCMR2 register */
\r
1397 TIMx->CCMR2 = tmpccmr2;
\r
1401 * @brief Configures the TIMx Output Compare 1 Fast feature.
\r
1402 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1403 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1404 * This parameter can be one of the following values:
\r
1405 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1406 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1409 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1411 uint16_t tmpccmr1 = 0;
\r
1413 /* Check the parameters */
\r
1414 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1415 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1417 /* Get the TIMx CCMR1 register value */
\r
1418 tmpccmr1 = TIMx->CCMR1;
\r
1419 /* Reset the OC1FE Bit */
\r
1420 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
\r
1421 /* Enable or Disable the Output Compare Fast Bit */
\r
1422 tmpccmr1 |= TIM_OCFast;
\r
1423 /* Write to TIMx CCMR1 */
\r
1424 TIMx->CCMR1 = tmpccmr1;
\r
1428 * @brief Configures the TIMx Output Compare 2 Fast feature.
\r
1429 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
1430 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1431 * This parameter can be one of the following values:
\r
1432 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1433 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1436 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1438 uint16_t tmpccmr1 = 0;
\r
1440 /* Check the parameters */
\r
1441 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1442 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1444 /* Get the TIMx CCMR1 register value */
\r
1445 tmpccmr1 = TIMx->CCMR1;
\r
1446 /* Reset the OC2FE Bit */
\r
1447 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
\r
1448 /* Enable or Disable the Output Compare Fast Bit */
\r
1449 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
\r
1450 /* Write to TIMx CCMR1 */
\r
1451 TIMx->CCMR1 = tmpccmr1;
\r
1455 * @brief Configures the TIMx Output Compare 3 Fast feature.
\r
1456 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1457 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1458 * This parameter can be one of the following values:
\r
1459 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1460 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1463 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1465 uint16_t tmpccmr2 = 0;
\r
1467 /* Check the parameters */
\r
1468 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1469 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1471 /* Get the TIMx CCMR2 register value */
\r
1472 tmpccmr2 = TIMx->CCMR2;
\r
1473 /* Reset the OC3FE Bit */
\r
1474 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
\r
1475 /* Enable or Disable the Output Compare Fast Bit */
\r
1476 tmpccmr2 |= TIM_OCFast;
\r
1477 /* Write to TIMx CCMR2 */
\r
1478 TIMx->CCMR2 = tmpccmr2;
\r
1482 * @brief Configures the TIMx Output Compare 4 Fast feature.
\r
1483 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1484 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1485 * This parameter can be one of the following values:
\r
1486 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1487 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1490 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1492 uint16_t tmpccmr2 = 0;
\r
1494 /* Check the parameters */
\r
1495 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1496 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1498 /* Get the TIMx CCMR2 register value */
\r
1499 tmpccmr2 = TIMx->CCMR2;
\r
1500 /* Reset the OC4FE Bit */
\r
1501 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
\r
1502 /* Enable or Disable the Output Compare Fast Bit */
\r
1503 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
\r
1504 /* Write to TIMx CCMR2 */
\r
1505 TIMx->CCMR2 = tmpccmr2;
\r
1509 * @brief Clears or safeguards the OCREF1 signal on an external event
\r
1510 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1511 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1512 * This parameter can be one of the following values:
\r
1513 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1514 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1517 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1519 uint16_t tmpccmr1 = 0;
\r
1521 /* Check the parameters */
\r
1522 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1523 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1525 tmpccmr1 = TIMx->CCMR1;
\r
1526 /* Reset the OC1CE Bit */
\r
1527 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
\r
1528 /* Enable or Disable the Output Compare Clear Bit */
\r
1529 tmpccmr1 |= TIM_OCClear;
\r
1530 /* Write to TIMx CCMR1 register */
\r
1531 TIMx->CCMR1 = tmpccmr1;
\r
1535 * @brief Clears or safeguards the OCREF2 signal on an external event
\r
1536 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
1537 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1539 * This parameter can be one of the following values:
\r
1540 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1541 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1544 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1546 uint16_t tmpccmr1 = 0;
\r
1548 /* Check the parameters */
\r
1549 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1550 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1552 tmpccmr1 = TIMx->CCMR1;
\r
1553 /* Reset the OC2CE Bit */
\r
1554 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
\r
1555 /* Enable or Disable the Output Compare Clear Bit */
\r
1556 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
\r
1557 /* Write to TIMx CCMR1 register */
\r
1558 TIMx->CCMR1 = tmpccmr1;
\r
1562 * @brief Clears or safeguards the OCREF3 signal on an external event
\r
1563 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1564 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1565 * This parameter can be one of the following values:
\r
1566 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1567 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1570 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1572 uint16_t tmpccmr2 = 0;
\r
1574 /* Check the parameters */
\r
1575 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1576 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1578 tmpccmr2 = TIMx->CCMR2;
\r
1579 /* Reset the OC3CE Bit */
\r
1580 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
\r
1581 /* Enable or Disable the Output Compare Clear Bit */
\r
1582 tmpccmr2 |= TIM_OCClear;
\r
1583 /* Write to TIMx CCMR2 register */
\r
1584 TIMx->CCMR2 = tmpccmr2;
\r
1588 * @brief Clears or safeguards the OCREF4 signal on an external event
\r
1589 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1590 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1591 * This parameter can be one of the following values:
\r
1592 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1593 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1596 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1598 uint16_t tmpccmr2 = 0;
\r
1600 /* Check the parameters */
\r
1601 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1602 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1604 tmpccmr2 = TIMx->CCMR2;
\r
1605 /* Reset the OC4CE Bit */
\r
1606 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
\r
1607 /* Enable or Disable the Output Compare Clear Bit */
\r
1608 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
\r
1609 /* Write to TIMx CCMR2 register */
\r
1610 TIMx->CCMR2 = tmpccmr2;
\r
1614 * @brief Configures the TIMx channel 1 polarity.
\r
1615 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1616 * @param TIM_OCPolarity: specifies the OC1 Polarity
\r
1617 * This parmeter can be one of the following values:
\r
1618 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1619 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1622 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1624 uint16_t tmpccer = 0;
\r
1626 /* Check the parameters */
\r
1627 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1628 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1630 tmpccer = TIMx->CCER;
\r
1631 /* Set or Reset the CC1P Bit */
\r
1632 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
\r
1633 tmpccer |= TIM_OCPolarity;
\r
1634 /* Write to TIMx CCER register */
\r
1635 TIMx->CCER = tmpccer;
\r
1639 * @brief Configures the TIMx Channel 1N polarity.
\r
1640 * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
\r
1641 * @param TIM_OCNPolarity: specifies the OC1N Polarity
\r
1642 * This parmeter can be one of the following values:
\r
1643 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1644 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1647 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1649 uint16_t tmpccer = 0;
\r
1650 /* Check the parameters */
\r
1651 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1652 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1654 tmpccer = TIMx->CCER;
\r
1655 /* Set or Reset the CC1NP Bit */
\r
1656 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
\r
1657 tmpccer |= TIM_OCNPolarity;
\r
1658 /* Write to TIMx CCER register */
\r
1659 TIMx->CCER = tmpccer;
\r
1663 * @brief Configures the TIMx channel 2 polarity.
\r
1664 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
1665 * @param TIM_OCPolarity: specifies the OC2 Polarity
\r
1666 * This parmeter can be one of the following values:
\r
1667 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1668 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1671 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1673 uint16_t tmpccer = 0;
\r
1675 /* Check the parameters */
\r
1676 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1677 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1679 tmpccer = TIMx->CCER;
\r
1680 /* Set or Reset the CC2P Bit */
\r
1681 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
\r
1682 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
\r
1683 /* Write to TIMx CCER register */
\r
1684 TIMx->CCER = tmpccer;
\r
1688 * @brief Configures the TIMx Channel 2N polarity.
\r
1689 * @param TIMx: where x can be 1 to select the TIM peripheral.
\r
1690 * @param TIM_OCNPolarity: specifies the OC2N Polarity
\r
1691 * This parmeter can be one of the following values:
\r
1692 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1693 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1696 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1698 uint16_t tmpccer = 0;
\r
1699 /* Check the parameters */
\r
1700 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1701 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1703 tmpccer = TIMx->CCER;
\r
1704 /* Set or Reset the CC2NP Bit */
\r
1705 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
\r
1706 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
\r
1707 /* Write to TIMx CCER register */
\r
1708 TIMx->CCER = tmpccer;
\r
1712 * @brief Configures the TIMx channel 3 polarity.
\r
1713 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1714 * @param TIM_OCPolarity: specifies the OC3 Polarity
\r
1715 * This parmeter can be one of the following values:
\r
1716 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1717 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1720 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1722 uint16_t tmpccer = 0;
\r
1724 /* Check the parameters */
\r
1725 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1726 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1728 tmpccer = TIMx->CCER;
\r
1729 /* Set or Reset the CC3P Bit */
\r
1730 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
\r
1731 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
\r
1732 /* Write to TIMx CCER register */
\r
1733 TIMx->CCER = tmpccer;
\r
1737 * @brief Configures the TIMx Channel 3N polarity.
\r
1738 * @param TIMx: where x can be 1 to select the TIM peripheral.
\r
1739 * @param TIM_OCNPolarity: specifies the OC3N Polarity
\r
1740 * This parmeter can be one of the following values:
\r
1741 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1742 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1745 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1747 uint16_t tmpccer = 0;
\r
1749 /* Check the parameters */
\r
1750 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1751 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1753 tmpccer = TIMx->CCER;
\r
1754 /* Set or Reset the CC3NP Bit */
\r
1755 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
\r
1756 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
\r
1757 /* Write to TIMx CCER register */
\r
1758 TIMx->CCER = tmpccer;
\r
1763 * @brief Configures the TIMx channel 4 polarity.
\r
1764 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1765 * @param TIM_OCPolarity: specifies the OC4 Polarity
\r
1766 * This parmeter can be one of the following values:
\r
1767 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1768 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1771 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1773 uint16_t tmpccer = 0;
\r
1775 /* Check the parameters */
\r
1776 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1777 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1779 tmpccer = TIMx->CCER;
\r
1780 /* Set or Reset the CC4P Bit */
\r
1781 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
\r
1782 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
\r
1783 /* Write to TIMx CCER register */
\r
1784 TIMx->CCER = tmpccer;
\r
1788 * @brief Selects the OCReference Clear source.
\r
1789 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
1790 * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
\r
1791 * This parameter can be one of the following values:
\r
1792 * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
\r
1793 * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
\r
1796 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
\r
1798 /* Check the parameters */
\r
1799 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1800 assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
\r
1802 /* Set the TIM_OCReferenceClear source */
\r
1803 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
\r
1804 TIMx->SMCR |= TIM_OCReferenceClear;
\r
1808 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
1809 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1810 * @param TIM_Channel: specifies the TIM Channel
\r
1811 * This parameter can be one of the following values:
\r
1812 * @arg TIM_Channel_1: TIM Channel 1
\r
1813 * @arg TIM_Channel_2: TIM Channel 2
\r
1814 * @arg TIM_Channel_3: TIM Channel 3
\r
1815 * @arg TIM_Channel_4: TIM Channel 4
\r
1816 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
\r
1817 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
\r
1820 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
\r
1824 /* Check the parameters */
\r
1825 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1826 assert_param(IS_TIM_CCX(TIM_CCx));
\r
1828 tmp = CCER_CCE_SET << TIM_Channel;
\r
1830 /* Reset the CCxE Bit */
\r
1831 TIMx->CCER &= (uint16_t)~ tmp;
\r
1833 /* Set or reset the CCxE Bit */
\r
1834 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
\r
1838 * @brief Enables or disables the TIM Capture Compare Channel xN.
\r
1839 * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
\r
1840 * @param TIM_Channel: specifies the TIM Channel
\r
1841 * This parmeter can be one of the following values:
\r
1842 * @arg TIM_Channel_1: TIM Channel 1
\r
1843 * @arg TIM_Channel_2: TIM Channel 2
\r
1844 * @arg TIM_Channel_3: TIM Channel 3
\r
1845 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
\r
1846 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
\r
1849 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
\r
1853 /* Check the parameters */
\r
1854 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1855 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
\r
1856 assert_param(IS_TIM_CCXN(TIM_CCxN));
\r
1858 tmp = CCER_CCNE_SET << TIM_Channel;
\r
1860 /* Reset the CCxNE Bit */
\r
1861 TIMx->CCER &= (uint16_t) ~tmp;
\r
1863 /* Set or reset the CCxNE Bit */
\r
1864 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
\r
1868 * @brief Selects the TIM peripheral Commutation event.
\r
1869 * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral
\r
1870 * @param NewState: new state of the Commutation event.
\r
1871 * This parameter can be: ENABLE or DISABLE.
\r
1874 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1876 /* Check the parameters */
\r
1877 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1878 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1879 if (NewState != DISABLE)
\r
1881 /* Set the COM Bit */
\r
1882 TIMx->CR2 |= TIM_CR2_CCUS;
\r
1886 /* Reset the COM Bit */
\r
1887 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
\r
1895 /** @defgroup TIM_Group4 Input Capture management functions
\r
1896 * @brief Input Capture management functions
\r
1899 ===============================================================================
\r
1900 ##### Input Capture management functions #####
\r
1901 ===============================================================================
\r
1903 *** TIM Driver: how to use it in Input Capture Mode ***
\r
1904 ===============================================================================
\r
1905 [..] To use the Timer in Input Capture mode, the following steps are mandatory:
\r
1906 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
\r
1908 (#) Configure the TIM pins by configuring the corresponding GPIO pins.
\r
1909 (#) Configure the Time base unit as described in the first part of this
\r
1910 driver, if needed, else the Timer will run with the default configuration:
\r
1911 (++) Autoreload value = 0xFFFF.
\r
1912 (++) Prescaler value = 0x0000.
\r
1913 (++) Counter mode = Up counting.
\r
1914 (++) Clock Division = TIM_CKD_DIV1.
\r
1915 (#) Fill the TIM_ICInitStruct with the desired parameters including:
\r
1916 (++) TIM Channel: TIM_Channel.
\r
1917 (++) TIM Input Capture polarity: TIM_ICPolarity.
\r
1918 (++) TIM Input Capture selection: TIM_ICSelection.
\r
1919 (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
\r
1920 (++) TIM Input CApture filter value: TIM_ICFilter.
\r
1921 (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired
\r
1922 channel with the corresponding configuration and to measure only
\r
1923 frequency or duty cycle of the input signal,or, Call
\r
1924 TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired
\r
1925 channels with the corresponding configuration and to measure the
\r
1926 frequency and the duty cycle of the input signal.
\r
1927 (#) Enable the NVIC or the DMA to read the measured frequency.
\r
1928 (#) Enable the corresponding interrupt (or DMA request) to read
\r
1929 the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
\r
1930 (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
\r
1931 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
\r
1932 (#) Use TIM_GetCapturex(TIMx); to read the captured value.
\r
1934 (@) All other functions can be used separately to modify, if needed,
\r
1935 a specific feature of the Timer.
\r
1942 * @brief Initializes the TIM peripheral according to the specified
\r
1943 * parameters in the TIM_ICInitStruct.
\r
1944 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
1945 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
1946 * that contains the configuration information for the specified TIM
\r
1950 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
1952 /* Check the parameters */
\r
1953 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1954 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
\r
1955 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
\r
1956 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
\r
1957 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
\r
1958 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
\r
1960 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
1962 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1963 /* TI1 Configuration */
\r
1964 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1965 TIM_ICInitStruct->TIM_ICSelection,
\r
1966 TIM_ICInitStruct->TIM_ICFilter);
\r
1967 /* Set the Input Capture Prescaler value */
\r
1968 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1970 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
\r
1972 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1973 /* TI2 Configuration */
\r
1974 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1975 TIM_ICInitStruct->TIM_ICSelection,
\r
1976 TIM_ICInitStruct->TIM_ICFilter);
\r
1977 /* Set the Input Capture Prescaler value */
\r
1978 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1980 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
\r
1982 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1983 /* TI3 Configuration */
\r
1984 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1985 TIM_ICInitStruct->TIM_ICSelection,
\r
1986 TIM_ICInitStruct->TIM_ICFilter);
\r
1987 /* Set the Input Capture Prescaler value */
\r
1988 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1992 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1993 /* TI4 Configuration */
\r
1994 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1995 TIM_ICInitStruct->TIM_ICSelection,
\r
1996 TIM_ICInitStruct->TIM_ICFilter);
\r
1997 /* Set the Input Capture Prescaler value */
\r
1998 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
2003 * @brief Fills each TIM_ICInitStruct member with its default value.
\r
2004 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
\r
2008 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
2010 /* Set the default configuration */
\r
2011 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
\r
2012 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
\r
2013 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
\r
2014 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
\r
2015 TIM_ICInitStruct->TIM_ICFilter = 0x00;
\r
2019 * @brief Configures the TIM peripheral according to the specified
\r
2020 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
\r
2021 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
2022 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
2023 * that contains the configuration information for the specified TIM
\r
2027 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
2029 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
\r
2030 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
\r
2031 /* Check the parameters */
\r
2032 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2033 /* Select the Opposite Input Polarity */
\r
2034 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
\r
2036 icoppositepolarity = TIM_ICPolarity_Falling;
\r
2040 icoppositepolarity = TIM_ICPolarity_Rising;
\r
2042 /* Select the Opposite Input */
\r
2043 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
\r
2045 icoppositeselection = TIM_ICSelection_IndirectTI;
\r
2049 icoppositeselection = TIM_ICSelection_DirectTI;
\r
2051 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
2053 /* TI1 Configuration */
\r
2054 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
2055 TIM_ICInitStruct->TIM_ICFilter);
\r
2056 /* Set the Input Capture Prescaler value */
\r
2057 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
2058 /* TI2 Configuration */
\r
2059 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
2060 /* Set the Input Capture Prescaler value */
\r
2061 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
2065 /* TI2 Configuration */
\r
2066 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
2067 TIM_ICInitStruct->TIM_ICFilter);
\r
2068 /* Set the Input Capture Prescaler value */
\r
2069 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
2070 /* TI1 Configuration */
\r
2071 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
2072 /* Set the Input Capture Prescaler value */
\r
2073 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
2078 * @brief Gets the TIMx Input Capture 1 value.
\r
2079 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2080 * @retval Capture Compare 1 Register value.
\r
2082 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
\r
2084 /* Check the parameters */
\r
2085 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
2087 /* Get the Capture 1 Register value */
\r
2088 return TIMx->CCR1;
\r
2092 * @brief Gets the TIMx Input Capture 2 value.
\r
2093 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
2094 * @retval Capture Compare 2 Register value.
\r
2096 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
\r
2098 /* Check the parameters */
\r
2099 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2101 /* Get the Capture 2 Register value */
\r
2102 return TIMx->CCR2;
\r
2106 * @brief Gets the TIMx Input Capture 3 value.
\r
2107 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2108 * @retval Capture Compare 3 Register value.
\r
2110 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
\r
2112 /* Check the parameters */
\r
2113 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2115 /* Get the Capture 3 Register value */
\r
2116 return TIMx->CCR3;
\r
2120 * @brief Gets the TIMx Input Capture 4 value.
\r
2121 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2122 * @retval Capture Compare 4 Register value.
\r
2124 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
\r
2126 /* Check the parameters */
\r
2127 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2129 /* Get the Capture 4 Register value */
\r
2130 return TIMx->CCR4;
\r
2134 * @brief Sets the TIMx Input Capture 1 prescaler.
\r
2135 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2136 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
\r
2137 * This parameter can be one of the following values:
\r
2138 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2139 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2140 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2141 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2144 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2146 /* Check the parameters */
\r
2147 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
2148 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2150 /* Reset the IC1PSC Bits */
\r
2151 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
\r
2152 /* Set the IC1PSC value */
\r
2153 TIMx->CCMR1 |= TIM_ICPSC;
\r
2157 * @brief Sets the TIMx Input Capture 2 prescaler.
\r
2158 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
2159 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
\r
2160 * This parameter can be one of the following values:
\r
2161 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2162 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2163 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2164 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2167 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2169 /* Check the parameters */
\r
2170 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2171 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2173 /* Reset the IC2PSC Bits */
\r
2174 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
\r
2175 /* Set the IC2PSC value */
\r
2176 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
\r
2180 * @brief Sets the TIMx Input Capture 3 prescaler.
\r
2181 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2182 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
\r
2183 * This parameter can be one of the following values:
\r
2184 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2185 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2186 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2187 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2190 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2192 /* Check the parameters */
\r
2193 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2194 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2196 /* Reset the IC3PSC Bits */
\r
2197 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
\r
2198 /* Set the IC3PSC value */
\r
2199 TIMx->CCMR2 |= TIM_ICPSC;
\r
2203 * @brief Sets the TIMx Input Capture 4 prescaler.
\r
2204 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2205 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
\r
2206 * This parameter can be one of the following values:
\r
2207 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2208 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2209 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2210 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2213 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2215 /* Check the parameters */
\r
2216 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2217 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2219 /* Reset the IC4PSC Bits */
\r
2220 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
\r
2221 /* Set the IC4PSC value */
\r
2222 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
\r
2229 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions
\r
2230 * @brief Interrupts, DMA and flags management functions
\r
2233 ===============================================================================
\r
2234 ##### Interrupts, DMA and flags management functions #####
\r
2235 ===============================================================================
\r
2242 * @brief Enables or disables the specified TIM interrupts.
\r
2243 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIMx peripheral.
\r
2244 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
\r
2245 * This parameter can be any combination of the following values:
\r
2246 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2247 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2248 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2249 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2250 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2251 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2252 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2253 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2255 * - TIM6 can only generate an update interrupt.
\r
2256 * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
\r
2257 * TIM_IT_CC2 or TIM_IT_Trigger.
\r
2258 * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
2259 * - TIM_IT_Break is used only with TIM1 and TIM15.
\r
2260 * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
\r
2261 * @param NewState: new state of the TIM interrupts.
\r
2262 * This parameter can be: ENABLE or DISABLE.
\r
2265 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
\r
2267 /* Check the parameters */
\r
2268 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2269 assert_param(IS_TIM_IT(TIM_IT));
\r
2270 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2272 if (NewState != DISABLE)
\r
2274 /* Enable the Interrupt sources */
\r
2275 TIMx->DIER |= TIM_IT;
\r
2279 /* Disable the Interrupt sources */
\r
2280 TIMx->DIER &= (uint16_t)~TIM_IT;
\r
2285 * @brief Configures the TIMx event to be generate by software.
\r
2286 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the
\r
2288 * @param TIM_EventSource: specifies the event source.
\r
2289 * This parameter can be one or more of the following values:
\r
2290 * @arg TIM_EventSource_Update: Timer update Event source
\r
2291 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
\r
2292 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
\r
2293 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
\r
2294 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
\r
2295 * @arg TIM_EventSource_COM: Timer COM event source
\r
2296 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
\r
2297 * @arg TIM_EventSource_Break: Timer Break event source
\r
2299 * - TIM6 can only generate an update event.
\r
2300 * - TIM9 can only generate an update event, Capture Compare 1 event,
\r
2301 * Capture Compare 2 event and TIM_EventSource_Trigger.
\r
2302 * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
\r
2305 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
\r
2307 /* Check the parameters */
\r
2308 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2309 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
\r
2310 /* Set the event sources */
\r
2311 TIMx->EGR = TIM_EventSource;
\r
2315 * @brief Checks whether the specified TIM flag is set or not.
\r
2316 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2317 * @param TIM_FLAG: specifies the flag to check.
\r
2318 * This parameter can be one of the following values:
\r
2319 * @arg TIM_FLAG_Update: TIM update Flag
\r
2320 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2321 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2322 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2323 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2324 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2325 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2326 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2327 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2328 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2329 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2330 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2332 * - TIM6 can have only one update flag.
\r
2333 * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or
\r
2334 * TIM_FLAG_Trigger.
\r
2335 * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
\r
2336 * - TIM_FLAG_Break is used only with TIM1 and TIM15.
\r
2337 * - TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
\r
2338 * @retval The new state of TIM_FLAG (SET or RESET).
\r
2340 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2342 ITStatus bitstatus = RESET;
\r
2344 /* Check the parameters */
\r
2345 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2346 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
\r
2348 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
\r
2354 bitstatus = RESET;
\r
2360 * @brief Clears the TIMx's pending flags.
\r
2361 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2362 * @param TIM_FLAG: specifies the flag bit to clear.
\r
2363 * This parameter can be any combination of the following values:
\r
2364 * @arg TIM_FLAG_Update: TIM update Flag
\r
2365 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2366 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2367 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2368 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2369 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2370 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2371 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2372 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2373 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2374 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2375 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2377 * - TIM6 can have only one update flag.
\r
2378 * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or
\r
2379 * TIM_FLAG_Trigger.
\r
2380 * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
\r
2381 * - TIM_FLAG_Break is used only with TIM1 and TIM15.
\r
2382 * - TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
\r
2385 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2387 /* Check the parameters */
\r
2388 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2389 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
\r
2391 /* Clear the flags */
\r
2392 TIMx->SR = (uint16_t)~TIM_FLAG;
\r
2396 * @brief Checks whether the TIM interrupt has occurred or not.
\r
2397 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2398 * @param TIM_IT: specifies the TIM interrupt source to check.
\r
2399 * This parameter can be one of the following values:
\r
2400 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2401 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2402 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2403 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2404 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2405 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2406 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2407 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2409 * - TIM6 can generate only an update interrupt.
\r
2410 * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
\r
2411 * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
2412 * - TIM_IT_Break is used only with TIM1 and TIM15.
\r
2413 * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
\r
2414 * @retval The new state of the TIM_IT(SET or RESET).
\r
2416 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2418 ITStatus bitstatus = RESET;
\r
2419 uint16_t itstatus = 0x0, itenable = 0x0;
\r
2421 /* Check the parameters */
\r
2422 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2423 assert_param(IS_TIM_GET_IT(TIM_IT));
\r
2425 itstatus = TIMx->SR & TIM_IT;
\r
2427 itenable = TIMx->DIER & TIM_IT;
\r
2428 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
\r
2434 bitstatus = RESET;
\r
2440 * @brief Clears the TIMx's interrupt pending bits.
\r
2441 * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
\r
2442 * @param TIM_IT: specifies the pending bit to clear.
\r
2443 * This parameter can be any combination of the following values:
\r
2444 * @arg TIM_IT_Update: TIM1 update Interrupt source
\r
2445 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2446 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2447 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2448 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2449 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2450 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2451 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2453 * - TIM6 can generate only an update interrupt.
\r
2454 * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
\r
2455 * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
2456 * - TIM_IT_Break is used only with TIM1 and TIM15.
\r
2457 * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
\r
2460 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2462 /* Check the parameters */
\r
2463 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2464 assert_param(IS_TIM_IT(TIM_IT));
\r
2466 /* Clear the IT pending Bit */
\r
2467 TIMx->SR = (uint16_t)~TIM_IT;
\r
2471 * @brief Configures the TIMx's DMA interface.
\r
2472 * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
\r
2473 * @param TIM_DMABase: DMA Base address.
\r
2474 * This parameter can be one of the following values:
\r
2475 * @arg TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,
\r
2476 * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
\r
2477 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
\r
2478 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
\r
2479 * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
\r
2480 * TIM_DMABase_CCR4, TIM_DMABase_DCR, TIM_DMABase_OR.
\r
2481 * @param TIM_DMABurstLength: DMA Burst length.
\r
2482 * This parameter can be one value between:
\r
2483 * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
\r
2486 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
\r
2488 /* Check the parameters */
\r
2489 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
2490 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
\r
2491 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
\r
2492 /* Set the DMA Base and the DMA Burst Length */
\r
2493 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
\r
2497 * @brief Enables or disables the TIMx's DMA Requests.
\r
2498 * @param TIMx: where x can be 1, 2, 3, 6, 15, 16 or 17 to select the TIM peripheral.
\r
2499 * @param TIM_DMASource: specifies the DMA Request sources.
\r
2500 * This parameter can be any combination of the following values:
\r
2501 * @arg TIM_DMA_Update: TIM update Interrupt source
\r
2502 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
2503 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
2504 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
2505 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
2506 * @arg TIM_DMA_COM: TIM Commutation DMA source
\r
2507 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
\r
2508 * @param NewState: new state of the DMA Request sources.
\r
2509 * This parameter can be: ENABLE or DISABLE.
\r
2512 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
\r
2514 /* Check the parameters */
\r
2515 assert_param(IS_TIM_LIST10_PERIPH(TIMx));
\r
2516 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
\r
2517 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2519 if (NewState != DISABLE)
\r
2521 /* Enable the DMA sources */
\r
2522 TIMx->DIER |= TIM_DMASource;
\r
2526 /* Disable the DMA sources */
\r
2527 TIMx->DIER &= (uint16_t)~TIM_DMASource;
\r
2532 * @brief Selects the TIMx peripheral Capture Compare DMA source.
\r
2533 * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
\r
2534 * @param NewState: new state of the Capture Compare DMA source
\r
2535 * This parameter can be: ENABLE or DISABLE.
\r
2538 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2540 /* Check the parameters */
\r
2541 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
\r
2542 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2544 if (NewState != DISABLE)
\r
2546 /* Set the CCDS Bit */
\r
2547 TIMx->CR2 |= TIM_CR2_CCDS;
\r
2551 /* Reset the CCDS Bit */
\r
2552 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
\r
2560 /** @defgroup TIM_Group6 Clocks management functions
\r
2561 * @brief Clocks management functions
\r
2564 ===============================================================================
\r
2565 ##### Clocks management functions #####
\r
2566 ===============================================================================
\r
2573 * @brief Configures the TIMx internal Clock
\r
2574 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
2577 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
\r
2579 /* Check the parameters */
\r
2580 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2581 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
2582 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2586 * @brief Configures the TIMx Internal Trigger as External Clock
\r
2587 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
2588 * @param TIM_ITRSource: Trigger source.
\r
2589 * This parameter can be one of the following values:
\r
2590 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
2591 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
2592 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
2593 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
2596 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
2598 /* Check the parameters */
\r
2599 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2600 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
2601 /* Select the Internal Trigger */
\r
2602 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
\r
2603 /* Select the External clock mode1 */
\r
2604 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
2608 * @brief Configures the TIMx Trigger as External Clock
\r
2609 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
2610 * @param TIM_TIxExternalCLKSource: Trigger source.
\r
2611 * This parameter can be one of the following values:
\r
2612 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
\r
2613 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
\r
2614 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
\r
2615 * @param TIM_ICPolarity: specifies the TIx Polarity.
\r
2616 * This parameter can be one of the following values:
\r
2617 * @arg TIM_ICPolarity_Rising
\r
2618 * @arg TIM_ICPolarity_Falling
\r
2619 * @param ICFilter : specifies the filter value.
\r
2620 * This parameter must be a value between 0x0 and 0xF.
\r
2623 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
2624 uint16_t TIM_ICPolarity, uint16_t ICFilter)
\r
2626 /* Check the parameters */
\r
2627 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2628 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
\r
2629 assert_param(IS_TIM_IC_FILTER(ICFilter));
\r
2631 /* Configure the Timer Input Clock Source */
\r
2632 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
\r
2634 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
2638 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
2640 /* Select the Trigger source */
\r
2641 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
\r
2642 /* Select the External clock mode1 */
\r
2643 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
2647 * @brief Configures the External clock Mode1
\r
2648 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2649 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2650 * This parameter can be one of the following values:
\r
2651 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2652 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2653 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2654 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2655 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2656 * This parameter can be one of the following values:
\r
2657 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2658 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2659 * @param ExtTRGFilter: External Trigger Filter.
\r
2660 * This parameter must be a value between 0x00 and 0x0F
\r
2663 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
2664 uint16_t ExtTRGFilter)
\r
2666 uint16_t tmpsmcr = 0;
\r
2668 /* Check the parameters */
\r
2669 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2670 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2671 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2672 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2674 /* Configure the ETR Clock source */
\r
2675 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
2677 /* Get the TIMx SMCR register value */
\r
2678 tmpsmcr = TIMx->SMCR;
\r
2679 /* Reset the SMS Bits */
\r
2680 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2681 /* Select the External clock mode1 */
\r
2682 tmpsmcr |= TIM_SlaveMode_External1;
\r
2683 /* Select the Trigger selection : ETRF */
\r
2684 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
2685 tmpsmcr |= TIM_TS_ETRF;
\r
2686 /* Write to TIMx SMCR */
\r
2687 TIMx->SMCR = tmpsmcr;
\r
2691 * @brief Configures the External clock Mode2
\r
2692 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2693 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2694 * This parameter can be one of the following values:
\r
2695 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2696 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2697 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2698 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2699 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2700 * This parameter can be one of the following values:
\r
2701 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2702 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2703 * @param ExtTRGFilter: External Trigger Filter.
\r
2704 * This parameter must be a value between 0x00 and 0x0F
\r
2707 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
2708 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
\r
2710 /* Check the parameters */
\r
2711 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2712 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2713 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2714 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2716 /* Configure the ETR Clock source */
\r
2717 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
2718 /* Enable the External clock mode2 */
\r
2719 TIMx->SMCR |= TIM_SMCR_ECE;
\r
2726 /** @defgroup TIM_Group7 Synchronization management functions
\r
2727 * @brief Synchronization management functions
\r
2730 ===============================================================================
\r
2731 ##### Synchronization management functions #####
\r
2732 ===============================================================================
\r
2733 *** TIM Driver: how to use it in synchronization Mode ***
\r
2734 ===============================================================================
\r
2735 [..] Case of two/several Timers
\r
2736 (#) Configure the Master Timers using the following functions:
\r
2737 (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
\r
2738 uint16_t TIM_TRGOSource).
\r
2739 (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
\r
2740 uint16_t TIM_MasterSlaveMode);
\r
2741 (#) Configure the Slave Timers using the following functions:
\r
2742 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
\r
2743 uint16_t TIM_InputTriggerSource);
\r
2744 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
\r
2745 [..] Case of Timers and external trigger(ETR pin)
\r
2746 (#) Configure the Etrenal trigger using this function:
\r
2747 (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
2748 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
\r
2749 (#) Configure the Slave Timers using the following functions:
\r
2750 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
\r
2751 uint16_t TIM_InputTriggerSource);
\r
2752 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
\r
2758 * @brief Selects the Input Trigger source
\r
2759 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
2760 * @param TIM_InputTriggerSource: The Input Trigger source.
\r
2761 * This parameter can be one of the following values:
\r
2762 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
2763 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
2764 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
2765 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
2766 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
2767 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
2768 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
2769 * @arg TIM_TS_ETRF: External Trigger input
\r
2772 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
2774 uint16_t tmpsmcr = 0;
\r
2776 /* Check the parameters */
\r
2777 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2778 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
2780 /* Get the TIMx SMCR register value */
\r
2781 tmpsmcr = TIMx->SMCR;
\r
2782 /* Reset the TS Bits */
\r
2783 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
2784 /* Set the Input Trigger source */
\r
2785 tmpsmcr |= TIM_InputTriggerSource;
\r
2786 /* Write to TIMx SMCR */
\r
2787 TIMx->SMCR = tmpsmcr;
\r
2791 * @brief Selects the TIMx Trigger Output Mode.
\r
2792 * @param TIMx: where x can be 1, 2, 3, 6, or 15 to select the TIM peripheral.
\r
2793 * @param TIM_TRGOSource: specifies the Trigger Output source.
\r
2794 * This paramter can be one of the following values:
\r
2797 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
\r
2798 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
\r
2799 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
\r
2801 * For all TIMx except TIM6
\r
2802 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
\r
2803 * is to be set, as soon as a capture or compare match occurs (TRGO).
\r
2804 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
\r
2805 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
\r
2806 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
\r
2807 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
\r
2811 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
\r
2813 /* Check the parameters */
\r
2814 assert_param(IS_TIM_LIST9_PERIPH(TIMx));
\r
2815 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
\r
2817 /* Reset the MMS Bits */
\r
2818 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
\r
2819 /* Select the TRGO source */
\r
2820 TIMx->CR2 |= TIM_TRGOSource;
\r
2824 * @brief Selects the TIMx Slave Mode.
\r
2825 * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
\r
2826 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
\r
2827 * This paramter can be one of the following values:
\r
2828 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
\r
2829 * the counter and triggers an update of the registers.
\r
2830 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
\r
2831 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
\r
2832 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
\r
2835 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
\r
2837 /* Check the parameters */
\r
2838 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2839 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
\r
2841 /* Reset the SMS Bits */
\r
2842 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
\r
2843 /* Select the Slave Mode */
\r
2844 TIMx->SMCR |= TIM_SlaveMode;
\r
2848 * @brief Sets or Resets the TIMx Master/Slave Mode.
\r
2849 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
2850 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
\r
2851 * This paramter can be one of the following values:
\r
2852 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
\r
2853 * and its slaves (through TRGO).
\r
2854 * @arg TIM_MasterSlaveMode_Disable: No action
\r
2857 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
\r
2859 /* Check the parameters */
\r
2860 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2861 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
\r
2863 /* Reset the MSM Bit */
\r
2864 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
\r
2866 /* Set or Reset the MSM Bit */
\r
2867 TIMx->SMCR |= TIM_MasterSlaveMode;
\r
2871 * @brief Configures the TIMx External Trigger (ETR).
\r
2872 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2873 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2874 * This parameter can be one of the following values:
\r
2875 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2876 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2877 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2878 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2879 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2880 * This parameter can be one of the following values:
\r
2881 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2882 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2883 * @param ExtTRGFilter: External Trigger Filter.
\r
2884 * This parameter must be a value between 0x00 and 0x0F
\r
2887 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
2888 uint16_t ExtTRGFilter)
\r
2890 uint16_t tmpsmcr = 0;
\r
2892 /* Check the parameters */
\r
2893 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2894 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2895 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2896 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2898 tmpsmcr = TIMx->SMCR;
\r
2899 /* Reset the ETR Bits */
\r
2900 tmpsmcr &= SMCR_ETR_MASK;
\r
2901 /* Set the Prescaler, the Filter value and the Polarity */
\r
2902 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
\r
2903 /* Write to TIMx SMCR */
\r
2904 TIMx->SMCR = tmpsmcr;
\r
2911 /** @defgroup TIM_Group8 Specific interface management functions
\r
2912 * @brief Specific interface management functions
\r
2915 ===============================================================================
\r
2916 ##### Specific interface management functions #####
\r
2917 ===============================================================================
\r
2924 * @brief Configures the TIMx Encoder Interface.
\r
2925 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2926 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
\r
2927 * This parameter can be one of the following values:
\r
2928 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
\r
2929 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
\r
2930 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
\r
2931 * on the level of the other input.
\r
2932 * @param TIM_IC1Polarity: specifies the IC1 Polarity
\r
2933 * This parmeter can be one of the following values:
\r
2934 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
2935 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
2936 * @param TIM_IC2Polarity: specifies the IC2 Polarity
\r
2937 * This parmeter can be one of the following values:
\r
2938 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
2939 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
2942 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
2943 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
\r
2945 uint16_t tmpsmcr = 0;
\r
2946 uint16_t tmpccmr1 = 0;
\r
2947 uint16_t tmpccer = 0;
\r
2949 /* Check the parameters */
\r
2950 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2951 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
\r
2952 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
\r
2953 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
\r
2955 /* Get the TIMx SMCR register value */
\r
2956 tmpsmcr = TIMx->SMCR;
\r
2957 /* Get the TIMx CCMR1 register value */
\r
2958 tmpccmr1 = TIMx->CCMR1;
\r
2959 /* Get the TIMx CCER register value */
\r
2960 tmpccer = TIMx->CCER;
\r
2961 /* Set the encoder Mode */
\r
2962 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2963 tmpsmcr |= TIM_EncoderMode;
\r
2964 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
2965 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
\r
2966 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
\r
2967 /* Set the TI1 and the TI2 Polarities */
\r
2968 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
\r
2969 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
\r
2970 /* Write to TIMx SMCR */
\r
2971 TIMx->SMCR = tmpsmcr;
\r
2972 /* Write to TIMx CCMR1 */
\r
2973 TIMx->CCMR1 = tmpccmr1;
\r
2974 /* Write to TIMx CCER */
\r
2975 TIMx->CCER = tmpccer;
\r
2979 * @brief Enables or disables the TIMx's Hall sensor interface.
\r
2980 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
2981 * @param NewState: new state of the TIMx Hall sensor interface.
\r
2982 * This parameter can be: ENABLE or DISABLE.
\r
2985 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2987 /* Check the parameters */
\r
2988 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2989 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2991 if (NewState != DISABLE)
\r
2993 /* Set the TI1S Bit */
\r
2994 TIMx->CR2 |= TIM_CR2_TI1S;
\r
2998 /* Reset the TI1S Bit */
\r
2999 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
\r
3007 /** @defgroup TIM_Group9 Specific remapping management function
\r
3008 * @brief Specific remapping management function
\r
3011 ===============================================================================
\r
3012 ##### Specific remapping management function #####
\r
3013 ===============================================================================
\r
3019 * @brief Configures the TIM14 Remapping input Capabilities.
\r
3020 * @param TIMx: where x can be 14 to select the TIM peripheral.
\r
3021 * @param TIM_Remap: specifies the TIM input reampping source.
\r
3022 * This parameter can be one of the following values:
\r
3023 * @arg TIM14_GPIO : TIM14 Channel 1 is connected to GPIO.
\r
3024 * @arg TIM14_RTC_CLK : TIM14 Channel 1 is connected to RTC input clock.
\r
3025 * RTC input clock can be LSE, LSI or HSE/div128.
\r
3028 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
\r
3030 /* Check the parameters */
\r
3031 assert_param(IS_TIM_LIST11_PERIPH(TIMx));
\r
3032 assert_param(IS_TIM_REMAP(TIM_Remap));
\r
3034 /* Set the Timer remapping configuration */
\r
3035 TIMx->OR = TIM_Remap;
\r
3043 * @brief Configure the TI1 as Input.
\r
3044 * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
\r
3045 * @param TIM_ICPolarity : The Input Polarity.
\r
3046 * This parameter can be one of the following values:
\r
3047 * @arg TIM_ICPolarity_Rising
\r
3048 * @arg TIM_ICPolarity_Falling
\r
3049 * @param TIM_ICSelection: specifies the input to be used.
\r
3050 * This parameter can be one of the following values:
\r
3051 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
3052 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
3053 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
3054 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
3055 * This parameter must be a value between 0x00 and 0x0F.
\r
3058 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
3059 uint16_t TIM_ICFilter)
\r
3061 uint16_t tmpccmr1 = 0, tmpccer = 0;
\r
3062 /* Disable the Channel 1: Reset the CC1E Bit */
\r
3063 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
\r
3064 tmpccmr1 = TIMx->CCMR1;
\r
3065 tmpccer = TIMx->CCER;
\r
3066 /* Select the Input and set the filter */
\r
3067 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
\r
3068 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
3070 /* Select the Polarity and set the CC1E Bit */
\r
3071 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
\r
3072 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
\r
3073 /* Write to TIMx CCMR1 and CCER registers */
\r
3074 TIMx->CCMR1 = tmpccmr1;
\r
3075 TIMx->CCER = tmpccer;
\r
3079 * @brief Configure the TI2 as Input.
\r
3080 * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
\r
3081 * @param TIM_ICPolarity : The Input Polarity.
\r
3082 * This parameter can be one of the following values:
\r
3083 * @arg TIM_ICPolarity_Rising
\r
3084 * @arg TIM_ICPolarity_Falling
\r
3085 * @param TIM_ICSelection: specifies the input to be used.
\r
3086 * This parameter can be one of the following values:
\r
3087 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
3088 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
3089 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
3090 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
3091 * This parameter must be a value between 0x00 and 0x0F.
\r
3094 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
3095 uint16_t TIM_ICFilter)
\r
3097 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
\r
3098 /* Disable the Channel 2: Reset the CC2E Bit */
\r
3099 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
\r
3100 tmpccmr1 = TIMx->CCMR1;
\r
3101 tmpccer = TIMx->CCER;
\r
3102 tmp = (uint16_t)(TIM_ICPolarity << 4);
\r
3103 /* Select the Input and set the filter */
\r
3104 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
\r
3105 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
\r
3106 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
\r
3107 /* Select the Polarity and set the CC2E Bit */
\r
3108 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
\r
3109 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
\r
3110 /* Write to TIMx CCMR1 and CCER registers */
\r
3111 TIMx->CCMR1 = tmpccmr1 ;
\r
3112 TIMx->CCER = tmpccer;
\r
3116 * @brief Configure the TI3 as Input.
\r
3117 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
3118 * @param TIM_ICPolarity : The Input Polarity.
\r
3119 * This parameter can be one of the following values:
\r
3120 * @arg TIM_ICPolarity_Rising
\r
3121 * @arg TIM_ICPolarity_Falling
\r
3122 * @param TIM_ICSelection: specifies the input to be used.
\r
3123 * This parameter can be one of the following values:
\r
3124 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
3125 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
3126 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
3127 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
3128 * This parameter must be a value between 0x00 and 0x0F.
\r
3131 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
3132 uint16_t TIM_ICFilter)
\r
3134 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
3135 /* Disable the Channel 3: Reset the CC3E Bit */
\r
3136 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
\r
3137 tmpccmr2 = TIMx->CCMR2;
\r
3138 tmpccer = TIMx->CCER;
\r
3139 tmp = (uint16_t)(TIM_ICPolarity << 8);
\r
3140 /* Select the Input and set the filter */
\r
3141 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
\r
3142 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
3143 /* Select the Polarity and set the CC3E Bit */
\r
3144 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
\r
3145 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
\r
3146 /* Write to TIMx CCMR2 and CCER registers */
\r
3147 TIMx->CCMR2 = tmpccmr2;
\r
3148 TIMx->CCER = tmpccer;
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3152 * @brief Configure the TI4 as Input.
\r
3153 * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
\r
3154 * @param TIM_ICPolarity : The Input Polarity.
\r
3155 * This parameter can be one of the following values:
\r
3156 * @arg TIM_ICPolarity_Rising
\r
3157 * @arg TIM_ICPolarity_Falling
\r
3158 * @param TIM_ICSelection: specifies the input to be used.
\r
3159 * This parameter can be one of the following values:
\r
3160 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
3161 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
3162 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
3163 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
3164 * This parameter must be a value between 0x00 and 0x0F.
\r
3167 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
3168 uint16_t TIM_ICFilter)
\r
3170 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
3172 /* Disable the Channel 4: Reset the CC4E Bit */
\r
3173 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
\r
3174 tmpccmr2 = TIMx->CCMR2;
\r
3175 tmpccer = TIMx->CCER;
\r
3176 tmp = (uint16_t)(TIM_ICPolarity << 12);
\r
3177 /* Select the Input and set the filter */
\r
3178 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
\r
3179 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
\r
3180 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
\r
3181 /* Select the Polarity and set the CC4E Bit */
\r
3182 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
\r
3183 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
\r
3184 /* Write to TIMx CCMR2 and CCER registers */
\r
3185 TIMx->CCMR2 = tmpccmr2;
\r
3186 TIMx->CCER = tmpccer;
\r
3201 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
\r
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