1 /**************************************************************************//**
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2 * @file core_cm4_simd.h
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3 * @brief CMSIS Cortex-M4 SIMD Header File
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5 * @date 19. July 2011
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8 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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22 ******************************************************************************/
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28 #ifndef __CORE_CM4_SIMD_H
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29 #define __CORE_CM4_SIMD_H
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32 /*******************************************************************************
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33 * Hardware Abstraction Layer
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34 ******************************************************************************/
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37 /* ################### Compiler specific Intrinsics ########################### */
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38 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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39 Access to dedicated SIMD instructions
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43 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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44 /* ARM armcc specific functions */
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46 /*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
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47 #define __SADD8 __sadd8
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48 #define __QADD8 __qadd8
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49 #define __SHADD8 __shadd8
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50 #define __UADD8 __uadd8
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51 #define __UQADD8 __uqadd8
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52 #define __UHADD8 __uhadd8
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53 #define __SSUB8 __ssub8
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54 #define __QSUB8 __qsub8
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55 #define __SHSUB8 __shsub8
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56 #define __USUB8 __usub8
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57 #define __UQSUB8 __uqsub8
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58 #define __UHSUB8 __uhsub8
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59 #define __SADD16 __sadd16
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60 #define __QADD16 __qadd16
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61 #define __SHADD16 __shadd16
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62 #define __UADD16 __uadd16
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63 #define __UQADD16 __uqadd16
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64 #define __UHADD16 __uhadd16
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65 #define __SSUB16 __ssub16
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66 #define __QSUB16 __qsub16
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67 #define __SHSUB16 __shsub16
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68 #define __USUB16 __usub16
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69 #define __UQSUB16 __uqsub16
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70 #define __UHSUB16 __uhsub16
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71 #define __SASX __sasx
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72 #define __QASX __qasx
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73 #define __SHASX __shasx
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74 #define __UASX __uasx
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75 #define __UQASX __uqasx
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76 #define __UHASX __uhasx
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77 #define __SSAX __ssax
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78 #define __QSAX __qsax
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79 #define __SHSAX __shsax
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80 #define __USAX __usax
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81 #define __UQSAX __uqsax
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82 #define __UHSAX __uhsax
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83 #define __USAD8 __usad8
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84 #define __USADA8 __usada8
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85 #define __SSAT16 __ssat16
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86 #define __USAT16 __usat16
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87 #define __UXTB16 __uxtb16
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88 #define __UXTAB16 __uxtab16
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89 #define __SXTB16 __sxtb16
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90 #define __SXTAB16 __sxtab16
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91 #define __SMUAD __smuad
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92 #define __SMUADX __smuadx
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93 #define __SMLAD __smlad
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94 #define __SMLADX __smladx
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95 #define __SMLALD __smlald
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96 #define __SMLALDX __smlaldx
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97 #define __SMUSD __smusd
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98 #define __SMUSDX __smusdx
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99 #define __SMLSD __smlsd
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100 #define __SMLSDX __smlsdx
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101 #define __SMLSLD __smlsld
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102 #define __SMLSLDX __smlsldx
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103 #define __SEL __sel
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104 #define __QADD __qadd
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105 #define __QSUB __qsub
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107 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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108 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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110 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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111 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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114 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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118 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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119 /* IAR iccarm specific functions */
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121 #include <cmsis_iar.h>
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123 /*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
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124 /* intrinsic __SADD8 see intrinsics.h */
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125 /* intrinsic __QADD8 see intrinsics.h */
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126 /* intrinsic __SHADD8 see intrinsics.h */
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127 /* intrinsic __UADD8 see intrinsics.h */
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128 /* intrinsic __UQADD8 see intrinsics.h */
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129 /* intrinsic __UHADD8 see intrinsics.h */
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130 /* intrinsic __SSUB8 see intrinsics.h */
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131 /* intrinsic __QSUB8 see intrinsics.h */
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132 /* intrinsic __SHSUB8 see intrinsics.h */
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133 /* intrinsic __USUB8 see intrinsics.h */
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134 /* intrinsic __UQSUB8 see intrinsics.h */
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135 /* intrinsic __UHSUB8 see intrinsics.h */
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136 /* intrinsic __SADD16 see intrinsics.h */
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137 /* intrinsic __QADD16 see intrinsics.h */
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138 /* intrinsic __SHADD16 see intrinsics.h */
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139 /* intrinsic __UADD16 see intrinsics.h */
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140 /* intrinsic __UQADD16 see intrinsics.h */
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141 /* intrinsic __UHADD16 see intrinsics.h */
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142 /* intrinsic __SSUB16 see intrinsics.h */
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143 /* intrinsic __QSUB16 see intrinsics.h */
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144 /* intrinsic __SHSUB16 see intrinsics.h */
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145 /* intrinsic __USUB16 see intrinsics.h */
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146 /* intrinsic __UQSUB16 see intrinsics.h */
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147 /* intrinsic __UHSUB16 see intrinsics.h */
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148 /* intrinsic __SASX see intrinsics.h */
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149 /* intrinsic __QASX see intrinsics.h */
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150 /* intrinsic __SHASX see intrinsics.h */
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151 /* intrinsic __UASX see intrinsics.h */
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152 /* intrinsic __UQASX see intrinsics.h */
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153 /* intrinsic __UHASX see intrinsics.h */
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154 /* intrinsic __SSAX see intrinsics.h */
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155 /* intrinsic __QSAX see intrinsics.h */
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156 /* intrinsic __SHSAX see intrinsics.h */
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157 /* intrinsic __USAX see intrinsics.h */
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158 /* intrinsic __UQSAX see intrinsics.h */
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159 /* intrinsic __UHSAX see intrinsics.h */
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160 /* intrinsic __USAD8 see intrinsics.h */
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161 /* intrinsic __USADA8 see intrinsics.h */
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162 /* intrinsic __SSAT16 see intrinsics.h */
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163 /* intrinsic __USAT16 see intrinsics.h */
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164 /* intrinsic __UXTB16 see intrinsics.h */
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165 /* intrinsic __SXTB16 see intrinsics.h */
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166 /* intrinsic __UXTAB16 see intrinsics.h */
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167 /* intrinsic __SXTAB16 see intrinsics.h */
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168 /* intrinsic __SMUAD see intrinsics.h */
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169 /* intrinsic __SMUADX see intrinsics.h */
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170 /* intrinsic __SMLAD see intrinsics.h */
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171 /* intrinsic __SMLADX see intrinsics.h */
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172 /* intrinsic __SMLALD see intrinsics.h */
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173 /* intrinsic __SMLALDX see intrinsics.h */
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174 /* intrinsic __SMUSD see intrinsics.h */
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175 /* intrinsic __SMUSDX see intrinsics.h */
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176 /* intrinsic __SMLSD see intrinsics.h */
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177 /* intrinsic __SMLSDX see intrinsics.h */
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178 /* intrinsic __SMLSLD see intrinsics.h */
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179 /* intrinsic __SMLSLDX see intrinsics.h */
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180 /* intrinsic __SEL see intrinsics.h */
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181 /* intrinsic __QADD see intrinsics.h */
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182 /* intrinsic __QSUB see intrinsics.h */
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183 /* intrinsic __PKHBT see intrinsics.h */
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184 /* intrinsic __PKHTB see intrinsics.h */
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186 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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190 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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191 /* GNU gcc specific functions */
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193 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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194 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
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198 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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202 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
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206 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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210 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
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214 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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218 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
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222 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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226 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
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230 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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234 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
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238 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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243 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
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247 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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251 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
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255 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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259 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
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263 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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267 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
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271 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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275 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
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279 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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283 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
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287 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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292 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
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296 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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300 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
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304 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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308 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
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312 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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316 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
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320 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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324 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
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328 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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332 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
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336 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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340 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
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344 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
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352 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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356 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
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360 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
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368 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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372 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
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376 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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380 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
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384 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
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392 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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396 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
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400 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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404 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
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408 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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412 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
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416 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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420 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
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424 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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428 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
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432 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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436 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
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440 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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444 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
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448 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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452 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
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456 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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460 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
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464 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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468 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
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472 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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476 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
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480 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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484 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
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488 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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492 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
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496 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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500 #define __SSAT16(ARG1,ARG2) \
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502 uint32_t __RES, __ARG1 = (ARG1); \
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503 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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507 #define __USAT16(ARG1,ARG2) \
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509 uint32_t __RES, __ARG1 = (ARG1); \
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510 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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514 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
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518 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
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522 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
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526 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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530 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
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534 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
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538 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
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542 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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546 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
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550 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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554 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
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558 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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562 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
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566 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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570 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
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574 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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578 #define __SMLALD(ARG1,ARG2,ARG3) \
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580 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
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581 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
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582 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
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585 #define __SMLALDX(ARG1,ARG2,ARG3) \
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587 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
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588 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
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589 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
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592 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
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596 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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600 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
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604 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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608 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
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612 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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616 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
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620 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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624 #define __SMLSLD(ARG1,ARG2,ARG3) \
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626 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
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627 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
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628 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
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631 #define __SMLSLDX(ARG1,ARG2,ARG3) \
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633 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
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634 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
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635 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
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638 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
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642 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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646 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
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650 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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654 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
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658 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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662 #define __PKHBT(ARG1,ARG2,ARG3) \
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664 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
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665 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
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669 #define __PKHTB(ARG1,ARG2,ARG3) \
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671 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
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673 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
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675 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
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679 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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683 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
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684 /* TASKING carm specific functions */
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687 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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688 /* not yet supported */
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689 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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694 /*@} end of group CMSIS_SIMD_intrinsics */
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697 #endif /* __CORE_CM4_SIMD_H */
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