git.sur5r.net Git - freertos/blob - Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/startup_keil/startup_mb9bf50x.s

   1 ;/************************************************************************/\r
   2 ;/*               (C) Fujitsu Semiconductor Europe GmbH                  */\r
   3 ;/*                                                                      */\r
   4 ;/* The following software deliverable is intended for and must only be  */\r
   5 ;/* used for reference and in an evaluation laboratory environment.      */\r
   6 ;/* It is provided on an as-is basis without charge and is subject to    */\r
   7 ;/* alterations.                                                         */\r
   8 ;/* It is the user\92s obligation to fully test the software in its        */\r
   9 ;/* environment and to ensure proper functionality, qualification and    */\r
  10 ;/* compliance with component specifications.                            */\r
  11 ;/*                                                                      */\r
  12 ;/* In the event the software deliverable includes the use of open       */\r
  13 ;/* source components, the provisions of the governing open source       */\r
  14 ;/* license agreement shall apply with respect to such software          */\r
  15 ;/* deliverable.                                                         */\r
  16 ;/* FSEU does not warrant that the deliverables do not infringe any      */\r
  17 ;/* third party intellectual property right (IPR). In the event that     */\r
  18 ;/* the deliverables infringe a third party IPR it is the sole           */\r
  19 ;/* responsibility of the customer to obtain necessary licenses to       */\r
  20 ;/* continue the usage of the deliverable.                               */\r
  21 ;/*                                                                      */\r
  22 ;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
  23 ;/* warranties, whether express or implied, in particular, but not       */\r
  24 ;/* limited to, warranties of merchantability and fitness for a          */\r
  25 ;/* particular purpose for which the deliverable is not designated.      */\r
  26 ;/*                                                                      */\r
  27 ;/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
  28 ;/* is restricted to intention and gross negligence.                     */\r
  29 ;/* FSEU is not liable for consequential damages.                        */\r
  30 ;/*                                                                      */\r
  31 ;/* (V1.4)                                                               */\r
  32 ;/************************************************************************/\r
  33 ;/*  Startup for ARM                                                     */\r
  34 ;/*  Version     V1.02                                                   */\r
  35 ;/*  Date        2011-01-12                                              */\r
  36 ;/*  Target-mcu  MB9B5xx                                                 */\r
  37 ;/************************************************************************/\r
  38 \r
  39 ; Stack Configuration\r
  40 ;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  41 \r
  42 Stack_Size      EQU     0x00000200\r
  43 \r
  44                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  45 Stack_Mem       SPACE   Stack_Size\r
  46 __initial_sp\r
  47 \r
  48 \r
  49 ; Heap Configuration\r
  50 ;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  51 \r
  52 Heap_Size       EQU     0x00000000\r
  53 \r
  54                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  55 __heap_base\r
  56 Heap_Mem        SPACE   Heap_Size\r
  57 __heap_limit\r
  58 \r
  59 \r
  60                 PRESERVE8\r
  61                 THUMB\r
  62 \r
  63 \r
  64 ; Vector Table Mapped to Address 0 at Reset\r
  65 \r
  66                 AREA    RESET, DATA, READONLY\r
  67                 EXPORT  __Vectors\r
  68                 EXPORT  __Vectors_End\r
  69                 EXPORT  __Vectors_Size\r
  70 \r
  71 __Vectors       DCD     __initial_sp              ; Top of Stack\r
  72                 DCD     Reset_Handler             ; Reset Handler\r
  73                 DCD     NMI_Handler               ; NMI Handler\r
  74                 DCD     HardFault_Handler         ; Hard Fault Handler\r
  75                 DCD     MemManage_Handler         ; MPU Fault Handler\r
  76                 DCD     BusFault_Handler          ; Bus Fault Handler\r
  77                 DCD     UsageFault_Handler        ; Usage Fault Handler\r
  78                 DCD     0                         ; Reserved\r
  79                 DCD     0                         ; Reserved\r
  80                 DCD     0                         ; Reserved\r
  81                 DCD     0                         ; Reserved\r
  82                 DCD     SVC_Handler               ; SVCall Handler\r
  83                 DCD     DebugMon_Handler          ; Debug Monitor Handler\r
  84                 DCD     0                         ; Reserved\r
  85                 DCD     PendSV_Handler            ; PendSV Handler\r
  86                 DCD     SysTick_Handler           ; SysTick Handler\r
  87 \r
  88                 DCD     CSV_Handler               ; 0: Clock Super Visor\r
  89                 DCD     SWDT_Handler              ; 1: Software Watchdog Timer\r
  90                 DCD     LVD_Handler               ; 2: Low Voltage Detector\r
  91                 DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF\r
  92                 DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7\r
  93                 DCD     INT8_15_Handler           ; 5: External Interrupt Request ch.8 to ch.15\r
  94                 DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder\r
  95                 DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0\r
  96                 DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0\r
  97                 DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1\r
  98                 DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1\r
  99                 DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2\r
 100                 DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2\r
 101                 DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3\r
 102                 DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3\r
 103                 DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4\r
 104                 DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4\r
 105                 DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5\r
 106                 DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5\r
 107                 DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6\r
 108                 DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6\r
 109                 DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7\r
 110                 DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7\r
 111                 DCD     PPG_Handler               ; 23: PPG\r
 112                 DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter\r
 113                 DCD     ADC0_IRQHandler           ; 25: ADC0\r
 114                 DCD     ADC1_IRQHandler           ; 26: ADC1\r
 115                 DCD     ADC2_IRQHandler           ; 27: ADC2\r
 116                 DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer\r
 117                 DCD     MFT_IPC_IRQHandler        ; 29: Input Capture\r
 118                 DCD     MFT_OPC_IRQHandler        ; 30: Output Compare\r
 119                 DCD     BT_IRQHandler             ; 31: Base Timer ch.0 to ch.7\r
 120                 DCD     CAN0_IRQHandler           ; 32: CAN ch.0\r
 121                 DCD     CAN1_IRQHandler           ; 33: CAN ch.1\r
 122                 DCD     USBF_Handler              ; 34: USB Function\r
 123                 DCD     USB_Handler               ; 35: USB Function / USB HOST\r
 124                 DCD     DummyHandler              ; 36: Reserved\r
 125                 DCD     DummyHandler              ; 37: Reserved\r
 126                 DCD     DMAC0_Handler             ; 38: DMAC ch.0\r
 127                 DCD     DMAC1_Handler             ; 39: DMAC ch.1\r
 128                 DCD     DMAC2_Handler             ; 40: DMAC ch.2\r
 129                 DCD     DMAC3_Handler             ; 41: DMAC ch.3\r
 130                 DCD     DMAC4_Handler             ; 42: DMAC ch.4\r
 131                 DCD     DMAC5_Handler             ; 43: DMAC ch.5\r
 132                 DCD     DMAC6_Handler             ; 44: DMAC ch.6\r
 133                 DCD     DMAC7_Handler             ; 45: DMAC ch.7\r
 134                 DCD     DummyHandler              ; 46: Reserved\r
 135                 DCD     DummyHandler              ; 47: Reserved\r
 136 __Vectors_End\r
 137 \r
 138 __Vectors_Size  EQU     __Vectors_End - __Vectors\r
 139 \r
 140                 AREA    |.text|, CODE, READONLY\r
 141 \r
 142 \r
 143 ; Reset Handler\r
 144 \r
 145 Reset_Handler   PROC\r
 146                 EXPORT  Reset_Handler             [WEAK]\r
 147                 IMPORT  SystemInit\r
 148                 IMPORT  __main\r
 149                 LDR     R0, =SystemInit\r
 150                 BLX     R0\r
 151                 LDR     R0, =__main\r
 152                 BX      R0\r
 153                 ENDP\r
 154 \r
 155 \r
 156 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 157 \r
 158 NMI_Handler     PROC\r
 159                 EXPORT  NMI_Handler               [WEAK]\r
 160                 B       .\r
 161                 ENDP\r
 162 HardFault_Handler\\r
 163                 PROC\r
 164                 EXPORT  HardFault_Handler         [WEAK]\r
 165                 B       .\r
 166                 ENDP\r
 167 MemManage_Handler\\r
 168                 PROC\r
 169                 EXPORT  MemManage_Handler         [WEAK]\r
 170                 B       .\r
 171                 ENDP\r
 172 BusFault_Handler\\r
 173                 PROC\r
 174                 EXPORT  BusFault_Handler          [WEAK]\r
 175                 B       .\r
 176                 ENDP\r
 177 UsageFault_Handler\\r
 178                 PROC\r
 179                 EXPORT  UsageFault_Handler        [WEAK]\r
 180                 B       .\r
 181                 ENDP\r
 182 SVC_Handler     PROC\r
 183                 EXPORT  SVC_Handler               [WEAK]\r
 184                 B       .\r
 185                 ENDP\r
 186 DebugMon_Handler\\r
 187                 PROC\r
 188                 EXPORT  DebugMon_Handler          [WEAK]\r
 189                 B       .\r
 190                 ENDP\r
 191 PendSV_Handler  PROC\r
 192                 EXPORT  PendSV_Handler            [WEAK]\r
 193                 B       .\r
 194                 ENDP\r
 195 SysTick_Handler PROC\r
 196                 EXPORT  SysTick_Handler           [WEAK]\r
 197                 B       .\r
 198                 ENDP\r
 199 \r
 200 Default_Handler PROC\r
 201 \r
 202                 EXPORT  CSV_Handler                   [WEAK]\r
 203                 EXPORT  SWDT_Handler              [WEAK]\r
 204                 EXPORT  LVD_Handler               [WEAK]\r
 205                 EXPORT  MFT_WG_IRQHandler         [WEAK]\r
 206                 EXPORT  INT0_7_Handler            [WEAK]\r
 207                 EXPORT  INT8_15_Handler           [WEAK]\r
 208                 EXPORT  DT_Handler                [WEAK]\r
 209                 EXPORT  MFS0RX_IRQHandler         [WEAK]\r
 210                 EXPORT  MFS0TX_IRQHandler         [WEAK]\r
 211                 EXPORT  MFS1RX_IRQHandler         [WEAK]\r
 212                 EXPORT  MFS1TX_IRQHandler         [WEAK]\r
 213                 EXPORT  MFS2RX_IRQHandler         [WEAK]\r
 214                 EXPORT  MFS2TX_IRQHandler         [WEAK]\r
 215                 EXPORT  MFS3RX_IRQHandler         [WEAK]\r
 216                 EXPORT  MFS3TX_IRQHandler         [WEAK]\r
 217                 EXPORT  MFS4RX_IRQHandler         [WEAK]\r
 218                 EXPORT  MFS4TX_IRQHandler         [WEAK]\r
 219                 EXPORT  MFS5RX_IRQHandler         [WEAK]\r
 220                 EXPORT  MFS5TX_IRQHandler         [WEAK]\r
 221                 EXPORT  MFS6RX_IRQHandler         [WEAK]\r
 222                 EXPORT  MFS6TX_IRQHandler         [WEAK]\r
 223                 EXPORT  MFS7RX_IRQHandler         [WEAK]\r
 224                 EXPORT  MFS7TX_IRQHandler         [WEAK]\r
 225                 EXPORT  PPG_Handler               [WEAK]\r
 226                 EXPORT  TIM_IRQHandler            [WEAK]\r
 227                 EXPORT  ADC0_IRQHandler           [WEAK]\r
 228                 EXPORT  ADC1_IRQHandler           [WEAK]\r
 229                 EXPORT  ADC2_IRQHandler           [WEAK]\r
 230                 EXPORT  MFT_FRT_IRQHandler        [WEAK]\r
 231                 EXPORT  MFT_IPC_IRQHandler        [WEAK]\r
 232                 EXPORT  MFT_OPC_IRQHandler        [WEAK]\r
 233                 EXPORT  BT_IRQHandler             [WEAK]\r
 234                 EXPORT  CAN0_IRQHandler           [WEAK]\r
 235                 EXPORT  CAN1_IRQHandler           [WEAK]\r
 236                 EXPORT  USBF_Handler              [WEAK]\r
 237                 EXPORT  USB_Handler               [WEAK]\r
 238                 EXPORT  DMAC0_Handler             [WEAK]\r
 239                 EXPORT  DMAC1_Handler             [WEAK]\r
 240                 EXPORT  DMAC2_Handler             [WEAK]\r
 241                 EXPORT  DMAC3_Handler             [WEAK]\r
 242                 EXPORT  DMAC4_Handler             [WEAK]\r
 243                 EXPORT  DMAC5_Handler             [WEAK]\r
 244                 EXPORT  DMAC6_Handler             [WEAK]\r
 245                 EXPORT  DMAC7_Handler             [WEAK]\r
 246                 EXPORT  DummyHandler              [WEAK]\r
 247 \r
 248 CSV_Handler\r
 249 SWDT_Handler\r
 250 LVD_Handler\r
 251 MFT_WG_IRQHandler\r
 252 INT0_7_Handler\r
 253 INT8_15_Handler\r
 254 DT_Handler\r
 255 MFS0RX_IRQHandler\r
 256 MFS0TX_IRQHandler\r
 257 MFS1RX_IRQHandler\r
 258 MFS1TX_IRQHandler\r
 259 MFS2RX_IRQHandler\r
 260 MFS2TX_IRQHandler\r
 261 MFS3RX_IRQHandler\r
 262 MFS3TX_IRQHandler\r
 263 MFS4RX_IRQHandler\r
 264 MFS4TX_IRQHandler\r
 265 MFS5RX_IRQHandler\r
 266 MFS5TX_IRQHandler\r
 267 MFS6RX_IRQHandler\r
 268 MFS6TX_IRQHandler\r
 269 MFS7RX_IRQHandler\r
 270 MFS7TX_IRQHandler\r
 271 PPG_Handler\r
 272 TIM_IRQHandler\r
 273 ADC0_IRQHandler\r
 274 ADC1_IRQHandler\r
 275 ADC2_IRQHandler\r
 276 MFT_FRT_IRQHandler\r
 277 MFT_IPC_IRQHandler\r
 278 MFT_OPC_IRQHandler\r
 279 BT_IRQHandler\r
 280 CAN0_IRQHandler\r
 281 CAN1_IRQHandler\r
 282 USBF_Handler\r
 283 USB_Handler\r
 284 DMAC0_Handler\r
 285 DMAC1_Handler\r
 286 DMAC2_Handler\r
 287 DMAC3_Handler\r
 288 DMAC4_Handler\r
 289 DMAC5_Handler\r
 290 DMAC6_Handler\r
 291 DMAC7_Handler\r
 292 DummyHandler\r
 293 \r
 294                 B       .\r
 295 \r
 296                 ENDP\r
 297 \r
 298 \r
 299                 ALIGN\r
 300 \r
 301 \r
 302 ; User Initial Stack & Heap\r
 303 \r
 304                 IF      :DEF:__MICROLIB\r
 305                 \r
 306                 EXPORT  __initial_sp\r
 307                 EXPORT  __heap_base\r
 308                 EXPORT  __heap_limit\r
 309                 \r
 310                 ELSE\r
 311                 \r
 312                 IMPORT  __use_two_region_memory\r
 313                 EXPORT  __user_initial_stackheap\r
 314 __user_initial_stackheap\r
 315 \r
 316                 LDR     R0, =  Heap_Mem\r
 317                 LDR     R1, =(Stack_Mem + Stack_Size)\r
 318                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
 319                 LDR     R3, = Stack_Mem\r
 320                 BX      LR\r
 321 \r
 322                 ALIGN\r
 323 \r
 324                 ENDIF\r
 325 \r
 326 \r
 327                 END\r