1 /*****************************************************************************
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2 * Copyright (c) 2006 Rowley Associates Limited. *
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4 * This file may be distributed under the terms of the License Agreement *
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5 * provided with this software. *
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7 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
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8 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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9 *****************************************************************************/
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11 /*****************************************************************************
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12 * Preprocessor Definitions
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13 * ------------------------
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15 * STARTUP_FROM_RESET
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17 * If defined, the program will startup from power-on/reset. If not defined
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18 * the program will just loop endlessly from power-on/reset.
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20 * This definition is not defined by default on this target because the
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21 * debugger is unable to reset this target and maintain control of it over the
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22 * JTAG interface. The advantage of doing this is that it allows the debugger
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23 * to reset the CPU and run programs from a known reset CPU state on each run.
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24 * It also acts as a safety net if you accidently download a program in FLASH
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25 * that crashes and prevents the debugger from taking control over JTAG
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26 * rendering the target unusable over JTAG. The obvious disadvantage of doing
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27 * this is that your application will not startup without the debugger.
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29 * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst
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30 * you are developing and only define STARTUP_FROM_RESET when development is
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33 *****************************************************************************/
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35 .extern xPortPendSVHandler
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36 .extern xPortSysTickHandler
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37 .extern vPortSVCHandler
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39 .global reset_handler
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41 .macro DEFAULT_ISR_HANDLER name=
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45 1: b 1b /* endless loop */
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48 .section .vectors, "ax"
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55 #ifdef STARTUP_FROM_RESET
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59 #endif /* STARTUP_FROM_RESET */
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63 .word 0 /* Populate if using Bus fault */
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64 .word 0 /* Populate if using Usage fault */
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65 .word 0 /* Reserved */
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66 .word 0 /* Reserved */
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67 .word 0 /* Reserved */
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68 .word 0 /* Reserved */
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69 .word vPortSVCHandler
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70 .word 0 /* Populate if using a debug monitor */
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71 .word 0 /* Reserved */
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72 .word xPortPendSVHandler
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73 .word xPortSysTickHandler
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74 .word GPIO_Port_A_ISR
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75 .word GPIO_Port_B_ISR
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76 .word GPIO_Port_C_ISR
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77 .word GPIO_Port_D_ISR
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78 .word GPIO_Port_E_ISR
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84 .word PWM_Generator_0_ISR
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85 .word PWM_Generator_1_ISR
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86 .word PWM_Generator_2_ISR
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88 .word ADC_Sequence_0_ISR
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89 .word ADC_Sequence_1_ISR
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90 .word ADC_Sequence_2_ISR
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91 .word ADC_Sequence_3_ISR
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92 .word Watchdog_Timer_ISR
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99 .word Analog_Comparator_0_ISR
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100 .word Analog_Comparator_1_ISR
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101 .word Analog_Comparator_2_ISR
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102 .word System_Control_ISR
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103 .word FLASH_Control_ISR
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104 .word GPIO_Port_F_ISR
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105 .word GPIO_Port_G_ISR
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106 .word GPIO_Port_H_ISR
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117 .word HIBERNATE_ISR
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119 .word PWM_Generator_3_ISR
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120 .word uDMA_Software_Transfer_ISR
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121 .word uDMA_Error_ISR
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124 .section .init, "ax"
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129 /* If this is a RAM build, configure vector table offset register to point
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130 to the RAM vector table. */
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131 ldr r0, =0xE000ED08
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137 DEFAULT_ISR_HANDLER Nmi_ISR
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138 /*DEFAULT_ISR_HANDLER Fault_ISR*/
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139 /*DEFAULT_ISR_HANDLER MPU_Fault_ISR*/
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140 DEFAULT_ISR_HANDLER SVCall_ISR
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141 DEFAULT_ISR_HANDLER SysTick_ISR
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142 DEFAULT_ISR_HANDLER PendSV_ISR
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143 DEFAULT_ISR_HANDLER GPIO_Port_A_ISR
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144 DEFAULT_ISR_HANDLER GPIO_Port_B_ISR
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145 DEFAULT_ISR_HANDLER GPIO_Port_C_ISR
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146 DEFAULT_ISR_HANDLER GPIO_Port_D_ISR
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147 DEFAULT_ISR_HANDLER GPIO_Port_E_ISR
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148 DEFAULT_ISR_HANDLER UART0_ISR
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149 DEFAULT_ISR_HANDLER UART1_ISR
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150 DEFAULT_ISR_HANDLER SSI_ISR
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151 DEFAULT_ISR_HANDLER I2C_ISR
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152 DEFAULT_ISR_HANDLER PWM_Fault_ISR
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153 DEFAULT_ISR_HANDLER PWM_Generator_0_ISR
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154 DEFAULT_ISR_HANDLER PWM_Generator_1_ISR
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155 DEFAULT_ISR_HANDLER PWM_Generator_2_ISR
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156 DEFAULT_ISR_HANDLER QEI_ISR
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157 DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR
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158 DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR
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159 DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR
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160 DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR
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161 DEFAULT_ISR_HANDLER Watchdog_Timer_ISR
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162 DEFAULT_ISR_HANDLER Timer0A_ISR
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163 DEFAULT_ISR_HANDLER Timer0B_ISR
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164 DEFAULT_ISR_HANDLER Timer1A_ISR
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165 DEFAULT_ISR_HANDLER Timer1B_ISR
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166 DEFAULT_ISR_HANDLER Timer2A_ISR
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167 DEFAULT_ISR_HANDLER Timer2B_ISR
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168 DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR
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169 DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR
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170 DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
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171 DEFAULT_ISR_HANDLER System_Control_ISR
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172 DEFAULT_ISR_HANDLER FLASH_Control_ISR
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173 DEFAULT_ISR_HANDLER GPIO_Port_F_ISR
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174 DEFAULT_ISR_HANDLER GPIO_Port_G_ISR
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175 DEFAULT_ISR_HANDLER GPIO_Port_H_ISR
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176 DEFAULT_ISR_HANDLER UART2_ISR
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177 DEFAULT_ISR_HANDLER SSI1_ISR
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178 DEFAULT_ISR_HANDLER Timer3A_ISR
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179 DEFAULT_ISR_HANDLER Timer3B_ISR
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180 DEFAULT_ISR_HANDLER I2C1_ISR
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181 DEFAULT_ISR_HANDLER QEI1_ISR
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182 DEFAULT_ISR_HANDLER CAN0_ISR
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183 DEFAULT_ISR_HANDLER CAN1_ISR
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184 DEFAULT_ISR_HANDLER CAN2_ISR
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185 DEFAULT_ISR_HANDLER ETHERNET_ISR
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186 DEFAULT_ISR_HANDLER HIBERNATE_ISR
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187 DEFAULT_ISR_HANDLER USB0_ISR
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188 DEFAULT_ISR_HANDLER PWM_Generator_3_ISR
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189 DEFAULT_ISR_HANDLER uDMA_Software_Transfer_ISR
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190 DEFAULT_ISR_HANDLER uDMA_Error_ISR
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191 DEFAULT_ISR_HANDLER EMAC_ISR
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193 #ifndef STARTUP_FROM_RESET
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194 DEFAULT_ISR_HANDLER reset_wait
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195 #endif /* STARTUP_FROM_RESET */
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