2 ******************************************************************************
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3 * @file stm32l1xx_tim.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the TIM firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32l1xx_tim.h"
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23 #include "stm32l1xx_rcc.h"
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25 /** @addtogroup STM32L1xx_StdPeriph_Driver
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30 * @brief TIM driver modules
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34 /** @defgroup TIM_Private_TypesDefinitions
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42 /** @defgroup TIM_Private_Defines
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46 /* ---------------------- TIM registers bit mask ------------------------ */
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47 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
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48 #define CCMR_OFFSET ((uint16_t)0x0018)
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49 #define CCER_CCE_SET ((uint16_t)0x0001)
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55 /** @defgroup TIM_Private_Macros
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63 /** @defgroup TIM_Private_Variables
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71 /** @defgroup TIM_Private_FunctionPrototypes
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75 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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76 uint16_t TIM_ICFilter);
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77 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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78 uint16_t TIM_ICFilter);
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79 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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80 uint16_t TIM_ICFilter);
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81 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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82 uint16_t TIM_ICFilter);
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87 /** @defgroup TIM_Private_Macros
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95 /** @defgroup TIM_Private_Variables
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103 /** @defgroup TIM_Private_FunctionPrototypes
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111 /** @defgroup TIM_Private_Functions
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116 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
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117 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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121 void TIM_DeInit(TIM_TypeDef* TIMx)
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123 /* Check the parameters */
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124 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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128 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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131 else if (TIMx == TIM3)
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133 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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134 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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136 else if (TIMx == TIM4)
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138 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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139 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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142 else if (TIMx == TIM6)
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144 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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147 else if (TIMx == TIM7)
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149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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153 else if (TIMx == TIM9)
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155 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
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156 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
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158 else if (TIMx == TIM10)
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160 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
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161 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
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167 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
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168 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
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175 * @brief Initializes the TIMx Time Base Unit peripheral according to
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176 * the specified parameters in the TIM_TimeBaseInitStruct.
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177 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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178 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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179 * structure that contains the configuration information for
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180 * the specified TIM peripheral.
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183 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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185 uint16_t tmpcr1 = 0;
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187 /* Check the parameters */
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188 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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189 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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190 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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192 tmpcr1 = TIMx->CR1;
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194 if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))
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196 /* Select the Counter Mode */
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197 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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198 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
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201 if(((TIMx) != TIM6) && ((TIMx) != TIM7))
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203 /* Set the clock division */
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204 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
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205 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
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208 TIMx->CR1 = tmpcr1;
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210 /* Set the Autoreload value */
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211 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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213 /* Set the Prescaler value */
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214 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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216 /* Generate an update event to reload the Prescaler value immediatly */
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217 TIMx->EGR = TIM_PSCReloadMode_Immediate;
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221 * @brief Initializes the TIMx Channel1 according to the specified
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222 * parameters in the TIM_OCInitStruct.
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223 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
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224 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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225 * that contains the configuration information for the specified TIM
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229 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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231 uint16_t tmpccmrx = 0, tmpccer = 0;
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233 /* Check the parameters */
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234 assert_param(IS_TIM_23491011_PERIPH(TIMx));
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235 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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236 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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237 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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238 /* Disable the Channel 1: Reset the CC1E Bit */
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239 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
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241 /* Get the TIMx CCER register value */
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242 tmpccer = TIMx->CCER;
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244 /* Get the TIMx CCMR1 register value */
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245 tmpccmrx = TIMx->CCMR1;
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247 /* Reset the Output Compare Mode Bits */
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248 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
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249 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
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251 /* Select the Output Compare Mode */
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252 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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254 /* Reset the Output Polarity level */
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255 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
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256 /* Set the Output Compare Polarity */
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257 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
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259 /* Set the Output State */
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260 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
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262 /* Set the Capture Compare Register value */
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263 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
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265 /* Write to TIMx CCMR1 */
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266 TIMx->CCMR1 = tmpccmrx;
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268 /* Write to TIMx CCER */
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269 TIMx->CCER = tmpccer;
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273 * @brief Initializes the TIMx Channel2 according to the specified
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274 * parameters in the TIM_OCInitStruct.
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275 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
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276 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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277 * that contains the configuration information for the specified TIM
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281 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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283 uint16_t tmpccmrx = 0, tmpccer = 0;
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285 /* Check the parameters */
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286 assert_param(IS_TIM_2349_PERIPH(TIMx));
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287 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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288 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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289 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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290 /* Disable the Channel 2: Reset the CC2E Bit */
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291 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
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293 /* Get the TIMx CCER register value */
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294 tmpccer = TIMx->CCER;
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296 /* Get the TIMx CCMR1 register value */
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297 tmpccmrx = TIMx->CCMR1;
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299 /* Reset the Output Compare Mode Bits */
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300 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
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302 /* Select the Output Compare Mode */
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303 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
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305 /* Reset the Output Polarity level */
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306 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
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307 /* Set the Output Compare Polarity */
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308 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
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310 /* Set the Output State */
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311 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
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313 /* Set the Capture Compare Register value */
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314 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
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316 /* Write to TIMx CCMR1 */
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317 TIMx->CCMR1 = tmpccmrx;
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319 /* Write to TIMx CCER */
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320 TIMx->CCER = tmpccer;
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324 * @brief Initializes the TIMx Channel3 according to the specified
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325 * parameters in the TIM_OCInitStruct.
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326 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
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327 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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328 * that contains the configuration information for the specified TIM
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332 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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334 uint16_t tmpccmrx = 0, tmpccer = 0;
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336 /* Check the parameters */
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337 assert_param(IS_TIM_234_PERIPH(TIMx));
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338 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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339 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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340 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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342 /* Disable the Channel 2: Reset the CC2E Bit */
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343 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
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345 /* Get the TIMx CCER register value */
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346 tmpccer = TIMx->CCER;
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348 /* Get the TIMx CCMR2 register value */
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349 tmpccmrx = TIMx->CCMR2;
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351 /* Reset the Output Compare Mode Bits */
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352 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
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354 /* Select the Output Compare Mode */
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355 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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357 /* Reset the Output Polarity level */
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358 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
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359 /* Set the Output Compare Polarity */
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360 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
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362 /* Set the Output State */
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363 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
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365 /* Set the Capture Compare Register value */
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366 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
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368 /* Write to TIMx CCMR2 */
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369 TIMx->CCMR2 = tmpccmrx;
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371 /* Write to TIMx CCER */
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372 TIMx->CCER = tmpccer;
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376 * @brief Initializes the TIMx Channel4 according to the specified
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377 * parameters in the TIM_OCInitStruct.
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378 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
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379 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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380 * that contains the configuration information for the specified TIM
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384 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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386 uint16_t tmpccmrx = 0, tmpccer = 0;
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388 /* Check the parameters */
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389 assert_param(IS_TIM_234_PERIPH(TIMx));
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390 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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391 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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392 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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394 /* Disable the Channel 2: Reset the CC4E Bit */
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395 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
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397 /* Get the TIMx CCER register value */
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398 tmpccer = TIMx->CCER;
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400 /* Get the TIMx CCMR2 register value */
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401 tmpccmrx = TIMx->CCMR2;
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403 /* Reset the Output Compare Mode Bits */
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404 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
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406 /* Select the Output Compare Mode */
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407 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
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409 /* Reset the Output Polarity level */
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410 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
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411 /* Set the Output Compare Polarity */
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412 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
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414 /* Set the Output State */
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415 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
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417 /* Set the Capture Compare Register value */
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418 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
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420 /* Write to TIMx CCMR2 */
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421 TIMx->CCMR2 = tmpccmrx;
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423 /* Write to TIMx CCER */
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424 TIMx->CCER = tmpccer;
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428 * @brief Initializes the TIM peripheral according to the specified
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429 * parameters in the TIM_ICInitStruct.
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430 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
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431 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
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432 * that contains the configuration information for the specified TIM
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436 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
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438 /* Check the parameters */
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439 assert_param(IS_TIM_23491011_PERIPH(TIMx));
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440 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
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441 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
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442 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
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443 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
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445 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
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447 /* TI1 Configuration */
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448 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
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449 TIM_ICInitStruct->TIM_ICSelection,
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450 TIM_ICInitStruct->TIM_ICFilter);
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451 /* Set the Input Capture Prescaler value */
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452 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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454 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
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456 /* TI2 Configuration */
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457 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
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458 TIM_ICInitStruct->TIM_ICSelection,
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459 TIM_ICInitStruct->TIM_ICFilter);
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460 /* Set the Input Capture Prescaler value */
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461 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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463 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
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465 /* TI3 Configuration */
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466 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
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467 TIM_ICInitStruct->TIM_ICSelection,
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468 TIM_ICInitStruct->TIM_ICFilter);
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469 /* Set the Input Capture Prescaler value */
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470 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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474 /* TI4 Configuration */
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475 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
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476 TIM_ICInitStruct->TIM_ICSelection,
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477 TIM_ICInitStruct->TIM_ICFilter);
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478 /* Set the Input Capture Prescaler value */
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479 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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484 * @brief Configures the TIM peripheral according to the specified
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485 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
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486 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
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487 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
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488 * that contains the configuration information for the specified TIM
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492 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
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494 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
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495 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
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496 /* Check the parameters */
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497 assert_param(IS_TIM_2349_PERIPH(TIMx));
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498 /* Select the Opposite Input Polarity */
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499 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
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501 icoppositepolarity = TIM_ICPolarity_Falling;
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505 icoppositepolarity = TIM_ICPolarity_Rising;
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507 /* Select the Opposite Input */
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508 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
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510 icoppositeselection = TIM_ICSelection_IndirectTI;
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514 icoppositeselection = TIM_ICSelection_DirectTI;
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516 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
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518 /* TI1 Configuration */
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519 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
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520 TIM_ICInitStruct->TIM_ICFilter);
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521 /* Set the Input Capture Prescaler value */
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522 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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523 /* TI2 Configuration */
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524 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
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525 /* Set the Input Capture Prescaler value */
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526 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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530 /* TI2 Configuration */
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531 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
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532 TIM_ICInitStruct->TIM_ICFilter);
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533 /* Set the Input Capture Prescaler value */
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534 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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535 /* TI1 Configuration */
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536 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
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537 /* Set the Input Capture Prescaler value */
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538 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
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543 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
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544 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
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545 * structure which will be initialized.
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548 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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550 /* Set the default configuration */
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551 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
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552 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
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553 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
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554 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
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558 * @brief Fills each TIM_OCInitStruct member with its default value.
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559 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
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563 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
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565 /* Set the default configuration */
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566 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
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567 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
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568 TIM_OCInitStruct->TIM_Pulse = 0x0000;
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569 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
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573 * @brief Fills each TIM_ICInitStruct member with its default value.
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574 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
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578 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
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580 /* Set the default configuration */
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581 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
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582 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
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583 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
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584 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
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585 TIM_ICInitStruct->TIM_ICFilter = 0x00;
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589 * @brief Enables or disables the specified TIM peripheral.
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590 * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
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591 * @param NewState: new state of the TIMx peripheral.
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592 * This parameter can be: ENABLE or DISABLE.
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595 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
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597 /* Check the parameters */
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598 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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599 assert_param(IS_FUNCTIONAL_STATE(NewState));
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601 if (NewState != DISABLE)
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603 /* Enable the TIM Counter */
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604 TIMx->CR1 |= TIM_CR1_CEN;
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608 /* Disable the TIM Counter */
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609 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
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614 * @brief Enables or disables the specified TIM interrupts.
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615 * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
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616 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
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617 * This parameter can be any combination of the following values:
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618 * @arg TIM_IT_Update: TIM update Interrupt source
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619 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
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620 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
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621 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
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622 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
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623 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
625 * - TIM6 and TIM7 can only generate an update interrupt.
\r
626 * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11
\r
627 * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
\r
628 * @param NewState: new state of the TIM interrupts.
\r
629 * This parameter can be: ENABLE or DISABLE.
\r
632 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
\r
634 /* Check the parameters */
\r
635 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
636 assert_param(IS_TIM_IT(TIM_IT));
\r
637 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
639 if (NewState != DISABLE)
\r
641 /* Enable the Interrupt sources */
\r
642 TIMx->DIER |= TIM_IT;
\r
646 /* Disable the Interrupt sources */
\r
647 TIMx->DIER &= (uint16_t)~TIM_IT;
\r
652 * @brief Configures the TIMx event to be generate by software.
\r
653 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
654 * @param TIM_EventSource: specifies the event source.
\r
655 * This parameter can be one or more of the following values:
\r
656 * @arg TIM_EventSource_Update: Timer update Event source
\r
657 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
\r
658 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
\r
659 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
\r
660 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
\r
661 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
\r
663 * - TIM6 and TIM7 can only generate an update event.
\r
664 * - TIM9 can only generate an update event, Capture Compare 1 event,
\r
665 * Capture Compare 2 event and TIM_EventSource_Trigger.
\r
666 * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
\r
669 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
\r
671 /* Check the parameters */
\r
672 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
673 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
\r
674 /* Set the event sources */
\r
675 TIMx->EGR = TIM_EventSource;
\r
679 * @brief Configures the TIMx
\92s DMA interface.
\r
680 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
681 * @param TIM_DMABase: DMA Base address.
\r
682 * This parameter can be one of the following values:
\r
683 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
\r
684 * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
\r
685 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
\r
686 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
\r
687 * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
\r
688 * TIM_DMABase_CCR4, TIM_DMABase_DCR.
\r
689 * @param TIM_DMABurstLength: DMA Burst length.
\r
690 * This parameter can be one value between:
\r
691 * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
\r
694 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
\r
696 /* Check the parameters */
\r
697 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
698 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
\r
699 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
\r
700 /* Set the DMA Base and the DMA Burst Length */
\r
701 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
\r
705 * @brief Enables or disables the TIMx
\92s DMA Requests.
\r
706 * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral.
\r
707 * @param TIM_DMASource: specifies the DMA Request sources.
\r
708 * This parameter can be any combination of the following values:
\r
709 * @arg TIM_DMA_Update: TIM update Interrupt source
\r
710 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
711 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
712 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
713 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
714 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
\r
715 * @param NewState: new state of the DMA Request sources.
\r
716 * This parameter can be: ENABLE or DISABLE.
\r
719 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
\r
721 /* Check the parameters */
\r
722 assert_param(IS_TIM_23467_PERIPH(TIMx));
\r
723 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
\r
724 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
726 if (NewState != DISABLE)
\r
728 /* Enable the DMA sources */
\r
729 TIMx->DIER |= TIM_DMASource;
\r
733 /* Disable the DMA sources */
\r
734 TIMx->DIER &= (uint16_t)~TIM_DMASource;
\r
739 * @brief Configures the TIMx interrnal Clock
\r
740 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
743 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
\r
745 /* Check the parameters */
\r
746 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
747 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
748 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
752 * @brief Configures the TIMx Internal Trigger as External Clock
\r
753 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
754 * @param TIM_ITRSource: Trigger source.
\r
755 * This parameter can be one of the following values:
\r
756 * @param TIM_TS_ITR0: Internal Trigger 0
\r
757 * @param TIM_TS_ITR1: Internal Trigger 1
\r
758 * @param TIM_TS_ITR2: Internal Trigger 2
\r
759 * @param TIM_TS_ITR3: Internal Trigger 3
\r
762 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
764 /* Check the parameters */
\r
765 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
766 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
767 /* Select the Internal Trigger */
\r
768 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
\r
769 /* Select the External clock mode1 */
\r
770 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
774 * @brief Configures the TIMx Trigger as External Clock
\r
775 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
776 * @param TIM_TIxExternalCLKSource: Trigger source.
\r
777 * This parameter can be one of the following values:
\r
778 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
\r
779 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
\r
780 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
\r
781 * @param TIM_ICPolarity: specifies the TIx Polarity.
\r
782 * This parameter can be one of the following values:
\r
783 * @arg TIM_ICPolarity_Rising
\r
784 * @arg TIM_ICPolarity_Falling
\r
785 * @param ICFilter : specifies the filter value.
\r
786 * This parameter must be a value between 0x0 and 0xF.
\r
789 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
790 uint16_t TIM_ICPolarity, uint16_t ICFilter)
\r
792 /* Check the parameters */
\r
793 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
794 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
\r
795 assert_param(IS_TIM_IC_FILTER(ICFilter));
\r
797 /* Configure the Timer Input Clock Source */
\r
798 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
\r
800 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
804 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
806 /* Select the Trigger source */
\r
807 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
\r
808 /* Select the External clock mode1 */
\r
809 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
813 * @brief Configures the External clock Mode1
\r
814 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
815 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
816 * This parameter can be one of the following values:
\r
817 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
818 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
819 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
820 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
821 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
822 * This parameter can be one of the following values:
\r
823 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
824 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
825 * @param ExtTRGFilter: External Trigger Filter.
\r
826 * This parameter must be a value between 0x00 and 0x0F
\r
829 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
830 uint16_t ExtTRGFilter)
\r
832 uint16_t tmpsmcr = 0;
\r
834 /* Check the parameters */
\r
835 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
836 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
837 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
838 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
840 /* Configure the ETR Clock source */
\r
841 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
843 /* Get the TIMx SMCR register value */
\r
844 tmpsmcr = TIMx->SMCR;
\r
845 /* Reset the SMS Bits */
\r
846 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
847 /* Select the External clock mode1 */
\r
848 tmpsmcr |= TIM_SlaveMode_External1;
\r
849 /* Select the Trigger selection : ETRF */
\r
850 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
851 tmpsmcr |= TIM_TS_ETRF;
\r
852 /* Write to TIMx SMCR */
\r
853 TIMx->SMCR = tmpsmcr;
\r
857 * @brief Configures the External clock Mode2
\r
858 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
859 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
860 * This parameter can be one of the following values:
\r
861 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
862 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
863 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
864 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
865 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
866 * This parameter can be one of the following values:
\r
867 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
868 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
869 * @param ExtTRGFilter: External Trigger Filter.
\r
870 * This parameter must be a value between 0x00 and 0x0F
\r
873 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
874 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
\r
876 /* Check the parameters */
\r
877 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
878 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
879 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
880 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
882 /* Configure the ETR Clock source */
\r
883 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
884 /* Enable the External clock mode2 */
\r
885 TIMx->SMCR |= TIM_SMCR_ECE;
\r
889 * @brief Configures the TIMx External Trigger (ETR).
\r
890 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
891 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
892 * This parameter can be one of the following values:
\r
893 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
894 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
895 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
896 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
897 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
898 * This parameter can be one of the following values:
\r
899 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
900 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
901 * @param ExtTRGFilter: External Trigger Filter.
\r
902 * This parameter must be a value between 0x00 and 0x0F
\r
905 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
906 uint16_t ExtTRGFilter)
\r
908 uint16_t tmpsmcr = 0;
\r
910 /* Check the parameters */
\r
911 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
912 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
913 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
914 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
916 tmpsmcr = TIMx->SMCR;
\r
917 /* Reset the ETR Bits */
\r
918 tmpsmcr &= SMCR_ETR_MASK;
\r
919 /* Set the Prescaler, the Filter value and the Polarity */
\r
920 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
\r
921 /* Write to TIMx SMCR */
\r
922 TIMx->SMCR = tmpsmcr;
\r
926 * @brief Configures the TIMx Prescaler.
\r
927 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
928 * @param Prescaler: specifies the Prescaler Register value
\r
929 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
\r
930 * This parameter can be one of the following values:
\r
931 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
\r
932 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
\r
935 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
\r
937 /* Check the parameters */
\r
938 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
939 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
\r
941 /* Set the Prescaler value */
\r
942 TIMx->PSC = Prescaler;
\r
943 /* Set or reset the UG Bit */
\r
944 TIMx->EGR = TIM_PSCReloadMode;
\r
948 * @brief Specifies the TIMx Counter Mode to be used.
\r
949 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
950 * @param TIM_CounterMode: specifies the Counter Mode to be used
\r
951 * This parameter can be one of the following values:
\r
952 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
\r
953 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
\r
954 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
\r
955 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
\r
956 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
\r
959 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
\r
961 uint16_t tmpcr1 = 0;
\r
963 /* Check the parameters */
\r
964 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
965 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
\r
967 tmpcr1 = TIMx->CR1;
\r
968 /* Reset the CMS and DIR Bits */
\r
969 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
\r
970 /* Set the Counter Mode */
\r
971 tmpcr1 |= TIM_CounterMode;
\r
972 /* Write to TIMx CR1 register */
\r
973 TIMx->CR1 = tmpcr1;
\r
977 * @brief Selects the Input Trigger source
\r
978 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
979 * @param TIM_InputTriggerSource: The Input Trigger source.
\r
980 * This parameter can be one of the following values:
\r
981 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
982 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
983 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
984 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
985 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
986 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
987 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
988 * @arg TIM_TS_ETRF: External Trigger input
\r
991 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
993 uint16_t tmpsmcr = 0;
\r
995 /* Check the parameters */
\r
996 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
997 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
999 /* Get the TIMx SMCR register value */
\r
1000 tmpsmcr = TIMx->SMCR;
\r
1001 /* Reset the TS Bits */
\r
1002 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
1003 /* Set the Input Trigger source */
\r
1004 tmpsmcr |= TIM_InputTriggerSource;
\r
1005 /* Write to TIMx SMCR */
\r
1006 TIMx->SMCR = tmpsmcr;
\r
1010 * @brief Configures the TIMx Encoder Interface.
\r
1011 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1012 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
\r
1013 * This parameter can be one of the following values:
\r
1014 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
\r
1015 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
\r
1016 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
\r
1017 * on the level of the other input.
\r
1018 * @param TIM_IC1Polarity: specifies the IC1 Polarity
\r
1019 * This parmeter can be one of the following values:
\r
1020 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1021 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1022 * @param TIM_IC2Polarity: specifies the IC2 Polarity
\r
1023 * This parmeter can be one of the following values:
\r
1024 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1025 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1028 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
1029 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
\r
1031 uint16_t tmpsmcr = 0;
\r
1032 uint16_t tmpccmr1 = 0;
\r
1033 uint16_t tmpccer = 0;
\r
1035 /* Check the parameters */
\r
1036 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1037 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
\r
1038 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
\r
1039 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
\r
1041 /* Get the TIMx SMCR register value */
\r
1042 tmpsmcr = TIMx->SMCR;
\r
1043 /* Get the TIMx CCMR1 register value */
\r
1044 tmpccmr1 = TIMx->CCMR1;
\r
1045 /* Get the TIMx CCER register value */
\r
1046 tmpccer = TIMx->CCER;
\r
1047 /* Set the encoder Mode */
\r
1048 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
1049 tmpsmcr |= TIM_EncoderMode;
\r
1050 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
1051 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
\r
1052 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
\r
1053 /* Set the TI1 and the TI2 Polarities */
\r
1054 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
\r
1055 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
\r
1056 /* Write to TIMx SMCR */
\r
1057 TIMx->SMCR = tmpsmcr;
\r
1058 /* Write to TIMx CCMR1 */
\r
1059 TIMx->CCMR1 = tmpccmr1;
\r
1060 /* Write to TIMx CCER */
\r
1061 TIMx->CCER = tmpccer;
\r
1065 * @brief Forces the TIMx output 1 waveform to active or inactive level.
\r
1066 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1067 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1068 * This parameter can be one of the following values:
\r
1069 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
\r
1070 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
\r
1073 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1075 uint16_t tmpccmr1 = 0;
\r
1076 /* Check the parameters */
\r
1077 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1078 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1079 tmpccmr1 = TIMx->CCMR1;
\r
1080 /* Reset the OC1M Bits */
\r
1081 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
\r
1082 /* Configure The Forced output Mode */
\r
1083 tmpccmr1 |= TIM_ForcedAction;
\r
1084 /* Write to TIMx CCMR1 register */
\r
1085 TIMx->CCMR1 = tmpccmr1;
\r
1089 * @brief Forces the TIMx output 2 waveform to active or inactive level.
\r
1090 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM
\r
1092 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1093 * This parameter can be one of the following values:
\r
1094 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
\r
1095 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
\r
1098 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1100 uint16_t tmpccmr1 = 0;
\r
1102 /* Check the parameters */
\r
1103 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1104 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1106 tmpccmr1 = TIMx->CCMR1;
\r
1107 /* Reset the OC2M Bits */
\r
1108 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
\r
1109 /* Configure The Forced output Mode */
\r
1110 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1111 /* Write to TIMx CCMR1 register */
\r
1112 TIMx->CCMR1 = tmpccmr1;
\r
1116 * @brief Forces the TIMx output 3 waveform to active or inactive level.
\r
1117 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1118 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1119 * This parameter can be one of the following values:
\r
1120 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
\r
1121 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
\r
1124 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1126 uint16_t tmpccmr2 = 0;
\r
1128 /* Check the parameters */
\r
1129 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1130 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1132 tmpccmr2 = TIMx->CCMR2;
\r
1133 /* Reset the OC1M Bits */
\r
1134 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
\r
1135 /* Configure The Forced output Mode */
\r
1136 tmpccmr2 |= TIM_ForcedAction;
\r
1137 /* Write to TIMx CCMR2 register */
\r
1138 TIMx->CCMR2 = tmpccmr2;
\r
1142 * @brief Forces the TIMx output 4 waveform to active or inactive level.
\r
1143 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1144 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1145 * This parameter can be one of the following values:
\r
1146 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
\r
1147 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
\r
1150 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1152 uint16_t tmpccmr2 = 0;
\r
1153 /* Check the parameters */
\r
1154 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1155 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1157 tmpccmr2 = TIMx->CCMR2;
\r
1158 /* Reset the OC2M Bits */
\r
1159 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
\r
1160 /* Configure The Forced output Mode */
\r
1161 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1162 /* Write to TIMx CCMR2 register */
\r
1163 TIMx->CCMR2 = tmpccmr2;
\r
1167 * @brief Enables or disables TIMx peripheral Preload register on ARR.
\r
1168 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1169 * @param NewState: new state of the TIMx peripheral Preload register
\r
1170 * This parameter can be: ENABLE or DISABLE.
\r
1173 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1175 /* Check the parameters */
\r
1176 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1177 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1179 if (NewState != DISABLE)
\r
1181 /* Set the ARR Preload Bit */
\r
1182 TIMx->CR1 |= TIM_CR1_ARPE;
\r
1186 /* Reset the ARR Preload Bit */
\r
1187 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
\r
1192 * @brief Selects the TIMx peripheral Capture Compare DMA source.
\r
1193 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1194 * @param NewState: new state of the Capture Compare DMA source
\r
1195 * This parameter can be: ENABLE or DISABLE.
\r
1198 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1200 /* Check the parameters */
\r
1201 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1202 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1204 if (NewState != DISABLE)
\r
1206 /* Set the CCDS Bit */
\r
1207 TIMx->CR2 |= TIM_CR2_CCDS;
\r
1211 /* Reset the CCDS Bit */
\r
1212 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
\r
1217 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
\r
1218 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1219 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1220 * This parameter can be one of the following values:
\r
1221 * @arg TIM_OCPreload_Enable
\r
1222 * @arg TIM_OCPreload_Disable
\r
1225 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1227 uint16_t tmpccmr1 = 0;
\r
1228 /* Check the parameters */
\r
1229 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1230 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1232 tmpccmr1 = TIMx->CCMR1;
\r
1233 /* Reset the OC1PE Bit */
\r
1234 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
\r
1235 /* Enable or Disable the Output Compare Preload feature */
\r
1236 tmpccmr1 |= TIM_OCPreload;
\r
1237 /* Write to TIMx CCMR1 register */
\r
1238 TIMx->CCMR1 = tmpccmr1;
\r
1242 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
\r
1243 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1244 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1245 * This parameter can be one of the following values:
\r
1246 * @arg TIM_OCPreload_Enable
\r
1247 * @arg TIM_OCPreload_Disable
\r
1250 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1252 uint16_t tmpccmr1 = 0;
\r
1253 /* Check the parameters */
\r
1254 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1255 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1257 tmpccmr1 = TIMx->CCMR1;
\r
1258 /* Reset the OC2PE Bit */
\r
1259 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
\r
1260 /* Enable or Disable the Output Compare Preload feature */
\r
1261 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
\r
1262 /* Write to TIMx CCMR1 register */
\r
1263 TIMx->CCMR1 = tmpccmr1;
\r
1267 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
\r
1268 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1269 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1270 * This parameter can be one of the following values:
\r
1271 * @arg TIM_OCPreload_Enable
\r
1272 * @arg TIM_OCPreload_Disable
\r
1275 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1277 uint16_t tmpccmr2 = 0;
\r
1279 /* Check the parameters */
\r
1280 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1281 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1283 tmpccmr2 = TIMx->CCMR2;
\r
1284 /* Reset the OC3PE Bit */
\r
1285 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
\r
1286 /* Enable or Disable the Output Compare Preload feature */
\r
1287 tmpccmr2 |= TIM_OCPreload;
\r
1288 /* Write to TIMx CCMR2 register */
\r
1289 TIMx->CCMR2 = tmpccmr2;
\r
1293 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
\r
1294 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1295 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1296 * This parameter can be one of the following values:
\r
1297 * @arg TIM_OCPreload_Enable
\r
1298 * @arg TIM_OCPreload_Disable
\r
1301 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1303 uint16_t tmpccmr2 = 0;
\r
1305 /* Check the parameters */
\r
1306 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1307 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1309 tmpccmr2 = TIMx->CCMR2;
\r
1310 /* Reset the OC4PE Bit */
\r
1311 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
\r
1312 /* Enable or Disable the Output Compare Preload feature */
\r
1313 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
\r
1314 /* Write to TIMx CCMR2 register */
\r
1315 TIMx->CCMR2 = tmpccmr2;
\r
1319 * @brief Configures the TIMx Output Compare 1 Fast feature.
\r
1320 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1321 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1322 * This parameter can be one of the following values:
\r
1323 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1324 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1327 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1329 uint16_t tmpccmr1 = 0;
\r
1331 /* Check the parameters */
\r
1332 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1333 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1335 /* Get the TIMx CCMR1 register value */
\r
1336 tmpccmr1 = TIMx->CCMR1;
\r
1337 /* Reset the OC1FE Bit */
\r
1338 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
\r
1339 /* Enable or Disable the Output Compare Fast Bit */
\r
1340 tmpccmr1 |= TIM_OCFast;
\r
1341 /* Write to TIMx CCMR1 */
\r
1342 TIMx->CCMR1 = tmpccmr1;
\r
1346 * @brief Configures the TIMx Output Compare 2 Fast feature.
\r
1347 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1348 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1349 * This parameter can be one of the following values:
\r
1350 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1351 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1354 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1356 uint16_t tmpccmr1 = 0;
\r
1358 /* Check the parameters */
\r
1359 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1360 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1362 /* Get the TIMx CCMR1 register value */
\r
1363 tmpccmr1 = TIMx->CCMR1;
\r
1364 /* Reset the OC2FE Bit */
\r
1365 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
\r
1366 /* Enable or Disable the Output Compare Fast Bit */
\r
1367 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
\r
1368 /* Write to TIMx CCMR1 */
\r
1369 TIMx->CCMR1 = tmpccmr1;
\r
1373 * @brief Configures the TIMx Output Compare 3 Fast feature.
\r
1374 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1375 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1376 * This parameter can be one of the following values:
\r
1377 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1378 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1381 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1383 uint16_t tmpccmr2 = 0;
\r
1385 /* Check the parameters */
\r
1386 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1387 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1389 /* Get the TIMx CCMR2 register value */
\r
1390 tmpccmr2 = TIMx->CCMR2;
\r
1391 /* Reset the OC3FE Bit */
\r
1392 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
\r
1393 /* Enable or Disable the Output Compare Fast Bit */
\r
1394 tmpccmr2 |= TIM_OCFast;
\r
1395 /* Write to TIMx CCMR2 */
\r
1396 TIMx->CCMR2 = tmpccmr2;
\r
1400 * @brief Configures the TIMx Output Compare 4 Fast feature.
\r
1401 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1402 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1403 * This parameter can be one of the following values:
\r
1404 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1405 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1408 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1410 uint16_t tmpccmr2 = 0;
\r
1412 /* Check the parameters */
\r
1413 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1414 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1416 /* Get the TIMx CCMR2 register value */
\r
1417 tmpccmr2 = TIMx->CCMR2;
\r
1418 /* Reset the OC4FE Bit */
\r
1419 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
\r
1420 /* Enable or Disable the Output Compare Fast Bit */
\r
1421 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
\r
1422 /* Write to TIMx CCMR2 */
\r
1423 TIMx->CCMR2 = tmpccmr2;
\r
1427 * @brief Clears or safeguards the OCREF1 signal on an external event
\r
1428 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1429 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1430 * This parameter can be one of the following values:
\r
1431 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1432 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1435 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1437 uint16_t tmpccmr1 = 0;
\r
1439 /* Check the parameters */
\r
1440 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1441 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1443 tmpccmr1 = TIMx->CCMR1;
\r
1444 /* Reset the OC1CE Bit */
\r
1445 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
\r
1446 /* Enable or Disable the Output Compare Clear Bit */
\r
1447 tmpccmr1 |= TIM_OCClear;
\r
1448 /* Write to TIMx CCMR1 register */
\r
1449 TIMx->CCMR1 = tmpccmr1;
\r
1453 * @brief Clears or safeguards the OCREF2 signal on an external event
\r
1454 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1455 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1457 * This parameter can be one of the following values:
\r
1458 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1459 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1462 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1464 uint16_t tmpccmr1 = 0;
\r
1466 /* Check the parameters */
\r
1467 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1468 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1470 tmpccmr1 = TIMx->CCMR1;
\r
1471 /* Reset the OC2CE Bit */
\r
1472 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
\r
1473 /* Enable or Disable the Output Compare Clear Bit */
\r
1474 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
\r
1475 /* Write to TIMx CCMR1 register */
\r
1476 TIMx->CCMR1 = tmpccmr1;
\r
1480 * @brief Clears or safeguards the OCREF3 signal on an external event
\r
1481 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1482 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1483 * This parameter can be one of the following values:
\r
1484 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1485 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1488 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1490 uint16_t tmpccmr2 = 0;
\r
1492 /* Check the parameters */
\r
1493 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1494 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1496 tmpccmr2 = TIMx->CCMR2;
\r
1497 /* Reset the OC3CE Bit */
\r
1498 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
\r
1499 /* Enable or Disable the Output Compare Clear Bit */
\r
1500 tmpccmr2 |= TIM_OCClear;
\r
1501 /* Write to TIMx CCMR2 register */
\r
1502 TIMx->CCMR2 = tmpccmr2;
\r
1506 * @brief Clears or safeguards the OCREF4 signal on an external event
\r
1507 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1508 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1509 * This parameter can be one of the following values:
\r
1510 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1511 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1514 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1516 uint16_t tmpccmr2 = 0;
\r
1518 /* Check the parameters */
\r
1519 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1520 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1522 tmpccmr2 = TIMx->CCMR2;
\r
1523 /* Reset the OC4CE Bit */
\r
1524 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
\r
1525 /* Enable or Disable the Output Compare Clear Bit */
\r
1526 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
\r
1527 /* Write to TIMx CCMR2 register */
\r
1528 TIMx->CCMR2 = tmpccmr2;
\r
1532 * @brief Configures the TIMx channel 1 polarity.
\r
1533 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1534 * @param TIM_OCPolarity: specifies the OC1 Polarity
\r
1535 * This parmeter can be one of the following values:
\r
1536 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1537 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1540 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1542 uint16_t tmpccer = 0;
\r
1544 /* Check the parameters */
\r
1545 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1546 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1548 tmpccer = TIMx->CCER;
\r
1549 /* Set or Reset the CC1P Bit */
\r
1550 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
\r
1551 tmpccer |= TIM_OCPolarity;
\r
1552 /* Write to TIMx CCER register */
\r
1553 TIMx->CCER = tmpccer;
\r
1557 * @brief Configures the TIMx channel 2 polarity.
\r
1558 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1559 * @param TIM_OCPolarity: specifies the OC2 Polarity
\r
1560 * This parmeter can be one of the following values:
\r
1561 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1562 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1565 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1567 uint16_t tmpccer = 0;
\r
1569 /* Check the parameters */
\r
1570 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1571 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1573 tmpccer = TIMx->CCER;
\r
1574 /* Set or Reset the CC2P Bit */
\r
1575 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
\r
1576 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
\r
1577 /* Write to TIMx CCER register */
\r
1578 TIMx->CCER = tmpccer;
\r
1582 * @brief Configures the TIMx channel 3 polarity.
\r
1583 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1584 * @param TIM_OCPolarity: specifies the OC3 Polarity
\r
1585 * This parmeter can be one of the following values:
\r
1586 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1587 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1590 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1592 uint16_t tmpccer = 0;
\r
1594 /* Check the parameters */
\r
1595 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1596 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1598 tmpccer = TIMx->CCER;
\r
1599 /* Set or Reset the CC3P Bit */
\r
1600 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
\r
1601 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
\r
1602 /* Write to TIMx CCER register */
\r
1603 TIMx->CCER = tmpccer;
\r
1607 * @brief Configures the TIMx channel 4 polarity.
\r
1608 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1609 * @param TIM_OCPolarity: specifies the OC4 Polarity
\r
1610 * This parmeter can be one of the following values:
\r
1611 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1612 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1615 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1617 uint16_t tmpccer = 0;
\r
1619 /* Check the parameters */
\r
1620 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1621 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1623 tmpccer = TIMx->CCER;
\r
1624 /* Set or Reset the CC4P Bit */
\r
1625 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
\r
1626 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
\r
1627 /* Write to TIMx CCER register */
\r
1628 TIMx->CCER = tmpccer;
\r
1632 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
1633 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1634 * @param TIM_Channel: specifies the TIM Channel
\r
1635 * This parmeter can be one of the following values:
\r
1636 * @arg TIM_Channel_1: TIM Channel 1
\r
1637 * @arg TIM_Channel_2: TIM Channel 2
\r
1638 * @arg TIM_Channel_3: TIM Channel 3
\r
1639 * @arg TIM_Channel_4: TIM Channel 4
\r
1640 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
\r
1641 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
\r
1644 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
\r
1648 /* Check the parameters */
\r
1649 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1650 assert_param(IS_TIM_CCX(TIM_CCx));
\r
1652 tmp = CCER_CCE_SET << TIM_Channel;
\r
1654 /* Reset the CCxE Bit */
\r
1655 TIMx->CCER &= (uint16_t)~ tmp;
\r
1657 /* Set or reset the CCxE Bit */
\r
1658 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
\r
1662 * @brief Selects the TIM Ouput Compare Mode.
\r
1663 * @note This function disables the selected channel before changing the Ouput
\r
1665 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
\r
1666 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1667 * @param TIM_Channel: specifies the TIM Channel
\r
1668 * This parmeter can be one of the following values:
\r
1669 * @arg TIM_Channel_1: TIM Channel 1
\r
1670 * @arg TIM_Channel_2: TIM Channel 2
\r
1671 * @arg TIM_Channel_3: TIM Channel 3
\r
1672 * @arg TIM_Channel_4: TIM Channel 4
\r
1673 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
\r
1674 * This paramter can be one of the following values:
\r
1675 * @arg TIM_OCMode_Timing
\r
1676 * @arg TIM_OCMode_Active
\r
1677 * @arg TIM_OCMode_Toggle
\r
1678 * @arg TIM_OCMode_PWM1
\r
1679 * @arg TIM_OCMode_PWM2
\r
1680 * @arg TIM_ForcedAction_Active
\r
1681 * @arg TIM_ForcedAction_InActive
\r
1684 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
\r
1687 uint16_t tmp1 = 0;
\r
1689 /* Check the parameters */
\r
1690 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1691 assert_param(IS_TIM_OCM(TIM_OCMode));
\r
1693 tmp = (uint32_t) TIMx;
\r
1694 tmp += CCMR_OFFSET;
\r
1696 tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
\r
1698 /* Disable the Channel: Reset the CCxE Bit */
\r
1699 TIMx->CCER &= (uint16_t) ~tmp1;
\r
1701 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
\r
1703 tmp += (TIM_Channel>>1);
\r
1705 /* Reset the OCxM bits in the CCMRx register */
\r
1706 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
\r
1708 /* Configure the OCxM bits in the CCMRx register */
\r
1709 *(__IO uint32_t *) tmp |= TIM_OCMode;
\r
1713 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
\r
1715 /* Reset the OCxM bits in the CCMRx register */
\r
1716 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
\r
1718 /* Configure the OCxM bits in the CCMRx register */
\r
1719 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
\r
1724 * @brief Enables or Disables the TIMx Update event.
\r
1725 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1726 * @param NewState: new state of the TIMx UDIS bit
\r
1727 * This parameter can be: ENABLE or DISABLE.
\r
1730 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1732 /* Check the parameters */
\r
1733 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1734 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1736 if (NewState != DISABLE)
\r
1738 /* Set the Update Disable Bit */
\r
1739 TIMx->CR1 |= TIM_CR1_UDIS;
\r
1743 /* Reset the Update Disable Bit */
\r
1744 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
\r
1749 * @brief Configures the TIMx Update Request Interrupt source.
\r
1750 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1751 * @param TIM_UpdateSource: specifies the Update source.
\r
1752 * This parameter can be one of the following values:
\r
1753 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
\r
1754 or the setting of UG bit, or an update generation
\r
1755 through the slave mode controller.
\r
1756 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
\r
1759 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
\r
1761 /* Check the parameters */
\r
1762 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1763 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
\r
1765 if (TIM_UpdateSource != TIM_UpdateSource_Global)
\r
1767 /* Set the URS Bit */
\r
1768 TIMx->CR1 |= TIM_CR1_URS;
\r
1772 /* Reset the URS Bit */
\r
1773 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
\r
1778 * @brief Enables or disables the TIMx
\92s Hall sensor interface.
\r
1779 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1780 * @param NewState: new state of the TIMx Hall sensor interface.
\r
1781 * This parameter can be: ENABLE or DISABLE.
\r
1784 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1786 /* Check the parameters */
\r
1787 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1788 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1790 if (NewState != DISABLE)
\r
1792 /* Set the TI1S Bit */
\r
1793 TIMx->CR2 |= TIM_CR2_TI1S;
\r
1797 /* Reset the TI1S Bit */
\r
1798 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
\r
1803 * @brief Selects the TIMx
\92s One Pulse Mode.
\r
1804 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1805 * @param TIM_OPMode: specifies the OPM Mode to be used.
\r
1806 * This parameter can be one of the following values:
\r
1807 * @arg TIM_OPMode_Single
\r
1808 * @arg TIM_OPMode_Repetitive
\r
1811 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
\r
1813 /* Check the parameters */
\r
1814 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1815 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
\r
1817 /* Reset the OPM Bit */
\r
1818 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
\r
1819 /* Configure the OPM Mode */
\r
1820 TIMx->CR1 |= TIM_OPMode;
\r
1824 * @brief Selects the TIMx Trigger Output Mode.
\r
1825 * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.
\r
1826 * @param TIM_TRGOSource: specifies the Trigger Output source.
\r
1827 * This paramter can be one of the following values:
\r
1830 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
\r
1831 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
\r
1832 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
\r
1834 * - For all TIMx except TIM6 and TIM7
\r
1835 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
\r
1836 * is to be set, as soon as a capture or compare match occurs (TRGO).
\r
1837 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
\r
1839 * - For all TIMx except TIM6, TIM7, TIM10 and TIM11
\r
1840 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
\r
1842 * - For TIM2, TIM3 and TIM4
\r
1843 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
\r
1844 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
\r
1848 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
\r
1850 /* Check the parameters */
\r
1851 assert_param(IS_TIM_234679_PERIPH(TIMx));
\r
1852 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
\r
1854 /* Reset the MMS Bits */
\r
1855 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
\r
1856 /* Select the TRGO source */
\r
1857 TIMx->CR2 |= TIM_TRGOSource;
\r
1861 * @brief Selects the TIMx Slave Mode.
\r
1862 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1863 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
\r
1864 * This paramter can be one of the following values:
\r
1865 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
\r
1866 * the counter and triggers an update of the registers.
\r
1867 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
\r
1868 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
\r
1869 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
\r
1872 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
\r
1874 /* Check the parameters */
\r
1875 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1876 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
\r
1878 /* Reset the SMS Bits */
\r
1879 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
\r
1880 /* Select the Slave Mode */
\r
1881 TIMx->SMCR |= TIM_SlaveMode;
\r
1885 * @brief Sets or Resets the TIMx Master/Slave Mode.
\r
1886 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1887 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
\r
1888 * This paramter can be one of the following values:
\r
1889 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
\r
1890 * and its slaves (through TRGO).
\r
1891 * @arg TIM_MasterSlaveMode_Disable: No action
\r
1894 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
\r
1896 /* Check the parameters */
\r
1897 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1898 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
\r
1900 /* Reset the MSM Bit */
\r
1901 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
\r
1903 /* Set or Reset the MSM Bit */
\r
1904 TIMx->SMCR |= TIM_MasterSlaveMode;
\r
1908 * @brief Sets the TIMx Counter Register value
\r
1909 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1910 * @param Counter: specifies the Counter register new value.
\r
1913 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
\r
1915 /* Check the parameters */
\r
1916 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1918 /* Set the Counter Register value */
\r
1919 TIMx->CNT = Counter;
\r
1923 * @brief Sets the TIMx Autoreload Register value
\r
1924 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1925 * @param Autoreload: specifies the Autoreload register new value.
\r
1928 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
\r
1930 /* Check the parameters */
\r
1931 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1933 /* Set the Autoreload Register value */
\r
1934 TIMx->ARR = Autoreload;
\r
1938 * @brief Sets the TIMx Capture Compare1 Register value
\r
1939 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1940 * @param Compare1: specifies the Capture Compare1 register new value.
\r
1944 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
\r
1946 /* Check the parameters */
\r
1947 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
1949 /* Set the Capture Compare1 Register value */
\r
1950 TIMx->CCR1 = Compare1;
\r
1954 * @brief Sets the TIMx Capture Compare2 Register value
\r
1955 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1956 * @param Compare2: specifies the Capture Compare2 register new value.
\r
1960 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
\r
1962 /* Check the parameters */
\r
1963 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
1965 /* Set the Capture Compare2 Register value */
\r
1966 TIMx->CCR2 = Compare2;
\r
1970 * @brief Sets the TIMx Capture Compare3 Register value
\r
1971 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1972 * @param Compare3: specifies the Capture Compare3 register new value.
\r
1976 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
\r
1978 /* Check the parameters */
\r
1979 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1981 /* Set the Capture Compare3 Register value */
\r
1982 TIMx->CCR3 = Compare3;
\r
1986 * @brief Sets the TIMx Capture Compare4 Register value
\r
1987 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1988 * @param Compare4: specifies the Capture Compare4 register new value.
\r
1992 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
\r
1994 /* Check the parameters */
\r
1995 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
1997 /* Set the Capture Compare4 Register value */
\r
1998 TIMx->CCR4 = Compare4;
\r
2002 * @brief Sets the TIMx Input Capture 1 prescaler.
\r
2003 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2004 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
\r
2005 * This parameter can be one of the following values:
\r
2006 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2007 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2008 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2009 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2012 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2014 /* Check the parameters */
\r
2015 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
2016 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2018 /* Reset the IC1PSC Bits */
\r
2019 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
\r
2020 /* Set the IC1PSC value */
\r
2021 TIMx->CCMR1 |= TIM_ICPSC;
\r
2025 * @brief Sets the TIMx Input Capture 2 prescaler.
\r
2026 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2027 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
\r
2028 * This parameter can be one of the following values:
\r
2029 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2030 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2031 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2032 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2035 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2037 /* Check the parameters */
\r
2038 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
2039 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2041 /* Reset the IC2PSC Bits */
\r
2042 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
\r
2043 /* Set the IC2PSC value */
\r
2044 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
\r
2048 * @brief Sets the TIMx Input Capture 3 prescaler.
\r
2049 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2050 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
\r
2051 * This parameter can be one of the following values:
\r
2052 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2053 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2054 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2055 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2058 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2060 /* Check the parameters */
\r
2061 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
2062 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2064 /* Reset the IC3PSC Bits */
\r
2065 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
\r
2066 /* Set the IC3PSC value */
\r
2067 TIMx->CCMR2 |= TIM_ICPSC;
\r
2071 * @brief Sets the TIMx Input Capture 4 prescaler.
\r
2072 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2073 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
\r
2074 * This parameter can be one of the following values:
\r
2075 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2076 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2077 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2078 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2081 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2083 /* Check the parameters */
\r
2084 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
2085 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2087 /* Reset the IC4PSC Bits */
\r
2088 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
\r
2089 /* Set the IC4PSC value */
\r
2090 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
\r
2094 * @brief Sets the TIMx Clock Division value.
\r
2095 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2096 * @param TIM_CKD: specifies the clock division value.
\r
2097 * This parameter can be one of the following value:
\r
2098 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
\r
2099 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
\r
2100 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
\r
2103 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
\r
2105 /* Check the parameters */
\r
2106 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
2107 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
\r
2109 /* Reset the CKD Bits */
\r
2110 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
\r
2111 /* Set the CKD value */
\r
2112 TIMx->CR1 |= TIM_CKD;
\r
2116 * @brief Gets the TIMx Input Capture 1 value.
\r
2117 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2118 * @retval Capture Compare 1 Register value.
\r
2121 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
\r
2123 /* Check the parameters */
\r
2124 assert_param(IS_TIM_23491011_PERIPH(TIMx));
\r
2126 /* Get the Capture 1 Register value */
\r
2127 return TIMx->CCR1;
\r
2131 * @brief Gets the TIMx Input Capture 2 value.
\r
2132 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2133 * @retval Capture Compare 2 Register value.
\r
2136 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
\r
2138 /* Check the parameters */
\r
2139 assert_param(IS_TIM_2349_PERIPH(TIMx));
\r
2141 /* Get the Capture 2 Register value */
\r
2142 return TIMx->CCR2;
\r
2146 * @brief Gets the TIMx Input Capture 3 value.
\r
2147 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2148 * @retval Capture Compare 3 Register value.
\r
2150 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
\r
2152 /* Check the parameters */
\r
2153 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
2155 /* Get the Capture 3 Register value */
\r
2156 return TIMx->CCR3;
\r
2160 * @brief Gets the TIMx Input Capture 4 value.
\r
2161 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2162 * @retval Capture Compare 4 Register value.
\r
2164 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
\r
2166 /* Check the parameters */
\r
2167 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
2169 /* Get the Capture 4 Register value */
\r
2170 return TIMx->CCR4;
\r
2174 * @brief Gets the TIMx Counter value.
\r
2175 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2176 * @retval Counter Register value.
\r
2178 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
\r
2180 /* Check the parameters */
\r
2181 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2183 /* Get the Counter Register value */
\r
2188 * @brief Gets the TIMx Prescaler value.
\r
2189 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2190 * @retval Prescaler Register value.
\r
2192 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
\r
2194 /* Check the parameters */
\r
2195 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2197 /* Get the Prescaler Register value */
\r
2202 * @brief Selects the OCReference Clear source.
\r
2203 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2204 * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
\r
2205 * This parameter can be one of the following values:
\r
2206 * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
\r
2207 * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
\r
2210 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
\r
2212 /* Check the parameters */
\r
2213 assert_param(IS_TIM_234_PERIPH(TIMx));
\r
2214 assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
\r
2216 /* Set the TIM_OCReferenceClear source */
\r
2217 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
\r
2218 TIMx->SMCR |= TIM_OCReferenceClear;
\r
2222 * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.
\r
2223 * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.
\r
2224 * @param TIM_Remap: specifies the TIM input reampping source.
\r
2225 * This parameter can be one of the following values:
\r
2226 * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)
\r
2227 * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
\r
2228 * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default)
\r
2229 * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
\r
2230 * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
\r
2231 * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
\r
2232 * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default)
\r
2233 * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
\r
2234 * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
\r
2237 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
\r
2239 /* Check the parameters */
\r
2240 assert_param(IS_TIM_91011_PERIPH(TIMx));
\r
2241 assert_param(IS_TIM_REMAP(TIM_Remap));
\r
2243 /* Set the Timer remapping configuration */
\r
2244 TIMx->OR = TIM_Remap;
\r
2248 * @brief Checks whether the specified TIM flag is set or not.
\r
2249 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2250 * @param TIM_FLAG: specifies the flag to check.
\r
2251 * This parameter can be one of the following values:
\r
2252 * @arg TIM_FLAG_Update: TIM update Flag
\r
2253 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2254 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2255 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2256 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2257 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2258 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2259 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2260 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2261 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2263 * - TIM6 and TIM7 can have only one update flag.
\r
2264 * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,
\r
2265 * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
\r
2266 * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
\r
2267 * @retval The new state of TIM_FLAG (SET or RESET).
\r
2269 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2271 ITStatus bitstatus = RESET;
\r
2273 /* Check the parameters */
\r
2274 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2275 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
\r
2277 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
\r
2283 bitstatus = RESET;
\r
2289 * @brief Clears the TIMx's pending flags.
\r
2290 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2291 * @param TIM_FLAG: specifies the flag bit to clear.
\r
2292 * This parameter can be any combination of the following values:
\r
2293 * @arg TIM_FLAG_Update: TIM update Flag
\r
2294 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2295 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2296 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2297 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2298 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2299 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2300 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2301 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2302 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2304 * - TIM6 and TIM7 can have only one update flag.
\r
2305 * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags
\r
2306 * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
\r
2307 * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1
\r
2308 * or TIM_FLAG_CC1OF flags
\r
2311 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2313 /* Check the parameters */
\r
2314 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2315 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
\r
2317 /* Clear the flags */
\r
2318 TIMx->SR = (uint16_t)~TIM_FLAG;
\r
2322 * @brief Checks whether the TIM interrupt has occurred or not.
\r
2323 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2324 * @param TIM_IT: specifies the TIM interrupt source to check.
\r
2325 * This parameter can be one of the following values:
\r
2326 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2327 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2328 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2329 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2330 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2331 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2333 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2334 * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,
\r
2335 * interrupt and TIM_IT_Trigger interrupt.
\r
2336 * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1
\r
2338 * @retval The new state of the TIM_IT(SET or RESET).
\r
2340 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2342 ITStatus bitstatus = RESET;
\r
2343 uint16_t itstatus = 0x0, itenable = 0x0;
\r
2345 /* Check the parameters */
\r
2346 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2347 assert_param(IS_TIM_GET_IT(TIM_IT));
\r
2349 itstatus = TIMx->SR & TIM_IT;
\r
2351 itenable = TIMx->DIER & TIM_IT;
\r
2352 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
\r
2358 bitstatus = RESET;
\r
2364 * @brief Clears the TIMx's interrupt pending bits.
\r
2365 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2366 * @param TIM_IT: specifies the pending bit to clear.
\r
2367 * This parameter can be any combination of the following values:
\r
2368 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2369 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2370 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2371 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2372 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2373 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2375 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2376 * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,
\r
2377 * and TIM_IT_Trigger interrupt.
\r
2378 * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1
\r
2382 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2384 /* Check the parameters */
\r
2385 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2386 assert_param(IS_TIM_IT(TIM_IT));
\r
2388 /* Clear the IT pending Bit */
\r
2389 TIMx->SR = (uint16_t)~TIM_IT;
\r
2393 * @brief Configure the TI1 as Input.
\r
2394 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2395 * @param TIM_ICPolarity : The Input Polarity.
\r
2396 * This parameter can be one of the following values:
\r
2397 * @arg TIM_ICPolarity_Rising
\r
2398 * @arg TIM_ICPolarity_Falling
\r
2399 * @param TIM_ICSelection: specifies the input to be used.
\r
2400 * This parameter can be one of the following values:
\r
2401 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
2402 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
2403 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
2404 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2405 * This parameter must be a value between 0x00 and 0x0F.
\r
2408 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2409 uint16_t TIM_ICFilter)
\r
2411 uint16_t tmpccmr1 = 0, tmpccer = 0;
\r
2413 /* Disable the Channel 1: Reset the CC1E Bit */
\r
2414 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
\r
2415 tmpccmr1 = TIMx->CCMR1;
\r
2416 tmpccer = TIMx->CCER;
\r
2417 /* Select the Input and set the filter */
\r
2418 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
\r
2419 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2420 /* Select the Polarity and set the CC1E Bit */
\r
2421 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
\r
2422 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
\r
2423 /* Write to TIMx CCMR1 and CCER registers */
\r
2424 TIMx->CCMR1 = tmpccmr1;
\r
2425 TIMx->CCER = tmpccer;
\r
2429 * @brief Configure the TI2 as Input.
\r
2430 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2431 * @param TIM_ICPolarity : The Input Polarity.
\r
2432 * This parameter can be one of the following values:
\r
2433 * @arg TIM_ICPolarity_Rising
\r
2434 * @arg TIM_ICPolarity_Falling
\r
2435 * @param TIM_ICSelection: specifies the input to be used.
\r
2436 * This parameter can be one of the following values:
\r
2437 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
2438 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
2439 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
2440 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2441 * This parameter must be a value between 0x00 and 0x0F.
\r
2444 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2445 uint16_t TIM_ICFilter)
\r
2447 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
\r
2449 /* Disable the Channel 2: Reset the CC2E Bit */
\r
2450 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
\r
2451 tmpccmr1 = TIMx->CCMR1;
\r
2452 tmpccer = TIMx->CCER;
\r
2453 tmp = (uint16_t)(TIM_ICPolarity << 4);
\r
2454 /* Select the Input and set the filter */
\r
2455 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
\r
2456 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
\r
2457 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
\r
2458 /* Select the Polarity and set the CC2E Bit */
\r
2459 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
\r
2460 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
\r
2461 /* Write to TIMx CCMR1 and CCER registers */
\r
2462 TIMx->CCMR1 = tmpccmr1 ;
\r
2463 TIMx->CCER = tmpccer;
\r
2467 * @brief Configure the TI3 as Input.
\r
2468 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2469 * @param TIM_ICPolarity : The Input Polarity.
\r
2470 * This parameter can be one of the following values:
\r
2471 * @arg TIM_ICPolarity_Rising
\r
2472 * @arg TIM_ICPolarity_Falling
\r
2473 * @param TIM_ICSelection: specifies the input to be used.
\r
2474 * This parameter can be one of the following values:
\r
2475 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
2476 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
2477 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
2478 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2479 * This parameter must be a value between 0x00 and 0x0F.
\r
2482 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2483 uint16_t TIM_ICFilter)
\r
2485 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2487 /* Disable the Channel 3: Reset the CC3E Bit */
\r
2488 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
\r
2489 tmpccmr2 = TIMx->CCMR2;
\r
2490 tmpccer = TIMx->CCER;
\r
2491 tmp = (uint16_t)(TIM_ICPolarity << 8);
\r
2492 /* Select the Input and set the filter */
\r
2493 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
\r
2494 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2495 /* Select the Polarity and set the CC3E Bit */
\r
2496 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
\r
2497 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
\r
2498 /* Write to TIMx CCMR2 and CCER registers */
\r
2499 TIMx->CCMR2 = tmpccmr2;
\r
2500 TIMx->CCER = tmpccer;
\r
2504 * @brief Configure the TI4 as Input.
\r
2505 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2506 * @param TIM_ICPolarity : The Input Polarity.
\r
2507 * This parameter can be one of the following values:
\r
2508 * @arg TIM_ICPolarity_Rising
\r
2509 * @arg TIM_ICPolarity_Falling
\r
2510 * @param TIM_ICSelection: specifies the input to be used.
\r
2511 * This parameter can be one of the following values:
\r
2512 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
2513 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
2514 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
2515 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2516 * This parameter must be a value between 0x00 and 0x0F.
\r
2519 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2520 uint16_t TIM_ICFilter)
\r
2522 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2524 /* Disable the Channel 4: Reset the CC4E Bit */
\r
2525 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
\r
2526 tmpccmr2 = TIMx->CCMR2;
\r
2527 tmpccer = TIMx->CCER;
\r
2528 tmp = (uint16_t)(TIM_ICPolarity << 12);
\r
2529 /* Select the Input and set the filter */
\r
2530 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
\r
2531 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
\r
2532 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
\r
2534 /* Select the Polarity and set the CC4E Bit */
\r
2535 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
\r
2536 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
\r
2537 /* Write to TIMx CCMR2 and CCER registers */
\r
2538 TIMx->CCMR2 = tmpccmr2;
\r
2539 TIMx->CCER = tmpccer ;
\r
2554 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob