1 /** ###################################################################
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2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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3 ** Filename : IO_Map.H
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4 ** Project : RTOSDemo
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5 ** Processor : MC9S12DP256BCPV
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7 ** Version : Driver 01.01
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8 ** Compiler : Metrowerks HC12 C Compiler
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9 ** Date/Time : 13/06/2005, 20:14
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11 ** This bean "IO_Map" implements an IO devices mapping.
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15 ** No public methods
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17 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
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18 ** UNIS, spol. s r.o.
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22 ** http : www.processorexpert.com
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23 ** mail : info@processorexpert.com
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24 ** ###################################################################*/
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26 /* Linker pragmas */
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27 #pragma LINK_INFO DERIVATIVE "MC9S12DP256B"
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28 #pragma LINK_INFO OSCFREQUENCY "16000000"
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31 #define REG_BASE 0x0000 /* Base address for the I/O register block */
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33 /* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */
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34 #ifndef _MC9S12DP256_112_H
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35 #define _MC9S12DP256_112_H
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37 #include "PE_Types.h"
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39 #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
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41 /*********************************************/
\r
43 /* PE I/O map format */
\r
45 /*********************************************/
\r
47 /*** PORTAB - Port AB Register; 0x00000000 ***/
\r
50 /* Overlapped registers: */
\r
52 /*** PORTA - Port A Register; 0x00000000 ***/
\r
56 byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */
\r
57 byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */
\r
58 byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */
\r
59 byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */
\r
60 byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */
\r
61 byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */
\r
62 byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */
\r
63 byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */
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69 #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte
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70 #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0
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71 #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1
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72 #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2
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73 #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3
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74 #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4
\r
75 #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5
\r
76 #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6
\r
77 #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7
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78 #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT
\r
80 /*** PORTB - Port B Register; 0x00000001 ***/
\r
84 byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */
\r
85 byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */
\r
86 byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */
\r
87 byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */
\r
88 byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */
\r
89 byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */
\r
90 byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */
\r
91 byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */
\r
97 #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte
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98 #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0
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99 #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1
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100 #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2
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101 #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3
\r
102 #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4
\r
103 #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5
\r
104 #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6
\r
105 #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7
\r
106 #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT
\r
111 word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */
\r
112 word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */
\r
113 word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */
\r
114 word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */
\r
115 word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */
\r
116 word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */
\r
117 word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */
\r
118 word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */
\r
119 word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */
\r
120 word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */
\r
121 word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */
\r
122 word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */
\r
123 word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */
\r
124 word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */
\r
125 word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */
\r
126 word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */
\r
132 extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);
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133 #define PORTAB _PORTAB.Word
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134 #define PORTAB_BIT0 _PORTAB.Bits.BIT0
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135 #define PORTAB_BIT1 _PORTAB.Bits.BIT1
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136 #define PORTAB_BIT2 _PORTAB.Bits.BIT2
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137 #define PORTAB_BIT3 _PORTAB.Bits.BIT3
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138 #define PORTAB_BIT4 _PORTAB.Bits.BIT4
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139 #define PORTAB_BIT5 _PORTAB.Bits.BIT5
\r
140 #define PORTAB_BIT6 _PORTAB.Bits.BIT6
\r
141 #define PORTAB_BIT7 _PORTAB.Bits.BIT7
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142 #define PORTAB_BIT8 _PORTAB.Bits.BIT8
\r
143 #define PORTAB_BIT9 _PORTAB.Bits.BIT9
\r
144 #define PORTAB_BIT10 _PORTAB.Bits.BIT10
\r
145 #define PORTAB_BIT11 _PORTAB.Bits.BIT11
\r
146 #define PORTAB_BIT12 _PORTAB.Bits.BIT12
\r
147 #define PORTAB_BIT13 _PORTAB.Bits.BIT13
\r
148 #define PORTAB_BIT14 _PORTAB.Bits.BIT14
\r
149 #define PORTAB_BIT15 _PORTAB.Bits.BIT15
\r
150 #define PORTAB_BIT _PORTAB.MergedBits.grpBIT
\r
153 /*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/
\r
156 /* Overlapped registers: */
\r
158 /*** DDRA - Port A Data Direction Register; 0x00000002 ***/
\r
162 byte BIT0 :1; /* Data Direction Port A Bit 0 */
\r
163 byte BIT1 :1; /* Data Direction Port A Bit 1 */
\r
164 byte BIT2 :1; /* Data Direction Port A Bit 2 */
\r
165 byte BIT3 :1; /* Data Direction Port A Bit 3 */
\r
166 byte BIT4 :1; /* Data Direction Port A Bit 4 */
\r
167 byte BIT5 :1; /* Data Direction Port A Bit 5 */
\r
168 byte BIT6 :1; /* Data Direction Port A Bit 6 */
\r
169 byte BIT7 :1; /* Data Direction Port A Bit 7 */
\r
175 #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte
\r
176 #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0
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177 #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
\r
178 #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
\r
179 #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
\r
180 #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
\r
181 #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
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182 #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
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183 #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
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184 #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT
\r
186 /*** DDRB - Port B Data Direction Register; 0x00000003 ***/
\r
190 byte BIT0 :1; /* Data Direction Port B Bit 0 */
\r
191 byte BIT1 :1; /* Data Direction Port B Bit 1 */
\r
192 byte BIT2 :1; /* Data Direction Port B Bit 2 */
\r
193 byte BIT3 :1; /* Data Direction Port B Bit 3 */
\r
194 byte BIT4 :1; /* Data Direction Port B Bit 4 */
\r
195 byte BIT5 :1; /* Data Direction Port B Bit 5 */
\r
196 byte BIT6 :1; /* Data Direction Port B Bit 6 */
\r
197 byte BIT7 :1; /* Data Direction Port B Bit 7 */
\r
203 #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
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204 #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
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205 #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
\r
206 #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
\r
207 #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
\r
208 #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
\r
209 #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
\r
210 #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
\r
211 #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
\r
212 #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT
\r
217 word BIT0 :1; /* Data Direction Port B Bit 0 */
\r
218 word BIT1 :1; /* Data Direction Port B Bit 1 */
\r
219 word BIT2 :1; /* Data Direction Port B Bit 2 */
\r
220 word BIT3 :1; /* Data Direction Port B Bit 3 */
\r
221 word BIT4 :1; /* Data Direction Port B Bit 4 */
\r
222 word BIT5 :1; /* Data Direction Port B Bit 5 */
\r
223 word BIT6 :1; /* Data Direction Port B Bit 6 */
\r
224 word BIT7 :1; /* Data Direction Port B Bit 7 */
\r
225 word BIT8 :1; /* Data Direction Port A Bit 8 */
\r
226 word BIT9 :1; /* Data Direction Port A Bit 9 */
\r
227 word BIT10 :1; /* Data Direction Port A Bit 10 */
\r
228 word BIT11 :1; /* Data Direction Port A Bit 11 */
\r
229 word BIT12 :1; /* Data Direction Port A Bit 12 */
\r
230 word BIT13 :1; /* Data Direction Port A Bit 13 */
\r
231 word BIT14 :1; /* Data Direction Port A Bit 14 */
\r
232 word BIT15 :1; /* Data Direction Port A Bit 15 */
\r
238 extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
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239 #define DDRAB _DDRAB.Word
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240 #define DDRAB_BIT0 _DDRAB.Bits.BIT0
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241 #define DDRAB_BIT1 _DDRAB.Bits.BIT1
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242 #define DDRAB_BIT2 _DDRAB.Bits.BIT2
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243 #define DDRAB_BIT3 _DDRAB.Bits.BIT3
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244 #define DDRAB_BIT4 _DDRAB.Bits.BIT4
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245 #define DDRAB_BIT5 _DDRAB.Bits.BIT5
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246 #define DDRAB_BIT6 _DDRAB.Bits.BIT6
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247 #define DDRAB_BIT7 _DDRAB.Bits.BIT7
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248 #define DDRAB_BIT8 _DDRAB.Bits.BIT8
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249 #define DDRAB_BIT9 _DDRAB.Bits.BIT9
\r
250 #define DDRAB_BIT10 _DDRAB.Bits.BIT10
\r
251 #define DDRAB_BIT11 _DDRAB.Bits.BIT11
\r
252 #define DDRAB_BIT12 _DDRAB.Bits.BIT12
\r
253 #define DDRAB_BIT13 _DDRAB.Bits.BIT13
\r
254 #define DDRAB_BIT14 _DDRAB.Bits.BIT14
\r
255 #define DDRAB_BIT15 _DDRAB.Bits.BIT15
\r
256 #define DDRAB_BIT _DDRAB.MergedBits.grpBIT
\r
259 /*** TCNT - Timer Count Register; 0x00000044 ***/
\r
262 /* Overlapped registers: */
\r
264 /*** TCNTHi - Timer Count Register High; 0x00000044 ***/
\r
268 byte BIT15 :1; /* Timer Count Register Bit 15 */
\r
269 byte BIT14 :1; /* Timer Count Register Bit 14 */
\r
270 byte BIT13 :1; /* Timer Count Register Bit 13 */
\r
271 byte BIT12 :1; /* Timer Count Register Bit 12 */
\r
272 byte BIT11 :1; /* Timer Count Register Bit 11 */
\r
273 byte BIT10 :1; /* Timer Count Register Bit 10 */
\r
274 byte BIT9 :1; /* Timer Count Register Bit 9 */
\r
275 byte BIT8 :1; /* Timer Count Register Bit 8 */
\r
278 #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte
\r
279 #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15
\r
280 #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14
\r
281 #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13
\r
282 #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12
\r
283 #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11
\r
284 #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10
\r
285 #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9
\r
286 #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8
\r
288 /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/
\r
292 byte BIT0 :1; /* Timer Count Register Bit 0 */
\r
293 byte BIT1 :1; /* Timer Count Register Bit 1 */
\r
294 byte BIT2 :1; /* Timer Count Register Bit 2 */
\r
295 byte BIT3 :1; /* Timer Count Register Bit 3 */
\r
296 byte BIT4 :1; /* Timer Count Bit Register 4 */
\r
297 byte BIT5 :1; /* Timer Count Bit Register 5 */
\r
298 byte BIT6 :1; /* Timer Count Bit Register 6 */
\r
299 byte BIT7 :1; /* Timer Count Bit Register 7 */
\r
305 #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte
\r
306 #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0
\r
307 #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1
\r
308 #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2
\r
309 #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3
\r
310 #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4
\r
311 #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5
\r
312 #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6
\r
313 #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7
\r
314 #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT
\r
322 extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);
\r
323 #define TCNT _TCNT.Word
\r
324 #define TCNT_BIT _TCNT.MergedBits.grpBIT
\r
327 /*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/
\r
330 /* Overlapped registers: */
\r
332 /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/
\r
336 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */
\r
337 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */
\r
338 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */
\r
339 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */
\r
340 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */
\r
341 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */
\r
342 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */
\r
343 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */
\r
349 #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte
\r
350 #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8
\r
351 #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9
\r
352 #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10
\r
353 #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11
\r
354 #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12
\r
355 #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13
\r
356 #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14
\r
357 #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15
\r
358 #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8
\r
359 #define TC0Hi_BIT TC0Hi_BIT_8
\r
361 /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/
\r
365 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */
\r
366 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */
\r
367 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */
\r
368 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */
\r
369 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */
\r
370 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */
\r
371 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */
\r
372 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */
\r
378 #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte
\r
379 #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0
\r
380 #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1
\r
381 #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2
\r
382 #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3
\r
383 #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4
\r
384 #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5
\r
385 #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6
\r
386 #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7
\r
387 #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT
\r
395 extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);
\r
396 #define TC0 _TC0.Word
\r
397 #define TC0_BIT _TC0.MergedBits.grpBIT
\r
400 /*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/
\r
403 /* Overlapped registers: */
\r
405 /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/
\r
409 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */
\r
410 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */
\r
411 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */
\r
412 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */
\r
413 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */
\r
414 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */
\r
415 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */
\r
416 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */
\r
422 #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte
\r
423 #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8
\r
424 #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9
\r
425 #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10
\r
426 #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11
\r
427 #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12
\r
428 #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13
\r
429 #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14
\r
430 #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15
\r
431 #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8
\r
432 #define TC1Hi_BIT TC1Hi_BIT_8
\r
434 /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/
\r
438 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */
\r
439 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */
\r
440 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */
\r
441 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */
\r
442 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */
\r
443 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */
\r
444 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */
\r
445 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */
\r
451 #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte
\r
452 #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0
\r
453 #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1
\r
454 #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2
\r
455 #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3
\r
456 #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4
\r
457 #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5
\r
458 #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6
\r
459 #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7
\r
460 #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT
\r
468 extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);
\r
469 #define TC1 _TC1.Word
\r
470 #define TC1_BIT _TC1.MergedBits.grpBIT
\r
473 /*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/
\r
476 /* Overlapped registers: */
\r
478 /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/
\r
482 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */
\r
483 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */
\r
484 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */
\r
485 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */
\r
486 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */
\r
487 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */
\r
488 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */
\r
489 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */
\r
495 #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte
\r
496 #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8
\r
497 #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9
\r
498 #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10
\r
499 #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11
\r
500 #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12
\r
501 #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13
\r
502 #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14
\r
503 #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15
\r
504 #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8
\r
505 #define TC2Hi_BIT TC2Hi_BIT_8
\r
507 /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/
\r
511 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */
\r
512 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */
\r
513 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */
\r
514 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */
\r
515 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */
\r
516 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */
\r
517 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */
\r
518 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */
\r
524 #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte
\r
525 #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0
\r
526 #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1
\r
527 #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2
\r
528 #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3
\r
529 #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4
\r
530 #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5
\r
531 #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6
\r
532 #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7
\r
533 #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT
\r
541 extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);
\r
542 #define TC2 _TC2.Word
\r
543 #define TC2_BIT _TC2.MergedBits.grpBIT
\r
546 /*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/
\r
549 /* Overlapped registers: */
\r
551 /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/
\r
555 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */
\r
556 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */
\r
557 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */
\r
558 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */
\r
559 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */
\r
560 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */
\r
561 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */
\r
562 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */
\r
568 #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte
\r
569 #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8
\r
570 #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9
\r
571 #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10
\r
572 #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11
\r
573 #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12
\r
574 #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13
\r
575 #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14
\r
576 #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15
\r
577 #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8
\r
578 #define TC3Hi_BIT TC3Hi_BIT_8
\r
580 /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/
\r
584 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */
\r
585 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */
\r
586 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */
\r
587 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */
\r
588 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */
\r
589 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */
\r
590 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */
\r
591 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */
\r
597 #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte
\r
598 #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0
\r
599 #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1
\r
600 #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2
\r
601 #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3
\r
602 #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4
\r
603 #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5
\r
604 #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6
\r
605 #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7
\r
606 #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT
\r
614 extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);
\r
615 #define TC3 _TC3.Word
\r
616 #define TC3_BIT _TC3.MergedBits.grpBIT
\r
619 /*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/
\r
622 /* Overlapped registers: */
\r
624 /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/
\r
628 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */
\r
629 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */
\r
630 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */
\r
631 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */
\r
632 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */
\r
633 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */
\r
634 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */
\r
635 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */
\r
641 #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte
\r
642 #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8
\r
643 #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9
\r
644 #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10
\r
645 #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11
\r
646 #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12
\r
647 #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13
\r
648 #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14
\r
649 #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15
\r
650 #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8
\r
651 #define TC4Hi_BIT TC4Hi_BIT_8
\r
653 /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/
\r
657 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */
\r
658 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */
\r
659 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */
\r
660 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */
\r
661 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */
\r
662 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */
\r
663 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */
\r
664 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */
\r
670 #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte
\r
671 #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0
\r
672 #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1
\r
673 #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2
\r
674 #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3
\r
675 #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4
\r
676 #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5
\r
677 #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6
\r
678 #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7
\r
679 #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT
\r
687 extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);
\r
688 #define TC4 _TC4.Word
\r
689 #define TC4_BIT _TC4.MergedBits.grpBIT
\r
692 /*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/
\r
695 /* Overlapped registers: */
\r
697 /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/
\r
701 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */
\r
702 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */
\r
703 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */
\r
704 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */
\r
705 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */
\r
706 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */
\r
707 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */
\r
708 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */
\r
714 #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte
\r
715 #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8
\r
716 #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9
\r
717 #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10
\r
718 #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11
\r
719 #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12
\r
720 #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13
\r
721 #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14
\r
722 #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15
\r
723 #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8
\r
724 #define TC5Hi_BIT TC5Hi_BIT_8
\r
726 /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/
\r
730 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */
\r
731 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */
\r
732 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */
\r
733 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */
\r
734 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */
\r
735 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */
\r
736 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */
\r
737 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */
\r
743 #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte
\r
744 #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0
\r
745 #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1
\r
746 #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2
\r
747 #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3
\r
748 #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4
\r
749 #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5
\r
750 #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6
\r
751 #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7
\r
752 #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT
\r
760 extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);
\r
761 #define TC5 _TC5.Word
\r
762 #define TC5_BIT _TC5.MergedBits.grpBIT
\r
765 /*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/
\r
768 /* Overlapped registers: */
\r
770 /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/
\r
774 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */
\r
775 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */
\r
776 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */
\r
777 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */
\r
778 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */
\r
779 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */
\r
780 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */
\r
781 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */
\r
787 #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte
\r
788 #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8
\r
789 #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9
\r
790 #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10
\r
791 #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11
\r
792 #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12
\r
793 #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13
\r
794 #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14
\r
795 #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15
\r
796 #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8
\r
797 #define TC6Hi_BIT TC6Hi_BIT_8
\r
799 /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/
\r
803 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */
\r
804 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */
\r
805 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */
\r
806 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */
\r
807 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */
\r
808 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */
\r
809 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */
\r
810 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */
\r
816 #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte
\r
817 #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0
\r
818 #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1
\r
819 #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2
\r
820 #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3
\r
821 #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4
\r
822 #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5
\r
823 #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6
\r
824 #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7
\r
825 #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT
\r
833 extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);
\r
834 #define TC6 _TC6.Word
\r
835 #define TC6_BIT _TC6.MergedBits.grpBIT
\r
838 /*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/
\r
841 /* Overlapped registers: */
\r
843 /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/
\r
847 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */
\r
848 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */
\r
849 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */
\r
850 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */
\r
851 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */
\r
852 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */
\r
853 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */
\r
854 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */
\r
860 #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte
\r
861 #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8
\r
862 #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9
\r
863 #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10
\r
864 #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11
\r
865 #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12
\r
866 #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13
\r
867 #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14
\r
868 #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15
\r
869 #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8
\r
870 #define TC7Hi_BIT TC7Hi_BIT_8
\r
872 /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/
\r
876 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */
\r
877 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */
\r
878 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */
\r
879 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */
\r
880 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */
\r
881 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */
\r
882 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */
\r
883 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */
\r
889 #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte
\r
890 #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0
\r
891 #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1
\r
892 #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2
\r
893 #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3
\r
894 #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4
\r
895 #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5
\r
896 #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6
\r
897 #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7
\r
898 #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT
\r
906 extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);
\r
907 #define TC7 _TC7.Word
\r
908 #define TC7_BIT _TC7.MergedBits.grpBIT
\r
911 /*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/
\r
914 /* Overlapped registers: */
\r
916 /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/
\r
923 #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte
\r
924 #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT
\r
926 /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/
\r
933 #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte
\r
934 #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT
\r
942 extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062);
\r
943 #define PACN32 _PACN32.Word
\r
944 #define PACN32_BIT _PACN32.MergedBits.grpBIT
\r
947 /*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/
\r
950 /* Overlapped registers: */
\r
952 /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/
\r
959 #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte
\r
960 #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT
\r
962 /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/
\r
969 #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte
\r
970 #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT
\r
978 extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064);
\r
979 #define PACN10 _PACN10.Word
\r
980 #define PACN10_BIT _PACN10.MergedBits.grpBIT
\r
983 /*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/
\r
986 /* Overlapped registers: */
\r
988 /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/
\r
992 byte BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
993 byte BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
994 byte BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
995 byte BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
996 byte BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
997 byte BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
998 byte BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
999 byte BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1005 #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte
\r
1006 #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0
\r
1007 #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1
\r
1008 #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2
\r
1009 #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3
\r
1010 #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4
\r
1011 #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5
\r
1012 #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6
\r
1013 #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7
\r
1014 #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT
\r
1016 /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/
\r
1020 byte BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
1021 byte BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
1022 byte BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
1023 byte BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
1024 byte BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
1025 byte BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
1026 byte BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
1027 byte BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1033 #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte
\r
1034 #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0
\r
1035 #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1
\r
1036 #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2
\r
1037 #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3
\r
1038 #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4
\r
1039 #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5
\r
1040 #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6
\r
1041 #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7
\r
1042 #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT
\r
1047 word BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
1048 word BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
1049 word BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
1050 word BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
1051 word BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
1052 word BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
1053 word BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
1054 word BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1055 word BIT8 :1; /* Pulse Accumulator Bit 8 */
\r
1056 word BIT9 :1; /* Pulse Accumulator Bit 9 */
\r
1057 word BIT10 :1; /* Pulse Accumulator Bit 10 */
\r
1058 word BIT11 :1; /* Pulse Accumulator Bit 11 */
\r
1059 word BIT12 :1; /* Pulse Accumulator Bit 12 */
\r
1060 word BIT13 :1; /* Pulse Accumulator Bit 13 */
\r
1061 word BIT14 :1; /* Pulse Accumulator Bit 14 */
\r
1062 word BIT15 :1; /* Pulse Accumulator Bit 15 */
\r
1068 extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072);
\r
1069 #define PA32H _PA32H.Word
\r
1070 #define PA32H_BIT0 _PA32H.Bits.BIT0
\r
1071 #define PA32H_BIT1 _PA32H.Bits.BIT1
\r
1072 #define PA32H_BIT2 _PA32H.Bits.BIT2
\r
1073 #define PA32H_BIT3 _PA32H.Bits.BIT3
\r
1074 #define PA32H_BIT4 _PA32H.Bits.BIT4
\r
1075 #define PA32H_BIT5 _PA32H.Bits.BIT5
\r
1076 #define PA32H_BIT6 _PA32H.Bits.BIT6
\r
1077 #define PA32H_BIT7 _PA32H.Bits.BIT7
\r
1078 #define PA32H_BIT8 _PA32H.Bits.BIT8
\r
1079 #define PA32H_BIT9 _PA32H.Bits.BIT9
\r
1080 #define PA32H_BIT10 _PA32H.Bits.BIT10
\r
1081 #define PA32H_BIT11 _PA32H.Bits.BIT11
\r
1082 #define PA32H_BIT12 _PA32H.Bits.BIT12
\r
1083 #define PA32H_BIT13 _PA32H.Bits.BIT13
\r
1084 #define PA32H_BIT14 _PA32H.Bits.BIT14
\r
1085 #define PA32H_BIT15 _PA32H.Bits.BIT15
\r
1086 #define PA32H_BIT _PA32H.MergedBits.grpBIT
\r
1089 /*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/
\r
1092 /* Overlapped registers: */
\r
1094 /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/
\r
1098 byte BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
1099 byte BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
1100 byte BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
1101 byte BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
1102 byte BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
1103 byte BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
1104 byte BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
1105 byte BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1111 #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte
\r
1112 #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0
\r
1113 #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1
\r
1114 #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2
\r
1115 #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3
\r
1116 #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4
\r
1117 #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5
\r
1118 #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6
\r
1119 #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7
\r
1120 #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT
\r
1122 /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/
\r
1126 byte BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
1127 byte BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
1128 byte BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
1129 byte BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
1130 byte BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
1131 byte BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
1132 byte BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
1133 byte BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1139 #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte
\r
1140 #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0
\r
1141 #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1
\r
1142 #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2
\r
1143 #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3
\r
1144 #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4
\r
1145 #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5
\r
1146 #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6
\r
1147 #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7
\r
1148 #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT
\r
1153 word BIT0 :1; /* Pulse Accumulator Bit 0 */
\r
1154 word BIT1 :1; /* Pulse Accumulator Bit 1 */
\r
1155 word BIT2 :1; /* Pulse Accumulator Bit 2 */
\r
1156 word BIT3 :1; /* Pulse Accumulator Bit 3 */
\r
1157 word BIT4 :1; /* Pulse Accumulator Bit 4 */
\r
1158 word BIT5 :1; /* Pulse Accumulator Bit 5 */
\r
1159 word BIT6 :1; /* Pulse Accumulator Bit 6 */
\r
1160 word BIT7 :1; /* Pulse Accumulator Bit 7 */
\r
1161 word BIT8 :1; /* Pulse Accumulator Bit 8 */
\r
1162 word BIT9 :1; /* Pulse Accumulator Bit 9 */
\r
1163 word BIT10 :1; /* Pulse Accumulator Bit 10 */
\r
1164 word BIT11 :1; /* Pulse Accumulator Bit 11 */
\r
1165 word BIT12 :1; /* Pulse Accumulator Bit 12 */
\r
1166 word BIT13 :1; /* Pulse Accumulator Bit 13 */
\r
1167 word BIT14 :1; /* Pulse Accumulator Bit 14 */
\r
1168 word BIT15 :1; /* Pulse Accumulator Bit 15 */
\r
1174 extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074);
\r
1175 #define PA10H _PA10H.Word
\r
1176 #define PA10H_BIT0 _PA10H.Bits.BIT0
\r
1177 #define PA10H_BIT1 _PA10H.Bits.BIT1
\r
1178 #define PA10H_BIT2 _PA10H.Bits.BIT2
\r
1179 #define PA10H_BIT3 _PA10H.Bits.BIT3
\r
1180 #define PA10H_BIT4 _PA10H.Bits.BIT4
\r
1181 #define PA10H_BIT5 _PA10H.Bits.BIT5
\r
1182 #define PA10H_BIT6 _PA10H.Bits.BIT6
\r
1183 #define PA10H_BIT7 _PA10H.Bits.BIT7
\r
1184 #define PA10H_BIT8 _PA10H.Bits.BIT8
\r
1185 #define PA10H_BIT9 _PA10H.Bits.BIT9
\r
1186 #define PA10H_BIT10 _PA10H.Bits.BIT10
\r
1187 #define PA10H_BIT11 _PA10H.Bits.BIT11
\r
1188 #define PA10H_BIT12 _PA10H.Bits.BIT12
\r
1189 #define PA10H_BIT13 _PA10H.Bits.BIT13
\r
1190 #define PA10H_BIT14 _PA10H.Bits.BIT14
\r
1191 #define PA10H_BIT15 _PA10H.Bits.BIT15
\r
1192 #define PA10H_BIT _PA10H.MergedBits.grpBIT
\r
1195 /*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/
\r
1198 /* Overlapped registers: */
\r
1200 /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/
\r
1204 byte BIT8 :1; /* Modulus Down-Counter Bit 8 */
\r
1205 byte BIT9 :1; /* Modulus Down-Counter Bit 9 */
\r
1206 byte BIT10 :1; /* Modulus Down-Counter Bit 10 */
\r
1207 byte BIT11 :1; /* Modulus Down-Counter Bit 11 */
\r
1208 byte BIT12 :1; /* Modulus Down-Counter Bit 12 */
\r
1209 byte BIT13 :1; /* Modulus Down-Counter Bit 13 */
\r
1210 byte BIT14 :1; /* Modulus Down-Counter Bit 14 */
\r
1211 byte BIT15 :1; /* Modulus Down-Counter Bit 15 */
\r
1217 #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte
\r
1218 #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8
\r
1219 #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9
\r
1220 #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10
\r
1221 #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11
\r
1222 #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12
\r
1223 #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13
\r
1224 #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14
\r
1225 #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15
\r
1226 #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8
\r
1227 #define MCCNThi_BIT MCCNThi_BIT_8
\r
1229 /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/
\r
1233 byte BIT0 :1; /* Modulus Down-Counter Bit 0 */
\r
1234 byte BIT1 :1; /* Modulus Down-Counter Bit 1 */
\r
1235 byte BIT2 :1; /* Modulus Down-Counter Bit 2 */
\r
1236 byte BIT3 :1; /* Modulus Down-Counter Bit 3 */
\r
1237 byte BIT4 :1; /* Modulus Down-Counter Bit 4 */
\r
1238 byte BIT5 :1; /* Modulus Down-Counter Bit 5 */
\r
1239 byte BIT6 :1; /* Modulus Down-Counter Bit 6 */
\r
1240 byte BIT7 :1; /* Modulus Down-Counter Bit 7 */
\r
1246 #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte
\r
1247 #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0
\r
1248 #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1
\r
1249 #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2
\r
1250 #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3
\r
1251 #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4
\r
1252 #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5
\r
1253 #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6
\r
1254 #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7
\r
1255 #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT
\r
1263 extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076);
\r
1264 #define MCCNT _MCCNT.Word
\r
1265 #define MCCNT_BIT _MCCNT.MergedBits.grpBIT
\r
1268 /*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/
\r
1271 /* Overlapped registers: */
\r
1273 /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/
\r
1277 byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1278 byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1279 byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1280 byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1281 byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1282 byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1283 byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1284 byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1290 #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte
\r
1291 #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8
\r
1292 #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9
\r
1293 #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10
\r
1294 #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11
\r
1295 #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12
\r
1296 #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13
\r
1297 #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14
\r
1298 #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15
\r
1299 #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8
\r
1300 #define TC0Hhi_BIT TC0Hhi_BIT_8
\r
1302 /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/
\r
1306 byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1307 byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1308 byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1309 byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1310 byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1311 byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1312 byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1313 byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1319 #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte
\r
1320 #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0
\r
1321 #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1
\r
1322 #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2
\r
1323 #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3
\r
1324 #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4
\r
1325 #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5
\r
1326 #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6
\r
1327 #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7
\r
1328 #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT
\r
1333 word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1334 word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1335 word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1336 word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1337 word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1338 word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1339 word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1340 word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1341 word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1342 word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1343 word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1344 word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1345 word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1346 word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1347 word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1348 word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1354 extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078);
\r
1355 #define TC0H _TC0H.Word
\r
1356 #define TC0H_BIT0 _TC0H.Bits.BIT0
\r
1357 #define TC0H_BIT1 _TC0H.Bits.BIT1
\r
1358 #define TC0H_BIT2 _TC0H.Bits.BIT2
\r
1359 #define TC0H_BIT3 _TC0H.Bits.BIT3
\r
1360 #define TC0H_BIT4 _TC0H.Bits.BIT4
\r
1361 #define TC0H_BIT5 _TC0H.Bits.BIT5
\r
1362 #define TC0H_BIT6 _TC0H.Bits.BIT6
\r
1363 #define TC0H_BIT7 _TC0H.Bits.BIT7
\r
1364 #define TC0H_BIT8 _TC0H.Bits.BIT8
\r
1365 #define TC0H_BIT9 _TC0H.Bits.BIT9
\r
1366 #define TC0H_BIT10 _TC0H.Bits.BIT10
\r
1367 #define TC0H_BIT11 _TC0H.Bits.BIT11
\r
1368 #define TC0H_BIT12 _TC0H.Bits.BIT12
\r
1369 #define TC0H_BIT13 _TC0H.Bits.BIT13
\r
1370 #define TC0H_BIT14 _TC0H.Bits.BIT14
\r
1371 #define TC0H_BIT15 _TC0H.Bits.BIT15
\r
1372 #define TC0H_BIT _TC0H.MergedBits.grpBIT
\r
1375 /*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/
\r
1378 /* Overlapped registers: */
\r
1380 /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/
\r
1384 byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1385 byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1386 byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1387 byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1388 byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1389 byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1390 byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1391 byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1397 #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte
\r
1398 #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8
\r
1399 #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9
\r
1400 #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10
\r
1401 #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11
\r
1402 #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12
\r
1403 #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13
\r
1404 #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14
\r
1405 #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15
\r
1406 #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8
\r
1407 #define TC1Hhi_BIT TC1Hhi_BIT_8
\r
1409 /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/
\r
1413 byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1414 byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1415 byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1416 byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1417 byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1418 byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1419 byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1420 byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1426 #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte
\r
1427 #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0
\r
1428 #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1
\r
1429 #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2
\r
1430 #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3
\r
1431 #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4
\r
1432 #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5
\r
1433 #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6
\r
1434 #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7
\r
1435 #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT
\r
1440 word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1441 word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1442 word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1443 word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1444 word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1445 word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1446 word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1447 word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1448 word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1449 word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1450 word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1451 word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1452 word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1453 word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1454 word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1455 word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1461 extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A);
\r
1462 #define TC1H _TC1H.Word
\r
1463 #define TC1H_BIT0 _TC1H.Bits.BIT0
\r
1464 #define TC1H_BIT1 _TC1H.Bits.BIT1
\r
1465 #define TC1H_BIT2 _TC1H.Bits.BIT2
\r
1466 #define TC1H_BIT3 _TC1H.Bits.BIT3
\r
1467 #define TC1H_BIT4 _TC1H.Bits.BIT4
\r
1468 #define TC1H_BIT5 _TC1H.Bits.BIT5
\r
1469 #define TC1H_BIT6 _TC1H.Bits.BIT6
\r
1470 #define TC1H_BIT7 _TC1H.Bits.BIT7
\r
1471 #define TC1H_BIT8 _TC1H.Bits.BIT8
\r
1472 #define TC1H_BIT9 _TC1H.Bits.BIT9
\r
1473 #define TC1H_BIT10 _TC1H.Bits.BIT10
\r
1474 #define TC1H_BIT11 _TC1H.Bits.BIT11
\r
1475 #define TC1H_BIT12 _TC1H.Bits.BIT12
\r
1476 #define TC1H_BIT13 _TC1H.Bits.BIT13
\r
1477 #define TC1H_BIT14 _TC1H.Bits.BIT14
\r
1478 #define TC1H_BIT15 _TC1H.Bits.BIT15
\r
1479 #define TC1H_BIT _TC1H.MergedBits.grpBIT
\r
1482 /*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/
\r
1485 /* Overlapped registers: */
\r
1487 /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/
\r
1491 byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1492 byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1493 byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1494 byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1495 byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1496 byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1497 byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1498 byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1504 #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte
\r
1505 #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8
\r
1506 #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9
\r
1507 #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10
\r
1508 #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11
\r
1509 #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12
\r
1510 #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13
\r
1511 #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14
\r
1512 #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15
\r
1513 #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8
\r
1514 #define TC2Hhi_BIT TC2Hhi_BIT_8
\r
1516 /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/
\r
1520 byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1521 byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1522 byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1523 byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1524 byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1525 byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1526 byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1527 byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1533 #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte
\r
1534 #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0
\r
1535 #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1
\r
1536 #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2
\r
1537 #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3
\r
1538 #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4
\r
1539 #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5
\r
1540 #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6
\r
1541 #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7
\r
1542 #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT
\r
1547 word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1548 word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1549 word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1550 word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1551 word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1552 word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1553 word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1554 word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1555 word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1556 word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1557 word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1558 word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1559 word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1560 word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1561 word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1562 word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1568 extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C);
\r
1569 #define TC2H _TC2H.Word
\r
1570 #define TC2H_BIT0 _TC2H.Bits.BIT0
\r
1571 #define TC2H_BIT1 _TC2H.Bits.BIT1
\r
1572 #define TC2H_BIT2 _TC2H.Bits.BIT2
\r
1573 #define TC2H_BIT3 _TC2H.Bits.BIT3
\r
1574 #define TC2H_BIT4 _TC2H.Bits.BIT4
\r
1575 #define TC2H_BIT5 _TC2H.Bits.BIT5
\r
1576 #define TC2H_BIT6 _TC2H.Bits.BIT6
\r
1577 #define TC2H_BIT7 _TC2H.Bits.BIT7
\r
1578 #define TC2H_BIT8 _TC2H.Bits.BIT8
\r
1579 #define TC2H_BIT9 _TC2H.Bits.BIT9
\r
1580 #define TC2H_BIT10 _TC2H.Bits.BIT10
\r
1581 #define TC2H_BIT11 _TC2H.Bits.BIT11
\r
1582 #define TC2H_BIT12 _TC2H.Bits.BIT12
\r
1583 #define TC2H_BIT13 _TC2H.Bits.BIT13
\r
1584 #define TC2H_BIT14 _TC2H.Bits.BIT14
\r
1585 #define TC2H_BIT15 _TC2H.Bits.BIT15
\r
1586 #define TC2H_BIT _TC2H.MergedBits.grpBIT
\r
1589 /*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/
\r
1592 /* Overlapped registers: */
\r
1594 /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/
\r
1598 byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1599 byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1600 byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1601 byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1602 byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1603 byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1604 byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1605 byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1611 #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte
\r
1612 #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8
\r
1613 #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9
\r
1614 #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10
\r
1615 #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11
\r
1616 #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12
\r
1617 #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13
\r
1618 #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14
\r
1619 #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15
\r
1620 #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8
\r
1621 #define TC3Hhi_BIT TC3Hhi_BIT_8
\r
1623 /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/
\r
1627 byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1628 byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1629 byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1630 byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1631 byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1632 byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1633 byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1634 byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1640 #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte
\r
1641 #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0
\r
1642 #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1
\r
1643 #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2
\r
1644 #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3
\r
1645 #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4
\r
1646 #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5
\r
1647 #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6
\r
1648 #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7
\r
1649 #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT
\r
1654 word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
\r
1655 word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
\r
1656 word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
\r
1657 word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
\r
1658 word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
\r
1659 word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
\r
1660 word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
\r
1661 word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
\r
1662 word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
\r
1663 word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
\r
1664 word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
\r
1665 word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
\r
1666 word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
\r
1667 word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
\r
1668 word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
\r
1669 word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
\r
1675 extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E);
\r
1676 #define TC3H _TC3H.Word
\r
1677 #define TC3H_BIT0 _TC3H.Bits.BIT0
\r
1678 #define TC3H_BIT1 _TC3H.Bits.BIT1
\r
1679 #define TC3H_BIT2 _TC3H.Bits.BIT2
\r
1680 #define TC3H_BIT3 _TC3H.Bits.BIT3
\r
1681 #define TC3H_BIT4 _TC3H.Bits.BIT4
\r
1682 #define TC3H_BIT5 _TC3H.Bits.BIT5
\r
1683 #define TC3H_BIT6 _TC3H.Bits.BIT6
\r
1684 #define TC3H_BIT7 _TC3H.Bits.BIT7
\r
1685 #define TC3H_BIT8 _TC3H.Bits.BIT8
\r
1686 #define TC3H_BIT9 _TC3H.Bits.BIT9
\r
1687 #define TC3H_BIT10 _TC3H.Bits.BIT10
\r
1688 #define TC3H_BIT11 _TC3H.Bits.BIT11
\r
1689 #define TC3H_BIT12 _TC3H.Bits.BIT12
\r
1690 #define TC3H_BIT13 _TC3H.Bits.BIT13
\r
1691 #define TC3H_BIT14 _TC3H.Bits.BIT14
\r
1692 #define TC3H_BIT15 _TC3H.Bits.BIT15
\r
1693 #define TC3H_BIT _TC3H.MergedBits.grpBIT
\r
1696 /*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/
\r
1699 /* Overlapped registers: */
\r
1701 /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/
\r
1705 byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */
\r
1706 byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */
\r
1707 byte ETRIGE :1; /* External Trigger Mode enable */
\r
1708 byte ETRIGP :1; /* External Trigger Polarity */
\r
1709 byte ETRIGLE :1; /* External Trigger Level/Edge control */
\r
1710 byte AWAI :1; /* ATD 0 Wait Mode */
\r
1711 byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */
\r
1712 byte ADPU :1; /* ATD 0 Disable / Power Down */
\r
1715 #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte
\r
1716 #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF
\r
1717 #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE
\r
1718 #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE
\r
1719 #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP
\r
1720 #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE
\r
1721 #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI
\r
1722 #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC
\r
1723 #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU
\r
1725 /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/
\r
1729 byte FRZ0 :1; /* Background Debug Freeze Enable */
\r
1730 byte FRZ1 :1; /* Background Debug Freeze Enable */
\r
1731 byte FIFO :1; /* Result Register FIFO Mode */
\r
1732 byte S1C :1; /* Conversion Sequence Length 1 */
\r
1733 byte S2C :1; /* Conversion Sequence Length 2 */
\r
1734 byte S4C :1; /* Conversion Sequence Length 4 */
\r
1735 byte S8C :1; /* Conversion Sequence Length 8 */
\r
1748 #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte
\r
1749 #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0
\r
1750 #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1
\r
1751 #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO
\r
1752 #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C
\r
1753 #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C
\r
1754 #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C
\r
1755 #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C
\r
1756 #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ
\r
1761 word FRZ0 :1; /* Background Debug Freeze Enable */
\r
1762 word FRZ1 :1; /* Background Debug Freeze Enable */
\r
1763 word FIFO :1; /* Result Register FIFO Mode */
\r
1764 word S1C :1; /* Conversion Sequence Length 1 */
\r
1765 word S2C :1; /* Conversion Sequence Length 2 */
\r
1766 word S4C :1; /* Conversion Sequence Length 4 */
\r
1767 word S8C :1; /* Conversion Sequence Length 8 */
\r
1769 word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */
\r
1770 word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */
\r
1771 word ETRIGE :1; /* External Trigger Mode enable */
\r
1772 word ETRIGP :1; /* External Trigger Polarity */
\r
1773 word ETRIGLE :1; /* External Trigger Level/Edge control */
\r
1774 word AWAI :1; /* ATD 0 Wait Mode */
\r
1775 word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */
\r
1776 word ADPU :1; /* ATD 0 Disable / Power Down */
\r
1796 extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082);
\r
1797 #define ATD0CTL23 _ATD0CTL23.Word
\r
1798 #define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0
\r
1799 #define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1
\r
1800 #define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO
\r
1801 #define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C
\r
1802 #define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C
\r
1803 #define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C
\r
1804 #define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C
\r
1805 #define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF
\r
1806 #define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE
\r
1807 #define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE
\r
1808 #define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP
\r
1809 #define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE
\r
1810 #define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI
\r
1811 #define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC
\r
1812 #define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU
\r
1813 #define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ
\r
1816 /*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/
\r
1819 /* Overlapped registers: */
\r
1821 /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/
\r
1825 byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */
\r
1826 byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */
\r
1827 byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */
\r
1828 byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */
\r
1829 byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */
\r
1830 byte SMP0 :1; /* Sample Time Select 0 */
\r
1831 byte SMP1 :1; /* Sample Time Select 1 */
\r
1832 byte SRES8 :1; /* ATD 0 Resolution Select */
\r
1837 byte grpSRES_8 :1;
\r
1840 #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte
\r
1841 #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0
\r
1842 #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1
\r
1843 #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2
\r
1844 #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3
\r
1845 #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4
\r
1846 #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0
\r
1847 #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1
\r
1848 #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8
\r
1849 #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS
\r
1850 #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP
\r
1852 /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/
\r
1856 byte CA :1; /* Analog Input Channel Select Code A */
\r
1857 byte CB :1; /* Analog Input Channel Select Code B */
\r
1858 byte CC :1; /* Analog Input Channel Select Code C */
\r
1860 byte MULT :1; /* Multi-Channel Sample Mode */
\r
1861 byte SCAN :1; /* Continuous Conversion Sequence Mode */
\r
1862 byte DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
1863 byte DJM :1; /* Result Register Data Justification Mode */
\r
1866 #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte
\r
1867 #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA
\r
1868 #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB
\r
1869 #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC
\r
1870 #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT
\r
1871 #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN
\r
1872 #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN
\r
1873 #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM
\r
1878 word CA :1; /* Analog Input Channel Select Code A */
\r
1879 word CB :1; /* Analog Input Channel Select Code B */
\r
1880 word CC :1; /* Analog Input Channel Select Code C */
\r
1882 word MULT :1; /* Multi-Channel Sample Mode */
\r
1883 word SCAN :1; /* Continuous Conversion Sequence Mode */
\r
1884 word DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
1885 word DJM :1; /* Result Register Data Justification Mode */
\r
1886 word PRS0 :1; /* ATD 0 Clock Prescaler 0 */
\r
1887 word PRS1 :1; /* ATD 0 Clock Prescaler 1 */
\r
1888 word PRS2 :1; /* ATD 0 Clock Prescaler 2 */
\r
1889 word PRS3 :1; /* ATD 0 Clock Prescaler 3 */
\r
1890 word PRS4 :1; /* ATD 0 Clock Prescaler 4 */
\r
1891 word SMP0 :1; /* Sample Time Select 0 */
\r
1892 word SMP1 :1; /* Sample Time Select 1 */
\r
1893 word SRES8 :1; /* ATD 0 Resolution Select */
\r
1906 word grpSRES_8 :1;
\r
1909 extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084);
\r
1910 #define ATD0CTL45 _ATD0CTL45.Word
\r
1911 #define ATD0CTL45_CA _ATD0CTL45.Bits.CA
\r
1912 #define ATD0CTL45_CB _ATD0CTL45.Bits.CB
\r
1913 #define ATD0CTL45_CC _ATD0CTL45.Bits.CC
\r
1914 #define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT
\r
1915 #define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN
\r
1916 #define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN
\r
1917 #define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM
\r
1918 #define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0
\r
1919 #define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1
\r
1920 #define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2
\r
1921 #define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3
\r
1922 #define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4
\r
1923 #define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0
\r
1924 #define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1
\r
1925 #define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8
\r
1926 #define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS
\r
1927 #define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP
\r
1930 /*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/
\r
1933 /* Overlapped registers: */
\r
1935 /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/
\r
1939 byte BIT8 :1; /* Bit 8 */
\r
1940 byte BIT9 :1; /* Bit 9 */
\r
1941 byte BIT10 :1; /* Bit 10 */
\r
1942 byte BIT11 :1; /* Bit 11 */
\r
1943 byte BIT12 :1; /* Bit 12 */
\r
1944 byte BIT13 :1; /* Bit 13 */
\r
1945 byte BIT14 :1; /* Bit 14 */
\r
1946 byte BIT15 :1; /* Bit 15 */
\r
1952 #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte
\r
1953 #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8
\r
1954 #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9
\r
1955 #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10
\r
1956 #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11
\r
1957 #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12
\r
1958 #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13
\r
1959 #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14
\r
1960 #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15
\r
1961 #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8
\r
1962 #define ATD0DR0H_BIT ATD0DR0H_BIT_8
\r
1964 /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/
\r
1974 byte BIT6 :1; /* Bit 6 */
\r
1975 byte BIT7 :1; /* Bit 7 */
\r
1987 #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte
\r
1988 #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6
\r
1989 #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7
\r
1990 #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6
\r
1991 #define ATD0DR0L_BIT ATD0DR0L_BIT_6
\r
2002 word BIT6 :1; /* Bit 6 */
\r
2003 word BIT7 :1; /* Bit 7 */
\r
2004 word BIT8 :1; /* Bit 8 */
\r
2005 word BIT9 :1; /* Bit 9 */
\r
2006 word BIT10 :1; /* Bit 10 */
\r
2007 word BIT11 :1; /* Bit 11 */
\r
2008 word BIT12 :1; /* Bit 12 */
\r
2009 word BIT13 :1; /* Bit 13 */
\r
2010 word BIT14 :1; /* Bit 14 */
\r
2011 word BIT15 :1; /* Bit 15 */
\r
2020 word grpBIT_6 :10;
\r
2023 extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090);
\r
2024 #define ATD0DR0 _ATD0DR0.Word
\r
2025 #define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6
\r
2026 #define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7
\r
2027 #define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8
\r
2028 #define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9
\r
2029 #define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10
\r
2030 #define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11
\r
2031 #define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12
\r
2032 #define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13
\r
2033 #define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14
\r
2034 #define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15
\r
2035 #define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6
\r
2036 #define ATD0DR0_BIT ATD0DR0_BIT_6
\r
2039 /*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/
\r
2042 /* Overlapped registers: */
\r
2044 /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/
\r
2048 byte BIT8 :1; /* Bit 8 */
\r
2049 byte BIT9 :1; /* Bit 9 */
\r
2050 byte BIT10 :1; /* Bit 10 */
\r
2051 byte BIT11 :1; /* Bit 11 */
\r
2052 byte BIT12 :1; /* Bit 12 */
\r
2053 byte BIT13 :1; /* Bit 13 */
\r
2054 byte BIT14 :1; /* Bit 14 */
\r
2055 byte BIT15 :1; /* Bit 15 */
\r
2061 #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte
\r
2062 #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8
\r
2063 #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9
\r
2064 #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10
\r
2065 #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11
\r
2066 #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12
\r
2067 #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13
\r
2068 #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14
\r
2069 #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15
\r
2070 #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8
\r
2071 #define ATD0DR1H_BIT ATD0DR1H_BIT_8
\r
2073 /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/
\r
2083 byte BIT6 :1; /* Bit 6 */
\r
2084 byte BIT7 :1; /* Bit 7 */
\r
2096 #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte
\r
2097 #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6
\r
2098 #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7
\r
2099 #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6
\r
2100 #define ATD0DR1L_BIT ATD0DR1L_BIT_6
\r
2111 word BIT6 :1; /* Bit 6 */
\r
2112 word BIT7 :1; /* Bit 7 */
\r
2113 word BIT8 :1; /* Bit 8 */
\r
2114 word BIT9 :1; /* Bit 9 */
\r
2115 word BIT10 :1; /* Bit 10 */
\r
2116 word BIT11 :1; /* Bit 11 */
\r
2117 word BIT12 :1; /* Bit 12 */
\r
2118 word BIT13 :1; /* Bit 13 */
\r
2119 word BIT14 :1; /* Bit 14 */
\r
2120 word BIT15 :1; /* Bit 15 */
\r
2129 word grpBIT_6 :10;
\r
2132 extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092);
\r
2133 #define ATD0DR1 _ATD0DR1.Word
\r
2134 #define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6
\r
2135 #define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7
\r
2136 #define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8
\r
2137 #define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9
\r
2138 #define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10
\r
2139 #define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11
\r
2140 #define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12
\r
2141 #define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13
\r
2142 #define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14
\r
2143 #define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15
\r
2144 #define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6
\r
2145 #define ATD0DR1_BIT ATD0DR1_BIT_6
\r
2148 /*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/
\r
2151 /* Overlapped registers: */
\r
2153 /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/
\r
2157 byte BIT8 :1; /* Bit 8 */
\r
2158 byte BIT9 :1; /* Bit 9 */
\r
2159 byte BIT10 :1; /* Bit 10 */
\r
2160 byte BIT11 :1; /* Bit 11 */
\r
2161 byte BIT12 :1; /* Bit 12 */
\r
2162 byte BIT13 :1; /* Bit 13 */
\r
2163 byte BIT14 :1; /* Bit 14 */
\r
2164 byte BIT15 :1; /* Bit 15 */
\r
2170 #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte
\r
2171 #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8
\r
2172 #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9
\r
2173 #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10
\r
2174 #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11
\r
2175 #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12
\r
2176 #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13
\r
2177 #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14
\r
2178 #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15
\r
2179 #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8
\r
2180 #define ATD0DR2H_BIT ATD0DR2H_BIT_8
\r
2182 /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/
\r
2192 byte BIT6 :1; /* Bit 6 */
\r
2193 byte BIT7 :1; /* Bit 7 */
\r
2205 #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte
\r
2206 #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6
\r
2207 #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7
\r
2208 #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6
\r
2209 #define ATD0DR2L_BIT ATD0DR2L_BIT_6
\r
2220 word BIT6 :1; /* Bit 6 */
\r
2221 word BIT7 :1; /* Bit 7 */
\r
2222 word BIT8 :1; /* Bit 8 */
\r
2223 word BIT9 :1; /* Bit 9 */
\r
2224 word BIT10 :1; /* Bit 10 */
\r
2225 word BIT11 :1; /* Bit 11 */
\r
2226 word BIT12 :1; /* Bit 12 */
\r
2227 word BIT13 :1; /* Bit 13 */
\r
2228 word BIT14 :1; /* Bit 14 */
\r
2229 word BIT15 :1; /* Bit 15 */
\r
2238 word grpBIT_6 :10;
\r
2241 extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094);
\r
2242 #define ATD0DR2 _ATD0DR2.Word
\r
2243 #define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6
\r
2244 #define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7
\r
2245 #define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8
\r
2246 #define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9
\r
2247 #define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10
\r
2248 #define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11
\r
2249 #define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12
\r
2250 #define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13
\r
2251 #define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14
\r
2252 #define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15
\r
2253 #define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6
\r
2254 #define ATD0DR2_BIT ATD0DR2_BIT_6
\r
2257 /*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/
\r
2260 /* Overlapped registers: */
\r
2262 /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/
\r
2266 byte BIT8 :1; /* Bit 8 */
\r
2267 byte BIT9 :1; /* Bit 9 */
\r
2268 byte BIT10 :1; /* Bit 10 */
\r
2269 byte BIT11 :1; /* Bit 11 */
\r
2270 byte BIT12 :1; /* Bit 12 */
\r
2271 byte BIT13 :1; /* Bit 13 */
\r
2272 byte BIT14 :1; /* Bit 14 */
\r
2273 byte BIT15 :1; /* Bit 15 */
\r
2279 #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte
\r
2280 #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8
\r
2281 #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9
\r
2282 #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10
\r
2283 #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11
\r
2284 #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12
\r
2285 #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13
\r
2286 #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14
\r
2287 #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15
\r
2288 #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8
\r
2289 #define ATD0DR3H_BIT ATD0DR3H_BIT_8
\r
2291 /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/
\r
2301 byte BIT6 :1; /* Bit 6 */
\r
2302 byte BIT7 :1; /* Bit 7 */
\r
2314 #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte
\r
2315 #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6
\r
2316 #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7
\r
2317 #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6
\r
2318 #define ATD0DR3L_BIT ATD0DR3L_BIT_6
\r
2329 word BIT6 :1; /* Bit 6 */
\r
2330 word BIT7 :1; /* Bit 7 */
\r
2331 word BIT8 :1; /* Bit 8 */
\r
2332 word BIT9 :1; /* Bit 9 */
\r
2333 word BIT10 :1; /* Bit 10 */
\r
2334 word BIT11 :1; /* Bit 11 */
\r
2335 word BIT12 :1; /* Bit 12 */
\r
2336 word BIT13 :1; /* Bit 13 */
\r
2337 word BIT14 :1; /* Bit 14 */
\r
2338 word BIT15 :1; /* Bit 15 */
\r
2347 word grpBIT_6 :10;
\r
2350 extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096);
\r
2351 #define ATD0DR3 _ATD0DR3.Word
\r
2352 #define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6
\r
2353 #define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7
\r
2354 #define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8
\r
2355 #define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9
\r
2356 #define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10
\r
2357 #define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11
\r
2358 #define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12
\r
2359 #define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13
\r
2360 #define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14
\r
2361 #define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15
\r
2362 #define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6
\r
2363 #define ATD0DR3_BIT ATD0DR3_BIT_6
\r
2366 /*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/
\r
2369 /* Overlapped registers: */
\r
2371 /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/
\r
2375 byte BIT8 :1; /* Bit 8 */
\r
2376 byte BIT9 :1; /* Bit 9 */
\r
2377 byte BIT10 :1; /* Bit 10 */
\r
2378 byte BIT11 :1; /* Bit 11 */
\r
2379 byte BIT12 :1; /* Bit 12 */
\r
2380 byte BIT13 :1; /* Bit 13 */
\r
2381 byte BIT14 :1; /* Bit 14 */
\r
2382 byte BIT15 :1; /* Bit 15 */
\r
2388 #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte
\r
2389 #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8
\r
2390 #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9
\r
2391 #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10
\r
2392 #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11
\r
2393 #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12
\r
2394 #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13
\r
2395 #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14
\r
2396 #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15
\r
2397 #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8
\r
2398 #define ATD0DR4H_BIT ATD0DR4H_BIT_8
\r
2400 /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/
\r
2410 byte BIT6 :1; /* Bit 6 */
\r
2411 byte BIT7 :1; /* Bit 7 */
\r
2423 #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte
\r
2424 #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6
\r
2425 #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7
\r
2426 #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6
\r
2427 #define ATD0DR4L_BIT ATD0DR4L_BIT_6
\r
2438 word BIT6 :1; /* Bit 6 */
\r
2439 word BIT7 :1; /* Bit 7 */
\r
2440 word BIT8 :1; /* Bit 8 */
\r
2441 word BIT9 :1; /* Bit 9 */
\r
2442 word BIT10 :1; /* Bit 10 */
\r
2443 word BIT11 :1; /* Bit 11 */
\r
2444 word BIT12 :1; /* Bit 12 */
\r
2445 word BIT13 :1; /* Bit 13 */
\r
2446 word BIT14 :1; /* Bit 14 */
\r
2447 word BIT15 :1; /* Bit 15 */
\r
2456 word grpBIT_6 :10;
\r
2459 extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098);
\r
2460 #define ATD0DR4 _ATD0DR4.Word
\r
2461 #define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6
\r
2462 #define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7
\r
2463 #define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8
\r
2464 #define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9
\r
2465 #define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10
\r
2466 #define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11
\r
2467 #define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12
\r
2468 #define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13
\r
2469 #define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14
\r
2470 #define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15
\r
2471 #define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6
\r
2472 #define ATD0DR4_BIT ATD0DR4_BIT_6
\r
2475 /*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/
\r
2478 /* Overlapped registers: */
\r
2480 /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/
\r
2484 byte BIT8 :1; /* Bit 8 */
\r
2485 byte BIT9 :1; /* Bit 9 */
\r
2486 byte BIT10 :1; /* Bit 10 */
\r
2487 byte BIT11 :1; /* Bit 11 */
\r
2488 byte BIT12 :1; /* Bit 12 */
\r
2489 byte BIT13 :1; /* Bit 13 */
\r
2490 byte BIT14 :1; /* Bit 14 */
\r
2491 byte BIT15 :1; /* Bit 15 */
\r
2497 #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte
\r
2498 #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8
\r
2499 #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9
\r
2500 #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10
\r
2501 #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11
\r
2502 #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12
\r
2503 #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13
\r
2504 #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14
\r
2505 #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15
\r
2506 #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8
\r
2507 #define ATD0DR5H_BIT ATD0DR5H_BIT_8
\r
2509 /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/
\r
2519 byte BIT6 :1; /* Bit 6 */
\r
2520 byte BIT7 :1; /* Bit 7 */
\r
2532 #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte
\r
2533 #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6
\r
2534 #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7
\r
2535 #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6
\r
2536 #define ATD0DR5L_BIT ATD0DR5L_BIT_6
\r
2547 word BIT6 :1; /* Bit 6 */
\r
2548 word BIT7 :1; /* Bit 7 */
\r
2549 word BIT8 :1; /* Bit 8 */
\r
2550 word BIT9 :1; /* Bit 9 */
\r
2551 word BIT10 :1; /* Bit 10 */
\r
2552 word BIT11 :1; /* Bit 11 */
\r
2553 word BIT12 :1; /* Bit 12 */
\r
2554 word BIT13 :1; /* Bit 13 */
\r
2555 word BIT14 :1; /* Bit 14 */
\r
2556 word BIT15 :1; /* Bit 15 */
\r
2565 word grpBIT_6 :10;
\r
2568 extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A);
\r
2569 #define ATD0DR5 _ATD0DR5.Word
\r
2570 #define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6
\r
2571 #define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7
\r
2572 #define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8
\r
2573 #define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9
\r
2574 #define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10
\r
2575 #define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11
\r
2576 #define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12
\r
2577 #define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13
\r
2578 #define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14
\r
2579 #define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15
\r
2580 #define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6
\r
2581 #define ATD0DR5_BIT ATD0DR5_BIT_6
\r
2584 /*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/
\r
2587 /* Overlapped registers: */
\r
2589 /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/
\r
2593 byte BIT8 :1; /* Bit 8 */
\r
2594 byte BIT9 :1; /* Bit 9 */
\r
2595 byte BIT10 :1; /* Bit 10 */
\r
2596 byte BIT11 :1; /* Bit 11 */
\r
2597 byte BIT12 :1; /* Bit 12 */
\r
2598 byte BIT13 :1; /* Bit 13 */
\r
2599 byte BIT14 :1; /* Bit 14 */
\r
2600 byte BIT15 :1; /* Bit 15 */
\r
2606 #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte
\r
2607 #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8
\r
2608 #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9
\r
2609 #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10
\r
2610 #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11
\r
2611 #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12
\r
2612 #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13
\r
2613 #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14
\r
2614 #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15
\r
2615 #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8
\r
2616 #define ATD0DR6H_BIT ATD0DR6H_BIT_8
\r
2618 /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/
\r
2628 byte BIT6 :1; /* Bit 6 */
\r
2629 byte BIT7 :1; /* Bit 7 */
\r
2641 #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte
\r
2642 #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6
\r
2643 #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7
\r
2644 #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6
\r
2645 #define ATD0DR6L_BIT ATD0DR6L_BIT_6
\r
2656 word BIT6 :1; /* Bit 6 */
\r
2657 word BIT7 :1; /* Bit 7 */
\r
2658 word BIT8 :1; /* Bit 8 */
\r
2659 word BIT9 :1; /* Bit 9 */
\r
2660 word BIT10 :1; /* Bit 10 */
\r
2661 word BIT11 :1; /* Bit 11 */
\r
2662 word BIT12 :1; /* Bit 12 */
\r
2663 word BIT13 :1; /* Bit 13 */
\r
2664 word BIT14 :1; /* Bit 14 */
\r
2665 word BIT15 :1; /* Bit 15 */
\r
2674 word grpBIT_6 :10;
\r
2677 extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C);
\r
2678 #define ATD0DR6 _ATD0DR6.Word
\r
2679 #define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6
\r
2680 #define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7
\r
2681 #define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8
\r
2682 #define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9
\r
2683 #define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10
\r
2684 #define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11
\r
2685 #define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12
\r
2686 #define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13
\r
2687 #define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14
\r
2688 #define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15
\r
2689 #define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6
\r
2690 #define ATD0DR6_BIT ATD0DR6_BIT_6
\r
2693 /*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/
\r
2696 /* Overlapped registers: */
\r
2698 /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/
\r
2702 byte BIT8 :1; /* Bit 8 */
\r
2703 byte BIT9 :1; /* Bit 9 */
\r
2704 byte BIT10 :1; /* Bit 10 */
\r
2705 byte BIT11 :1; /* Bit 11 */
\r
2706 byte BIT12 :1; /* Bit 12 */
\r
2707 byte BIT13 :1; /* Bit 13 */
\r
2708 byte BIT14 :1; /* Bit 14 */
\r
2709 byte BIT15 :1; /* Bit 15 */
\r
2715 #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte
\r
2716 #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8
\r
2717 #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9
\r
2718 #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10
\r
2719 #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11
\r
2720 #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12
\r
2721 #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13
\r
2722 #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14
\r
2723 #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15
\r
2724 #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8
\r
2725 #define ATD0DR7H_BIT ATD0DR7H_BIT_8
\r
2727 /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/
\r
2737 byte BIT6 :1; /* Bit 6 */
\r
2738 byte BIT7 :1; /* Bit 7 */
\r
2750 #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte
\r
2751 #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6
\r
2752 #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7
\r
2753 #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6
\r
2754 #define ATD0DR7L_BIT ATD0DR7L_BIT_6
\r
2765 word BIT6 :1; /* Bit 6 */
\r
2766 word BIT7 :1; /* Bit 7 */
\r
2767 word BIT8 :1; /* Bit 8 */
\r
2768 word BIT9 :1; /* Bit 9 */
\r
2769 word BIT10 :1; /* Bit 10 */
\r
2770 word BIT11 :1; /* Bit 11 */
\r
2771 word BIT12 :1; /* Bit 12 */
\r
2772 word BIT13 :1; /* Bit 13 */
\r
2773 word BIT14 :1; /* Bit 14 */
\r
2774 word BIT15 :1; /* Bit 15 */
\r
2783 word grpBIT_6 :10;
\r
2786 extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E);
\r
2787 #define ATD0DR7 _ATD0DR7.Word
\r
2788 #define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6
\r
2789 #define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7
\r
2790 #define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8
\r
2791 #define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9
\r
2792 #define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10
\r
2793 #define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11
\r
2794 #define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12
\r
2795 #define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13
\r
2796 #define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14
\r
2797 #define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15
\r
2798 #define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6
\r
2799 #define ATD0DR7_BIT ATD0DR7_BIT_6
\r
2802 /*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/
\r
2805 /* Overlapped registers: */
\r
2807 /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/
\r
2814 #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte
\r
2815 #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT
\r
2817 /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/
\r
2824 #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte
\r
2825 #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT
\r
2833 extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC);
\r
2834 #define PWMCNT01 _PWMCNT01.Word
\r
2835 #define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT
\r
2838 /*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/
\r
2841 /* Overlapped registers: */
\r
2843 /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/
\r
2850 #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte
\r
2851 #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT
\r
2853 /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/
\r
2860 #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte
\r
2861 #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT
\r
2869 extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE);
\r
2870 #define PWMCNT23 _PWMCNT23.Word
\r
2871 #define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT
\r
2874 /*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/
\r
2877 /* Overlapped registers: */
\r
2879 /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/
\r
2886 #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte
\r
2887 #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT
\r
2889 /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/
\r
2896 #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte
\r
2897 #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT
\r
2905 extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0);
\r
2906 #define PWMCNT45 _PWMCNT45.Word
\r
2907 #define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT
\r
2910 /*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/
\r
2913 /* Overlapped registers: */
\r
2915 /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/
\r
2922 #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte
\r
2923 #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT
\r
2925 /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/
\r
2932 #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte
\r
2933 #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT
\r
2941 extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2);
\r
2942 #define PWMCNT67 _PWMCNT67.Word
\r
2943 #define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT
\r
2946 /*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/
\r
2949 /* Overlapped registers: */
\r
2951 /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/
\r
2958 #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte
\r
2959 #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT
\r
2961 /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/
\r
2968 #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte
\r
2969 #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT
\r
2977 extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4);
\r
2978 #define PWMPER01 _PWMPER01.Word
\r
2979 #define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT
\r
2982 /*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/
\r
2985 /* Overlapped registers: */
\r
2987 /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/
\r
2994 #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte
\r
2995 #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT
\r
2997 /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/
\r
3004 #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte
\r
3005 #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT
\r
3013 extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6);
\r
3014 #define PWMPER23 _PWMPER23.Word
\r
3015 #define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT
\r
3018 /*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/
\r
3021 /* Overlapped registers: */
\r
3023 /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/
\r
3030 #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte
\r
3031 #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT
\r
3033 /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/
\r
3040 #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte
\r
3041 #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT
\r
3049 extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8);
\r
3050 #define PWMPER45 _PWMPER45.Word
\r
3051 #define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT
\r
3054 /*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/
\r
3057 /* Overlapped registers: */
\r
3059 /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/
\r
3066 #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte
\r
3067 #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT
\r
3069 /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/
\r
3076 #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte
\r
3077 #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT
\r
3085 extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA);
\r
3086 #define PWMPER67 _PWMPER67.Word
\r
3087 #define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT
\r
3090 /*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/
\r
3093 /* Overlapped registers: */
\r
3095 /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/
\r
3102 #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte
\r
3103 #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT
\r
3105 /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/
\r
3112 #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte
\r
3113 #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT
\r
3121 extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC);
\r
3122 #define PWMDTY01 _PWMDTY01.Word
\r
3123 #define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT
\r
3126 /*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/
\r
3129 /* Overlapped registers: */
\r
3131 /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/
\r
3138 #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte
\r
3139 #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT
\r
3141 /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/
\r
3148 #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte
\r
3149 #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT
\r
3157 extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE);
\r
3158 #define PWMDTY23 _PWMDTY23.Word
\r
3159 #define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT
\r
3162 /*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/
\r
3165 /* Overlapped registers: */
\r
3167 /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/
\r
3174 #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte
\r
3175 #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT
\r
3177 /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/
\r
3184 #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte
\r
3185 #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT
\r
3193 extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0);
\r
3194 #define PWMDTY45 _PWMDTY45.Word
\r
3195 #define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT
\r
3198 /*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/
\r
3201 /* Overlapped registers: */
\r
3203 /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/
\r
3210 #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte
\r
3211 #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT
\r
3213 /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/
\r
3220 #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte
\r
3221 #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT
\r
3229 extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2);
\r
3230 #define PWMDTY67 _PWMDTY67.Word
\r
3231 #define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT
\r
3234 /*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/
\r
3237 /* Overlapped registers: */
\r
3239 /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/
\r
3243 byte SBR8 :1; /* SCI 0 baud rate Bit 8 */
\r
3244 byte SBR9 :1; /* SCI 0 baud rate Bit 9 */
\r
3245 byte SBR10 :1; /* SCI 0 baud rate Bit 10 */
\r
3246 byte SBR11 :1; /* SCI 0 baud rate Bit 11 */
\r
3247 byte SBR12 :1; /* SCI 0 baud rate Bit 12 */
\r
3259 #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte
\r
3260 #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8
\r
3261 #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9
\r
3262 #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10
\r
3263 #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11
\r
3264 #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12
\r
3265 #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8
\r
3266 #define SCI0BDH_SBR SCI0BDH_SBR_8
\r
3268 /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/
\r
3272 byte SBR0 :1; /* SCI 0 baud rate Bit 0 */
\r
3273 byte SBR1 :1; /* SCI 0 baud rate Bit 1 */
\r
3274 byte SBR2 :1; /* SCI 0 baud rate Bit 2 */
\r
3275 byte SBR3 :1; /* SCI 0 baud rate Bit 3 */
\r
3276 byte SBR4 :1; /* SCI 0 baud rate Bit 4 */
\r
3277 byte SBR5 :1; /* SCI 0 baud rate Bit 5 */
\r
3278 byte SBR6 :1; /* SCI 0 baud rate Bit 6 */
\r
3279 byte SBR7 :1; /* SCI 0 baud rate Bit 7 */
\r
3285 #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte
\r
3286 #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0
\r
3287 #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1
\r
3288 #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2
\r
3289 #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3
\r
3290 #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4
\r
3291 #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5
\r
3292 #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6
\r
3293 #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7
\r
3294 #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR
\r
3299 word SBR0 :1; /* SCI 0 baud rate Bit 0 */
\r
3300 word SBR1 :1; /* SCI 0 baud rate Bit 1 */
\r
3301 word SBR2 :1; /* SCI 0 baud rate Bit 2 */
\r
3302 word SBR3 :1; /* SCI 0 baud rate Bit 3 */
\r
3303 word SBR4 :1; /* SCI 0 baud rate Bit 4 */
\r
3304 word SBR5 :1; /* SCI 0 baud rate Bit 5 */
\r
3305 word SBR6 :1; /* SCI 0 baud rate Bit 6 */
\r
3306 word SBR7 :1; /* SCI 0 baud rate Bit 7 */
\r
3307 word SBR8 :1; /* SCI 0 baud rate Bit 8 */
\r
3308 word SBR9 :1; /* SCI 0 baud rate Bit 9 */
\r
3309 word SBR10 :1; /* SCI 0 baud rate Bit 10 */
\r
3310 word SBR11 :1; /* SCI 0 baud rate Bit 11 */
\r
3311 word SBR12 :1; /* SCI 0 baud rate Bit 12 */
\r
3323 extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);
\r
3324 #define SCI0BD _SCI0BD.Word
\r
3325 #define SCI0BD_SBR0 _SCI0BD.Bits.SBR0
\r
3326 #define SCI0BD_SBR1 _SCI0BD.Bits.SBR1
\r
3327 #define SCI0BD_SBR2 _SCI0BD.Bits.SBR2
\r
3328 #define SCI0BD_SBR3 _SCI0BD.Bits.SBR3
\r
3329 #define SCI0BD_SBR4 _SCI0BD.Bits.SBR4
\r
3330 #define SCI0BD_SBR5 _SCI0BD.Bits.SBR5
\r
3331 #define SCI0BD_SBR6 _SCI0BD.Bits.SBR6
\r
3332 #define SCI0BD_SBR7 _SCI0BD.Bits.SBR7
\r
3333 #define SCI0BD_SBR8 _SCI0BD.Bits.SBR8
\r
3334 #define SCI0BD_SBR9 _SCI0BD.Bits.SBR9
\r
3335 #define SCI0BD_SBR10 _SCI0BD.Bits.SBR10
\r
3336 #define SCI0BD_SBR11 _SCI0BD.Bits.SBR11
\r
3337 #define SCI0BD_SBR12 _SCI0BD.Bits.SBR12
\r
3338 #define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR
\r
3341 /*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/
\r
3344 /* Overlapped registers: */
\r
3346 /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/
\r
3350 byte SBR8 :1; /* SCI 1 baud rate Bit 8 */
\r
3351 byte SBR9 :1; /* SCI 1 baud rate Bit 9 */
\r
3352 byte SBR10 :1; /* SCI 1 baud rate Bit 10 */
\r
3353 byte SBR11 :1; /* SCI 1 baud rate Bit 11 */
\r
3354 byte SBR12 :1; /* SCI 1 baud rate Bit 12 */
\r
3366 #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte
\r
3367 #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8
\r
3368 #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9
\r
3369 #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10
\r
3370 #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11
\r
3371 #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12
\r
3372 #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8
\r
3373 #define SCI1BDH_SBR SCI1BDH_SBR_8
\r
3375 /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/
\r
3379 byte SBR0 :1; /* SCI 1 baud rate Bit 0 */
\r
3380 byte SBR1 :1; /* SCI 1 baud rate Bit 1 */
\r
3381 byte SBR2 :1; /* SCI 1 baud rate Bit 2 */
\r
3382 byte SBR3 :1; /* SCI 1 baud rate Bit 3 */
\r
3383 byte SBR4 :1; /* SCI 1 baud rate Bit 4 */
\r
3384 byte SBR5 :1; /* SCI 1 baud rate Bit 5 */
\r
3385 byte SBR6 :1; /* SCI 1 baud rate Bit 6 */
\r
3386 byte SBR7 :1; /* SCI 1 baud rate Bit 7 */
\r
3392 #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte
\r
3393 #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0
\r
3394 #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1
\r
3395 #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2
\r
3396 #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3
\r
3397 #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4
\r
3398 #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5
\r
3399 #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6
\r
3400 #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7
\r
3401 #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR
\r
3406 word SBR0 :1; /* SCI 1 baud rate Bit 0 */
\r
3407 word SBR1 :1; /* SCI 1 baud rate Bit 1 */
\r
3408 word SBR2 :1; /* SCI 1 baud rate Bit 2 */
\r
3409 word SBR3 :1; /* SCI 1 baud rate Bit 3 */
\r
3410 word SBR4 :1; /* SCI 1 baud rate Bit 4 */
\r
3411 word SBR5 :1; /* SCI 1 baud rate Bit 5 */
\r
3412 word SBR6 :1; /* SCI 1 baud rate Bit 6 */
\r
3413 word SBR7 :1; /* SCI 1 baud rate Bit 7 */
\r
3414 word SBR8 :1; /* SCI 1 baud rate Bit 8 */
\r
3415 word SBR9 :1; /* SCI 1 baud rate Bit 9 */
\r
3416 word SBR10 :1; /* SCI 1 baud rate Bit 10 */
\r
3417 word SBR11 :1; /* SCI 1 baud rate Bit 11 */
\r
3418 word SBR12 :1; /* SCI 1 baud rate Bit 12 */
\r
3430 extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);
\r
3431 #define SCI1BD _SCI1BD.Word
\r
3432 #define SCI1BD_SBR0 _SCI1BD.Bits.SBR0
\r
3433 #define SCI1BD_SBR1 _SCI1BD.Bits.SBR1
\r
3434 #define SCI1BD_SBR2 _SCI1BD.Bits.SBR2
\r
3435 #define SCI1BD_SBR3 _SCI1BD.Bits.SBR3
\r
3436 #define SCI1BD_SBR4 _SCI1BD.Bits.SBR4
\r
3437 #define SCI1BD_SBR5 _SCI1BD.Bits.SBR5
\r
3438 #define SCI1BD_SBR6 _SCI1BD.Bits.SBR6
\r
3439 #define SCI1BD_SBR7 _SCI1BD.Bits.SBR7
\r
3440 #define SCI1BD_SBR8 _SCI1BD.Bits.SBR8
\r
3441 #define SCI1BD_SBR9 _SCI1BD.Bits.SBR9
\r
3442 #define SCI1BD_SBR10 _SCI1BD.Bits.SBR10
\r
3443 #define SCI1BD_SBR11 _SCI1BD.Bits.SBR11
\r
3444 #define SCI1BD_SBR12 _SCI1BD.Bits.SBR12
\r
3445 #define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR
\r
3448 /*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/
\r
3451 /* Overlapped registers: */
\r
3453 /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/
\r
3457 byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */
\r
3458 byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */
\r
3459 byte ETRIGE :1; /* External Trigger Mode enable */
\r
3460 byte ETRIGP :1; /* External Trigger Polarity */
\r
3461 byte ETRIGLE :1; /* External Trigger Level/Edge control */
\r
3462 byte AWAI :1; /* ATD 1 Wait Mode */
\r
3463 byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */
\r
3464 byte ADPU :1; /* ATD 1 Disable / Power Down */
\r
3467 #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte
\r
3468 #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF
\r
3469 #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE
\r
3470 #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE
\r
3471 #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP
\r
3472 #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE
\r
3473 #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI
\r
3474 #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC
\r
3475 #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU
\r
3477 /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/
\r
3481 byte FRZ0 :1; /* Background Debug Freeze Enable */
\r
3482 byte FRZ1 :1; /* Background Debug Freeze Enable */
\r
3483 byte FIFO :1; /* Result Register FIFO Mode */
\r
3484 byte S1C :1; /* Conversion Sequence Length 1 */
\r
3485 byte S2C :1; /* Conversion Sequence Length 2 */
\r
3486 byte S4C :1; /* Conversion Sequence Length 4 */
\r
3487 byte S8C :1; /* Conversion Sequence Length 8 */
\r
3500 #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte
\r
3501 #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0
\r
3502 #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1
\r
3503 #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO
\r
3504 #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C
\r
3505 #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C
\r
3506 #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C
\r
3507 #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C
\r
3508 #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ
\r
3513 word FRZ0 :1; /* Background Debug Freeze Enable */
\r
3514 word FRZ1 :1; /* Background Debug Freeze Enable */
\r
3515 word FIFO :1; /* Result Register FIFO Mode */
\r
3516 word S1C :1; /* Conversion Sequence Length 1 */
\r
3517 word S2C :1; /* Conversion Sequence Length 2 */
\r
3518 word S4C :1; /* Conversion Sequence Length 4 */
\r
3519 word S8C :1; /* Conversion Sequence Length 8 */
\r
3521 word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */
\r
3522 word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */
\r
3523 word ETRIGE :1; /* External Trigger Mode enable */
\r
3524 word ETRIGP :1; /* External Trigger Polarity */
\r
3525 word ETRIGLE :1; /* External Trigger Level/Edge control */
\r
3526 word AWAI :1; /* ATD 1 Wait Mode */
\r
3527 word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */
\r
3528 word ADPU :1; /* ATD 1 Disable / Power Down */
\r
3548 extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122);
\r
3549 #define ATD1CTL23 _ATD1CTL23.Word
\r
3550 #define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0
\r
3551 #define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1
\r
3552 #define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO
\r
3553 #define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C
\r
3554 #define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C
\r
3555 #define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C
\r
3556 #define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C
\r
3557 #define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF
\r
3558 #define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE
\r
3559 #define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE
\r
3560 #define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP
\r
3561 #define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE
\r
3562 #define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI
\r
3563 #define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC
\r
3564 #define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU
\r
3565 #define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ
\r
3568 /*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/
\r
3571 /* Overlapped registers: */
\r
3573 /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/
\r
3577 byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */
\r
3578 byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */
\r
3579 byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */
\r
3580 byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */
\r
3581 byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */
\r
3582 byte SMP0 :1; /* Sample Time Select 0 */
\r
3583 byte SMP1 :1; /* Sample Time Select 1 */
\r
3584 byte SRES8 :1; /* ATD 1 Resolution Select */
\r
3589 byte grpSRES_8 :1;
\r
3592 #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte
\r
3593 #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0
\r
3594 #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1
\r
3595 #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2
\r
3596 #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3
\r
3597 #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4
\r
3598 #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0
\r
3599 #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1
\r
3600 #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8
\r
3601 #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS
\r
3602 #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP
\r
3604 /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/
\r
3608 byte CA :1; /* Analog Input Channel Select Code A */
\r
3609 byte CB :1; /* Analog Input Channel Select Code B */
\r
3610 byte CC :1; /* Analog Input Channel Select Code C */
\r
3612 byte MULT :1; /* Multi-Channel Sample Mode */
\r
3613 byte SCAN :1; /* Continuous Conversion Sequence Mode */
\r
3614 byte DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
3615 byte DJM :1; /* Result Register Data Justification Mode */
\r
3618 #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte
\r
3619 #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA
\r
3620 #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB
\r
3621 #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC
\r
3622 #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT
\r
3623 #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN
\r
3624 #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN
\r
3625 #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM
\r
3630 word CA :1; /* Analog Input Channel Select Code A */
\r
3631 word CB :1; /* Analog Input Channel Select Code B */
\r
3632 word CC :1; /* Analog Input Channel Select Code C */
\r
3634 word MULT :1; /* Multi-Channel Sample Mode */
\r
3635 word SCAN :1; /* Continuous Conversion Sequence Mode */
\r
3636 word DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
3637 word DJM :1; /* Result Register Data Justification Mode */
\r
3638 word PRS0 :1; /* ATD 1 Clock Prescaler 0 */
\r
3639 word PRS1 :1; /* ATD 1 Clock Prescaler 1 */
\r
3640 word PRS2 :1; /* ATD 1 Clock Prescaler 2 */
\r
3641 word PRS3 :1; /* ATD 1 Clock Prescaler 3 */
\r
3642 word PRS4 :1; /* ATD 1 Clock Prescaler 4 */
\r
3643 word SMP0 :1; /* Sample Time Select 0 */
\r
3644 word SMP1 :1; /* Sample Time Select 1 */
\r
3645 word SRES8 :1; /* ATD 1 Resolution Select */
\r
3658 word grpSRES_8 :1;
\r
3661 extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124);
\r
3662 #define ATD1CTL45 _ATD1CTL45.Word
\r
3663 #define ATD1CTL45_CA _ATD1CTL45.Bits.CA
\r
3664 #define ATD1CTL45_CB _ATD1CTL45.Bits.CB
\r
3665 #define ATD1CTL45_CC _ATD1CTL45.Bits.CC
\r
3666 #define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT
\r
3667 #define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN
\r
3668 #define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN
\r
3669 #define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM
\r
3670 #define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0
\r
3671 #define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1
\r
3672 #define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2
\r
3673 #define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3
\r
3674 #define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4
\r
3675 #define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0
\r
3676 #define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1
\r
3677 #define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8
\r
3678 #define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS
\r
3679 #define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP
\r
3682 /*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/
\r
3685 /* Overlapped registers: */
\r
3687 /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/
\r
3691 byte BIT8 :1; /* Bit 8 */
\r
3692 byte BIT9 :1; /* Bit 9 */
\r
3693 byte BIT10 :1; /* Bit 10 */
\r
3694 byte BIT11 :1; /* Bit 11 */
\r
3695 byte BIT12 :1; /* Bit 12 */
\r
3696 byte BIT13 :1; /* Bit 13 */
\r
3697 byte BIT14 :1; /* Bit 14 */
\r
3698 byte BIT15 :1; /* Bit 15 */
\r
3704 #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte
\r
3705 #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8
\r
3706 #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9
\r
3707 #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10
\r
3708 #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11
\r
3709 #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12
\r
3710 #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13
\r
3711 #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14
\r
3712 #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15
\r
3713 #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8
\r
3714 #define ATD1DR0H_BIT ATD1DR0H_BIT_8
\r
3716 /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/
\r
3726 byte BIT6 :1; /* Bit 6 */
\r
3727 byte BIT7 :1; /* Bit 7 */
\r
3739 #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte
\r
3740 #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6
\r
3741 #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7
\r
3742 #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6
\r
3743 #define ATD1DR0L_BIT ATD1DR0L_BIT_6
\r
3754 word BIT6 :1; /* Bit 6 */
\r
3755 word BIT7 :1; /* Bit 7 */
\r
3756 word BIT8 :1; /* Bit 8 */
\r
3757 word BIT9 :1; /* Bit 9 */
\r
3758 word BIT10 :1; /* Bit 10 */
\r
3759 word BIT11 :1; /* Bit 11 */
\r
3760 word BIT12 :1; /* Bit 12 */
\r
3761 word BIT13 :1; /* Bit 13 */
\r
3762 word BIT14 :1; /* Bit 14 */
\r
3763 word BIT15 :1; /* Bit 15 */
\r
3772 word grpBIT_6 :10;
\r
3775 extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130);
\r
3776 #define ATD1DR0 _ATD1DR0.Word
\r
3777 #define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6
\r
3778 #define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7
\r
3779 #define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8
\r
3780 #define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9
\r
3781 #define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10
\r
3782 #define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11
\r
3783 #define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12
\r
3784 #define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13
\r
3785 #define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14
\r
3786 #define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15
\r
3787 #define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6
\r
3788 #define ATD1DR0_BIT ATD1DR0_BIT_6
\r
3791 /*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/
\r
3794 /* Overlapped registers: */
\r
3796 /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/
\r
3800 byte BIT8 :1; /* Bit 8 */
\r
3801 byte BIT9 :1; /* Bit 9 */
\r
3802 byte BIT10 :1; /* Bit 10 */
\r
3803 byte BIT11 :1; /* Bit 11 */
\r
3804 byte BIT12 :1; /* Bit 12 */
\r
3805 byte BIT13 :1; /* Bit 13 */
\r
3806 byte BIT14 :1; /* Bit 14 */
\r
3807 byte BIT15 :1; /* Bit 15 */
\r
3813 #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte
\r
3814 #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8
\r
3815 #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9
\r
3816 #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10
\r
3817 #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11
\r
3818 #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12
\r
3819 #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13
\r
3820 #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14
\r
3821 #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15
\r
3822 #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8
\r
3823 #define ATD1DR1H_BIT ATD1DR1H_BIT_8
\r
3825 /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/
\r
3835 byte BIT6 :1; /* Bit 6 */
\r
3836 byte BIT7 :1; /* Bit 7 */
\r
3848 #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte
\r
3849 #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6
\r
3850 #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7
\r
3851 #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6
\r
3852 #define ATD1DR1L_BIT ATD1DR1L_BIT_6
\r
3863 word BIT6 :1; /* Bit 6 */
\r
3864 word BIT7 :1; /* Bit 7 */
\r
3865 word BIT8 :1; /* Bit 8 */
\r
3866 word BIT9 :1; /* Bit 9 */
\r
3867 word BIT10 :1; /* Bit 10 */
\r
3868 word BIT11 :1; /* Bit 11 */
\r
3869 word BIT12 :1; /* Bit 12 */
\r
3870 word BIT13 :1; /* Bit 13 */
\r
3871 word BIT14 :1; /* Bit 14 */
\r
3872 word BIT15 :1; /* Bit 15 */
\r
3881 word grpBIT_6 :10;
\r
3884 extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132);
\r
3885 #define ATD1DR1 _ATD1DR1.Word
\r
3886 #define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6
\r
3887 #define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7
\r
3888 #define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8
\r
3889 #define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9
\r
3890 #define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10
\r
3891 #define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11
\r
3892 #define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12
\r
3893 #define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13
\r
3894 #define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14
\r
3895 #define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15
\r
3896 #define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6
\r
3897 #define ATD1DR1_BIT ATD1DR1_BIT_6
\r
3900 /*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/
\r
3903 /* Overlapped registers: */
\r
3905 /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/
\r
3909 byte BIT8 :1; /* Bit 8 */
\r
3910 byte BIT9 :1; /* Bit 9 */
\r
3911 byte BIT10 :1; /* Bit 10 */
\r
3912 byte BIT11 :1; /* Bit 11 */
\r
3913 byte BIT12 :1; /* Bit 12 */
\r
3914 byte BIT13 :1; /* Bit 13 */
\r
3915 byte BIT14 :1; /* Bit 14 */
\r
3916 byte BIT15 :1; /* Bit 15 */
\r
3922 #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte
\r
3923 #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8
\r
3924 #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9
\r
3925 #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10
\r
3926 #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11
\r
3927 #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12
\r
3928 #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13
\r
3929 #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14
\r
3930 #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15
\r
3931 #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8
\r
3932 #define ATD1DR2H_BIT ATD1DR2H_BIT_8
\r
3934 /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/
\r
3944 byte BIT6 :1; /* Bit 6 */
\r
3945 byte BIT7 :1; /* Bit 7 */
\r
3957 #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte
\r
3958 #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6
\r
3959 #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7
\r
3960 #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6
\r
3961 #define ATD1DR2L_BIT ATD1DR2L_BIT_6
\r
3972 word BIT6 :1; /* Bit 6 */
\r
3973 word BIT7 :1; /* Bit 7 */
\r
3974 word BIT8 :1; /* Bit 8 */
\r
3975 word BIT9 :1; /* Bit 9 */
\r
3976 word BIT10 :1; /* Bit 10 */
\r
3977 word BIT11 :1; /* Bit 11 */
\r
3978 word BIT12 :1; /* Bit 12 */
\r
3979 word BIT13 :1; /* Bit 13 */
\r
3980 word BIT14 :1; /* Bit 14 */
\r
3981 word BIT15 :1; /* Bit 15 */
\r
3990 word grpBIT_6 :10;
\r
3993 extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134);
\r
3994 #define ATD1DR2 _ATD1DR2.Word
\r
3995 #define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6
\r
3996 #define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7
\r
3997 #define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8
\r
3998 #define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9
\r
3999 #define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10
\r
4000 #define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11
\r
4001 #define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12
\r
4002 #define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13
\r
4003 #define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14
\r
4004 #define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15
\r
4005 #define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6
\r
4006 #define ATD1DR2_BIT ATD1DR2_BIT_6
\r
4009 /*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/
\r
4012 /* Overlapped registers: */
\r
4014 /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/
\r
4018 byte BIT8 :1; /* Bit 8 */
\r
4019 byte BIT9 :1; /* Bit 9 */
\r
4020 byte BIT10 :1; /* Bit 10 */
\r
4021 byte BIT11 :1; /* Bit 11 */
\r
4022 byte BIT12 :1; /* Bit 12 */
\r
4023 byte BIT13 :1; /* Bit 13 */
\r
4024 byte BIT14 :1; /* Bit 14 */
\r
4025 byte BIT15 :1; /* Bit 15 */
\r
4031 #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte
\r
4032 #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8
\r
4033 #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9
\r
4034 #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10
\r
4035 #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11
\r
4036 #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12
\r
4037 #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13
\r
4038 #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14
\r
4039 #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15
\r
4040 #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8
\r
4041 #define ATD1DR3H_BIT ATD1DR3H_BIT_8
\r
4043 /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/
\r
4053 byte BIT6 :1; /* Bit 6 */
\r
4054 byte BIT7 :1; /* Bit 7 */
\r
4066 #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte
\r
4067 #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6
\r
4068 #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7
\r
4069 #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6
\r
4070 #define ATD1DR3L_BIT ATD1DR3L_BIT_6
\r
4081 word BIT6 :1; /* Bit 6 */
\r
4082 word BIT7 :1; /* Bit 7 */
\r
4083 word BIT8 :1; /* Bit 8 */
\r
4084 word BIT9 :1; /* Bit 9 */
\r
4085 word BIT10 :1; /* Bit 10 */
\r
4086 word BIT11 :1; /* Bit 11 */
\r
4087 word BIT12 :1; /* Bit 12 */
\r
4088 word BIT13 :1; /* Bit 13 */
\r
4089 word BIT14 :1; /* Bit 14 */
\r
4090 word BIT15 :1; /* Bit 15 */
\r
4099 word grpBIT_6 :10;
\r
4102 extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136);
\r
4103 #define ATD1DR3 _ATD1DR3.Word
\r
4104 #define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6
\r
4105 #define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7
\r
4106 #define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8
\r
4107 #define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9
\r
4108 #define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10
\r
4109 #define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11
\r
4110 #define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12
\r
4111 #define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13
\r
4112 #define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14
\r
4113 #define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15
\r
4114 #define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6
\r
4115 #define ATD1DR3_BIT ATD1DR3_BIT_6
\r
4118 /*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/
\r
4121 /* Overlapped registers: */
\r
4123 /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/
\r
4127 byte BIT8 :1; /* Bit 8 */
\r
4128 byte BIT9 :1; /* Bit 9 */
\r
4129 byte BIT10 :1; /* Bit 10 */
\r
4130 byte BIT11 :1; /* Bit 11 */
\r
4131 byte BIT12 :1; /* Bit 12 */
\r
4132 byte BIT13 :1; /* Bit 13 */
\r
4133 byte BIT14 :1; /* Bit 14 */
\r
4134 byte BIT15 :1; /* Bit 15 */
\r
4140 #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte
\r
4141 #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8
\r
4142 #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9
\r
4143 #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10
\r
4144 #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11
\r
4145 #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12
\r
4146 #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13
\r
4147 #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14
\r
4148 #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15
\r
4149 #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8
\r
4150 #define ATD1DR4H_BIT ATD1DR4H_BIT_8
\r
4152 /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/
\r
4162 byte BIT6 :1; /* Bit 6 */
\r
4163 byte BIT7 :1; /* Bit 7 */
\r
4175 #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte
\r
4176 #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6
\r
4177 #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7
\r
4178 #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6
\r
4179 #define ATD1DR4L_BIT ATD1DR4L_BIT_6
\r
4190 word BIT6 :1; /* Bit 6 */
\r
4191 word BIT7 :1; /* Bit 7 */
\r
4192 word BIT8 :1; /* Bit 8 */
\r
4193 word BIT9 :1; /* Bit 9 */
\r
4194 word BIT10 :1; /* Bit 10 */
\r
4195 word BIT11 :1; /* Bit 11 */
\r
4196 word BIT12 :1; /* Bit 12 */
\r
4197 word BIT13 :1; /* Bit 13 */
\r
4198 word BIT14 :1; /* Bit 14 */
\r
4199 word BIT15 :1; /* Bit 15 */
\r
4208 word grpBIT_6 :10;
\r
4211 extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138);
\r
4212 #define ATD1DR4 _ATD1DR4.Word
\r
4213 #define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6
\r
4214 #define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7
\r
4215 #define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8
\r
4216 #define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9
\r
4217 #define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10
\r
4218 #define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11
\r
4219 #define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12
\r
4220 #define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13
\r
4221 #define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14
\r
4222 #define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15
\r
4223 #define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6
\r
4224 #define ATD1DR4_BIT ATD1DR4_BIT_6
\r
4227 /*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/
\r
4230 /* Overlapped registers: */
\r
4232 /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/
\r
4236 byte BIT8 :1; /* Bit 8 */
\r
4237 byte BIT9 :1; /* Bit 9 */
\r
4238 byte BIT10 :1; /* Bit 10 */
\r
4239 byte BIT11 :1; /* Bit 11 */
\r
4240 byte BIT12 :1; /* Bit 12 */
\r
4241 byte BIT13 :1; /* Bit 13 */
\r
4242 byte BIT14 :1; /* Bit 14 */
\r
4243 byte BIT15 :1; /* Bit 15 */
\r
4249 #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte
\r
4250 #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8
\r
4251 #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9
\r
4252 #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10
\r
4253 #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11
\r
4254 #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12
\r
4255 #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13
\r
4256 #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14
\r
4257 #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15
\r
4258 #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8
\r
4259 #define ATD1DR5H_BIT ATD1DR5H_BIT_8
\r
4261 /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/
\r
4271 byte BIT6 :1; /* Bit 6 */
\r
4272 byte BIT7 :1; /* Bit 7 */
\r
4284 #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte
\r
4285 #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6
\r
4286 #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7
\r
4287 #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6
\r
4288 #define ATD1DR5L_BIT ATD1DR5L_BIT_6
\r
4299 word BIT6 :1; /* Bit 6 */
\r
4300 word BIT7 :1; /* Bit 7 */
\r
4301 word BIT8 :1; /* Bit 8 */
\r
4302 word BIT9 :1; /* Bit 9 */
\r
4303 word BIT10 :1; /* Bit 10 */
\r
4304 word BIT11 :1; /* Bit 11 */
\r
4305 word BIT12 :1; /* Bit 12 */
\r
4306 word BIT13 :1; /* Bit 13 */
\r
4307 word BIT14 :1; /* Bit 14 */
\r
4308 word BIT15 :1; /* Bit 15 */
\r
4317 word grpBIT_6 :10;
\r
4320 extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A);
\r
4321 #define ATD1DR5 _ATD1DR5.Word
\r
4322 #define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6
\r
4323 #define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7
\r
4324 #define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8
\r
4325 #define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9
\r
4326 #define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10
\r
4327 #define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11
\r
4328 #define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12
\r
4329 #define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13
\r
4330 #define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14
\r
4331 #define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15
\r
4332 #define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6
\r
4333 #define ATD1DR5_BIT ATD1DR5_BIT_6
\r
4336 /*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/
\r
4339 /* Overlapped registers: */
\r
4341 /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/
\r
4345 byte BIT8 :1; /* Bit 8 */
\r
4346 byte BIT9 :1; /* Bit 9 */
\r
4347 byte BIT10 :1; /* Bit 10 */
\r
4348 byte BIT11 :1; /* Bit 11 */
\r
4349 byte BIT12 :1; /* Bit 12 */
\r
4350 byte BIT13 :1; /* Bit 13 */
\r
4351 byte BIT14 :1; /* Bit 14 */
\r
4352 byte BIT15 :1; /* Bit 15 */
\r
4358 #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte
\r
4359 #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8
\r
4360 #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9
\r
4361 #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10
\r
4362 #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11
\r
4363 #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12
\r
4364 #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13
\r
4365 #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14
\r
4366 #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15
\r
4367 #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8
\r
4368 #define ATD1DR6H_BIT ATD1DR6H_BIT_8
\r
4370 /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/
\r
4380 byte BIT6 :1; /* Bit 6 */
\r
4381 byte BIT7 :1; /* Bit 7 */
\r
4393 #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte
\r
4394 #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6
\r
4395 #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7
\r
4396 #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6
\r
4397 #define ATD1DR6L_BIT ATD1DR6L_BIT_6
\r
4408 word BIT6 :1; /* Bit 6 */
\r
4409 word BIT7 :1; /* Bit 7 */
\r
4410 word BIT8 :1; /* Bit 8 */
\r
4411 word BIT9 :1; /* Bit 9 */
\r
4412 word BIT10 :1; /* Bit 10 */
\r
4413 word BIT11 :1; /* Bit 11 */
\r
4414 word BIT12 :1; /* Bit 12 */
\r
4415 word BIT13 :1; /* Bit 13 */
\r
4416 word BIT14 :1; /* Bit 14 */
\r
4417 word BIT15 :1; /* Bit 15 */
\r
4426 word grpBIT_6 :10;
\r
4429 extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C);
\r
4430 #define ATD1DR6 _ATD1DR6.Word
\r
4431 #define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6
\r
4432 #define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7
\r
4433 #define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8
\r
4434 #define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9
\r
4435 #define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10
\r
4436 #define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11
\r
4437 #define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12
\r
4438 #define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13
\r
4439 #define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14
\r
4440 #define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15
\r
4441 #define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6
\r
4442 #define ATD1DR6_BIT ATD1DR6_BIT_6
\r
4445 /*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/
\r
4448 /* Overlapped registers: */
\r
4450 /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/
\r
4454 byte BIT8 :1; /* Bit 8 */
\r
4455 byte BIT9 :1; /* Bit 9 */
\r
4456 byte BIT10 :1; /* Bit 10 */
\r
4457 byte BIT11 :1; /* Bit 11 */
\r
4458 byte BIT12 :1; /* Bit 12 */
\r
4459 byte BIT13 :1; /* Bit 13 */
\r
4460 byte BIT14 :1; /* Bit 14 */
\r
4461 byte BIT15 :1; /* Bit 15 */
\r
4467 #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte
\r
4468 #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8
\r
4469 #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9
\r
4470 #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10
\r
4471 #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11
\r
4472 #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12
\r
4473 #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13
\r
4474 #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14
\r
4475 #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15
\r
4476 #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8
\r
4477 #define ATD1DR7H_BIT ATD1DR7H_BIT_8
\r
4479 /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/
\r
4489 byte BIT6 :1; /* Bit 6 */
\r
4490 byte BIT7 :1; /* Bit 7 */
\r
4502 #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte
\r
4503 #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6
\r
4504 #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7
\r
4505 #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6
\r
4506 #define ATD1DR7L_BIT ATD1DR7L_BIT_6
\r
4517 word BIT6 :1; /* Bit 6 */
\r
4518 word BIT7 :1; /* Bit 7 */
\r
4519 word BIT8 :1; /* Bit 8 */
\r
4520 word BIT9 :1; /* Bit 9 */
\r
4521 word BIT10 :1; /* Bit 10 */
\r
4522 word BIT11 :1; /* Bit 11 */
\r
4523 word BIT12 :1; /* Bit 12 */
\r
4524 word BIT13 :1; /* Bit 13 */
\r
4525 word BIT14 :1; /* Bit 14 */
\r
4526 word BIT15 :1; /* Bit 15 */
\r
4535 word grpBIT_6 :10;
\r
4538 extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E);
\r
4539 #define ATD1DR7 _ATD1DR7.Word
\r
4540 #define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6
\r
4541 #define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7
\r
4542 #define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8
\r
4543 #define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9
\r
4544 #define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10
\r
4545 #define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11
\r
4546 #define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12
\r
4547 #define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13
\r
4548 #define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14
\r
4549 #define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15
\r
4550 #define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6
\r
4551 #define ATD1DR7_BIT ATD1DR7_BIT_6
\r
4554 /*** PORTE - Port E Register; 0x00000008 ***/
\r
4558 byte BIT0 :1; /* Port E Bit 0, XIRQ */
\r
4559 byte BIT1 :1; /* Port E Bit 1, IRQ */
\r
4560 byte BIT2 :1; /* Port E Bit 2, R/W */
\r
4561 byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */
\r
4562 byte BIT4 :1; /* Port E Bit 4, ECLK */
\r
4563 byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */
\r
4564 byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */
\r
4565 byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */
\r
4571 extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
\r
4572 #define PORTE _PORTE.Byte
\r
4573 #define PORTE_BIT0 _PORTE.Bits.BIT0
\r
4574 #define PORTE_BIT1 _PORTE.Bits.BIT1
\r
4575 #define PORTE_BIT2 _PORTE.Bits.BIT2
\r
4576 #define PORTE_BIT3 _PORTE.Bits.BIT3
\r
4577 #define PORTE_BIT4 _PORTE.Bits.BIT4
\r
4578 #define PORTE_BIT5 _PORTE.Bits.BIT5
\r
4579 #define PORTE_BIT6 _PORTE.Bits.BIT6
\r
4580 #define PORTE_BIT7 _PORTE.Bits.BIT7
\r
4581 #define PORTE_BIT _PORTE.MergedBits.grpBIT
\r
4584 /*** DDRE - Port E Data Direction Register; 0x00000009 ***/
\r
4588 byte BIT0 :1; /* Data Direction Port A Bit 0 */
\r
4589 byte BIT1 :1; /* Data Direction Port A Bit 1 */
\r
4590 byte BIT2 :1; /* Data Direction Port A Bit 2 */
\r
4591 byte BIT3 :1; /* Data Direction Port A Bit 3 */
\r
4592 byte BIT4 :1; /* Data Direction Port A Bit 4 */
\r
4593 byte BIT5 :1; /* Data Direction Port A Bit 5 */
\r
4594 byte BIT6 :1; /* Data Direction Port A Bit 6 */
\r
4595 byte BIT7 :1; /* Data Direction Port A Bit 7 */
\r
4601 extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
\r
4602 #define DDRE _DDRE.Byte
\r
4603 #define DDRE_BIT0 _DDRE.Bits.BIT0
\r
4604 #define DDRE_BIT1 _DDRE.Bits.BIT1
\r
4605 #define DDRE_BIT2 _DDRE.Bits.BIT2
\r
4606 #define DDRE_BIT3 _DDRE.Bits.BIT3
\r
4607 #define DDRE_BIT4 _DDRE.Bits.BIT4
\r
4608 #define DDRE_BIT5 _DDRE.Bits.BIT5
\r
4609 #define DDRE_BIT6 _DDRE.Bits.BIT6
\r
4610 #define DDRE_BIT7 _DDRE.Bits.BIT7
\r
4611 #define DDRE_BIT _DDRE.MergedBits.grpBIT
\r
4614 /*** PEAR - Port E Assignment Register; 0x0000000A ***/
\r
4620 byte RDWE :1; /* Read / Write Enable */
\r
4621 byte LSTRE :1; /* Low Strobe (LSTRB) Enable */
\r
4622 byte NECLK :1; /* No External E Clock */
\r
4623 byte PIPOE :1; /* Pipe Status Signal Output Enable */
\r
4625 byte NOACCE :1; /* CPU No Access Output Enable */
\r
4628 extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
\r
4629 #define PEAR _PEAR.Byte
\r
4630 #define PEAR_RDWE _PEAR.Bits.RDWE
\r
4631 #define PEAR_LSTRE _PEAR.Bits.LSTRE
\r
4632 #define PEAR_NECLK _PEAR.Bits.NECLK
\r
4633 #define PEAR_PIPOE _PEAR.Bits.PIPOE
\r
4634 #define PEAR_NOACCE _PEAR.Bits.NOACCE
\r
4637 /*** MODE - Mode Register; 0x0000000B ***/
\r
4641 byte EME :1; /* Emulate Port E */
\r
4642 byte EMK :1; /* Emulate Port K */
\r
4644 byte IVIS :1; /* Internal Visibility */
\r
4646 byte MODA :1; /* Mode Select Bit A */
\r
4647 byte MODB :1; /* Mode Select Bit B */
\r
4648 byte MODC :1; /* Mode Select Bit C */
\r
4651 extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
\r
4652 #define MODE _MODE.Byte
\r
4653 #define MODE_EME _MODE.Bits.EME
\r
4654 #define MODE_EMK _MODE.Bits.EMK
\r
4655 #define MODE_IVIS _MODE.Bits.IVIS
\r
4656 #define MODE_MODA _MODE.Bits.MODA
\r
4657 #define MODE_MODB _MODE.Bits.MODB
\r
4658 #define MODE_MODC _MODE.Bits.MODC
\r
4661 /*** PUCR - Pull-Up Control Register; 0x0000000C ***/
\r
4665 byte PUPAE :1; /* Pull-Up Port A Enable */
\r
4666 byte PUPBE :1; /* Pull-Up Port B Enable */
\r
4669 byte PUPEE :1; /* Pull-Up Port E Enable */
\r
4672 byte PUPKE :1; /* Pull-Up Port K Enable */
\r
4675 extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);
\r
4676 #define PUCR _PUCR.Byte
\r
4677 #define PUCR_PUPAE _PUCR.Bits.PUPAE
\r
4678 #define PUCR_PUPBE _PUCR.Bits.PUPBE
\r
4679 #define PUCR_PUPEE _PUCR.Bits.PUPEE
\r
4680 #define PUCR_PUPKE _PUCR.Bits.PUPKE
\r
4683 /*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/
\r
4687 byte RDPA :1; /* Reduced Drive of Port A */
\r
4688 byte RDPB :1; /* Reduced Drive of Port B */
\r
4691 byte RDPE :1; /* Reduced Drive of Port E */
\r
4694 byte RDPK :1; /* Reduced Drive of Port K */
\r
4697 extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
\r
4698 #define RDRIV _RDRIV.Byte
\r
4699 #define RDRIV_RDPA _RDRIV.Bits.RDPA
\r
4700 #define RDRIV_RDPB _RDRIV.Bits.RDPB
\r
4701 #define RDRIV_RDPE _RDRIV.Bits.RDPE
\r
4702 #define RDRIV_RDPK _RDRIV.Bits.RDPK
\r
4705 /*** EBICTL - External Bus Interface Control; 0x0000000E ***/
\r
4709 byte ESTR :1; /* E Stretches */
\r
4719 extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
\r
4720 #define EBICTL _EBICTL.Byte
\r
4721 #define EBICTL_ESTR _EBICTL.Bits.ESTR
\r
4724 /*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
\r
4728 byte RAMHAL :1; /* Internal RAM map alignment */
\r
4731 byte RAM11 :1; /* Internal RAM map position Bit 11 */
\r
4732 byte RAM12 :1; /* Internal RAM map position Bit 12 */
\r
4733 byte RAM13 :1; /* Internal RAM map position Bit 13 */
\r
4734 byte RAM14 :1; /* Internal RAM map position Bit 14 */
\r
4735 byte RAM15 :1; /* Internal RAM map position Bit 15 */
\r
4741 byte grpRAM_11 :5;
\r
4744 extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
\r
4745 #define INITRM _INITRM.Byte
\r
4746 #define INITRM_RAMHAL _INITRM.Bits.RAMHAL
\r
4747 #define INITRM_RAM11 _INITRM.Bits.RAM11
\r
4748 #define INITRM_RAM12 _INITRM.Bits.RAM12
\r
4749 #define INITRM_RAM13 _INITRM.Bits.RAM13
\r
4750 #define INITRM_RAM14 _INITRM.Bits.RAM14
\r
4751 #define INITRM_RAM15 _INITRM.Bits.RAM15
\r
4752 #define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
\r
4753 #define INITRM_RAM INITRM_RAM_11
\r
4756 /*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/
\r
4763 byte REG11 :1; /* Internal register map position REG11 */
\r
4764 byte REG12 :1; /* Internal register map position REG12 */
\r
4765 byte REG13 :1; /* Internal register map position REG13 */
\r
4766 byte REG14 :1; /* Internal register map position REG14 */
\r
4773 byte grpREG_11 :4;
\r
4777 extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
\r
4778 #define INITRG _INITRG.Byte
\r
4779 #define INITRG_REG11 _INITRG.Bits.REG11
\r
4780 #define INITRG_REG12 _INITRG.Bits.REG12
\r
4781 #define INITRG_REG13 _INITRG.Bits.REG13
\r
4782 #define INITRG_REG14 _INITRG.Bits.REG14
\r
4783 #define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
\r
4784 #define INITRG_REG INITRG_REG_11
\r
4787 /*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
\r
4791 byte EEON :1; /* Internal EEPROM On */
\r
4795 byte EE12 :1; /* Internal EEPROM map position Bit 12 */
\r
4796 byte EE13 :1; /* Internal EEPROM map position Bit 13 */
\r
4797 byte EE14 :1; /* Internal EEPROM map position Bit 14 */
\r
4798 byte EE15 :1; /* Internal EEPROM map position Bit 15 */
\r
4808 extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
\r
4809 #define INITEE _INITEE.Byte
\r
4810 #define INITEE_EEON _INITEE.Bits.EEON
\r
4811 #define INITEE_EE12 _INITEE.Bits.EE12
\r
4812 #define INITEE_EE13 _INITEE.Bits.EE13
\r
4813 #define INITEE_EE14 _INITEE.Bits.EE14
\r
4814 #define INITEE_EE15 _INITEE.Bits.EE15
\r
4815 #define INITEE_EE_12 _INITEE.MergedBits.grpEE_12
\r
4816 #define INITEE_EE INITEE_EE_12
\r
4819 /*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/
\r
4823 byte ROMON :1; /* Enable Flash EEPROM */
\r
4824 byte ROMHM :1; /* Flash EEPROM only in second half of memory map */
\r
4825 byte EXSTR0 :1; /* External Access Stretch Bit 0 */
\r
4826 byte EXSTR1 :1; /* External Access Stretch Bit 1 */
\r
4842 extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
\r
4843 #define MISC _MISC.Byte
\r
4844 #define MISC_ROMON _MISC.Bits.ROMON
\r
4845 #define MISC_ROMHM _MISC.Bits.ROMHM
\r
4846 #define MISC_EXSTR0 _MISC.Bits.EXSTR0
\r
4847 #define MISC_EXSTR1 _MISC.Bits.EXSTR1
\r
4848 #define MISC_EXSTR _MISC.MergedBits.grpEXSTR
\r
4851 /*** MTST0 - MTST0; 0x00000014 ***/
\r
4855 byte BIT0 :1; /* MTST0 Bit 0 */
\r
4856 byte BIT1 :1; /* MTST0 Bit 1 */
\r
4857 byte BIT2 :1; /* MTST0 Bit 2 */
\r
4858 byte BIT3 :1; /* MTST0 Bit 3 */
\r
4859 byte BIT4 :1; /* MTST0 Bit 4 */
\r
4860 byte BIT5 :1; /* MTST0 Bit 5 */
\r
4861 byte BIT6 :1; /* MTST0 Bit 6 */
\r
4862 byte BIT7 :1; /* MTST0 Bit 7 */
\r
4868 extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);
\r
4869 #define MTST0 _MTST0.Byte
\r
4870 #define MTST0_BIT0 _MTST0.Bits.BIT0
\r
4871 #define MTST0_BIT1 _MTST0.Bits.BIT1
\r
4872 #define MTST0_BIT2 _MTST0.Bits.BIT2
\r
4873 #define MTST0_BIT3 _MTST0.Bits.BIT3
\r
4874 #define MTST0_BIT4 _MTST0.Bits.BIT4
\r
4875 #define MTST0_BIT5 _MTST0.Bits.BIT5
\r
4876 #define MTST0_BIT6 _MTST0.Bits.BIT6
\r
4877 #define MTST0_BIT7 _MTST0.Bits.BIT7
\r
4878 #define MTST0_BIT _MTST0.MergedBits.grpBIT
\r
4881 /*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
\r
4885 byte ADR0 :1; /* Test register select Bit 0 */
\r
4886 byte ADR1 :1; /* Test register select Bit 1 */
\r
4887 byte ADR2 :1; /* Test register select Bit 2 */
\r
4888 byte ADR3 :1; /* Test register select Bit 3 */
\r
4889 byte WRTINT :1; /* Write to the Interrupt Test Registers */
\r
4902 extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
\r
4903 #define ITCR _ITCR.Byte
\r
4904 #define ITCR_ADR0 _ITCR.Bits.ADR0
\r
4905 #define ITCR_ADR1 _ITCR.Bits.ADR1
\r
4906 #define ITCR_ADR2 _ITCR.Bits.ADR2
\r
4907 #define ITCR_ADR3 _ITCR.Bits.ADR3
\r
4908 #define ITCR_WRTINT _ITCR.Bits.WRTINT
\r
4909 #define ITCR_ADR _ITCR.MergedBits.grpADR
\r
4912 /*** ITEST - Interrupt Test Register; 0x00000016 ***/
\r
4916 byte INT0 :1; /* Interrupt Test Register Bit 0 */
\r
4917 byte INT2 :1; /* Interrupt Test Register Bit 1 */
\r
4918 byte INT4 :1; /* Interrupt Test Register Bit 2 */
\r
4919 byte INT6 :1; /* Interrupt Test Register Bit 3 */
\r
4920 byte INT8 :1; /* Interrupt Test Register Bit 4 */
\r
4921 byte INTA :1; /* Interrupt Test Register Bit 5 */
\r
4922 byte INTC :1; /* Interrupt Test Register Bit 6 */
\r
4923 byte INTE :1; /* Interrupt Test Register Bit 7 */
\r
4926 extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
\r
4927 #define ITEST _ITEST.Byte
\r
4928 #define ITEST_INT0 _ITEST.Bits.INT0
\r
4929 #define ITEST_INT2 _ITEST.Bits.INT2
\r
4930 #define ITEST_INT4 _ITEST.Bits.INT4
\r
4931 #define ITEST_INT6 _ITEST.Bits.INT6
\r
4932 #define ITEST_INT8 _ITEST.Bits.INT8
\r
4933 #define ITEST_INTA _ITEST.Bits.INTA
\r
4934 #define ITEST_INTC _ITEST.Bits.INTC
\r
4935 #define ITEST_INTE _ITEST.Bits.INTE
\r
4938 /*** MTST1 - MTST1; 0x00000017 ***/
\r
4942 byte BIT0 :1; /* MTST1 Bit 0 */
\r
4943 byte BIT1 :1; /* MTST1 Bit 1 */
\r
4944 byte BIT2 :1; /* MTST1 Bit 2 */
\r
4945 byte BIT3 :1; /* MTST1 Bit 3 */
\r
4946 byte BIT4 :1; /* MTST1 Bit 4 */
\r
4947 byte BIT5 :1; /* MTST1 Bit 5 */
\r
4948 byte BIT6 :1; /* MTST1 Bit 6 */
\r
4949 byte BIT7 :1; /* MTST1 Bit 7 */
\r
4955 extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);
\r
4956 #define MTST1 _MTST1.Byte
\r
4957 #define MTST1_BIT0 _MTST1.Bits.BIT0
\r
4958 #define MTST1_BIT1 _MTST1.Bits.BIT1
\r
4959 #define MTST1_BIT2 _MTST1.Bits.BIT2
\r
4960 #define MTST1_BIT3 _MTST1.Bits.BIT3
\r
4961 #define MTST1_BIT4 _MTST1.Bits.BIT4
\r
4962 #define MTST1_BIT5 _MTST1.Bits.BIT5
\r
4963 #define MTST1_BIT6 _MTST1.Bits.BIT6
\r
4964 #define MTST1_BIT7 _MTST1.Bits.BIT7
\r
4965 #define MTST1_BIT _MTST1.MergedBits.grpBIT
\r
4968 /*** PARTIDH - Part ID Register High; 0x0000001A ***/
\r
4972 byte ID15 :1; /* Part ID Register Bit 15 */
\r
4973 byte ID14 :1; /* Part ID Register Bit 14 */
\r
4974 byte ID13 :1; /* Part ID Register Bit 13 */
\r
4975 byte ID12 :1; /* Part ID Register Bit 12 */
\r
4976 byte ID11 :1; /* Part ID Register Bit 11 */
\r
4977 byte ID10 :1; /* Part ID Register Bit 10 */
\r
4978 byte ID9 :1; /* Part ID Register Bit 9 */
\r
4979 byte ID8 :1; /* Part ID Register Bit 8 */
\r
4982 extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
\r
4983 #define PARTIDH _PARTIDH.Byte
\r
4984 #define PARTIDH_ID15 _PARTIDH.Bits.ID15
\r
4985 #define PARTIDH_ID14 _PARTIDH.Bits.ID14
\r
4986 #define PARTIDH_ID13 _PARTIDH.Bits.ID13
\r
4987 #define PARTIDH_ID12 _PARTIDH.Bits.ID12
\r
4988 #define PARTIDH_ID11 _PARTIDH.Bits.ID11
\r
4989 #define PARTIDH_ID10 _PARTIDH.Bits.ID10
\r
4990 #define PARTIDH_ID9 _PARTIDH.Bits.ID9
\r
4991 #define PARTIDH_ID8 _PARTIDH.Bits.ID8
\r
4994 /*** PARTIDL - Part ID Register Low; 0x0000001B ***/
\r
4998 byte ID0 :1; /* Part ID Register Bit 0 */
\r
4999 byte ID1 :1; /* Part ID Register Bit 1 */
\r
5000 byte ID2 :1; /* Part ID Register Bit 2 */
\r
5001 byte ID3 :1; /* Part ID Register Bit 3 */
\r
5002 byte ID4 :1; /* Part ID Register Bit 4 */
\r
5003 byte ID5 :1; /* Part ID Register Bit 5 */
\r
5004 byte ID6 :1; /* Part ID Register Bit 6 */
\r
5005 byte ID7 :1; /* Part ID Register Bit 7 */
\r
5011 extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
\r
5012 #define PARTIDL _PARTIDL.Byte
\r
5013 #define PARTIDL_ID0 _PARTIDL.Bits.ID0
\r
5014 #define PARTIDL_ID1 _PARTIDL.Bits.ID1
\r
5015 #define PARTIDL_ID2 _PARTIDL.Bits.ID2
\r
5016 #define PARTIDL_ID3 _PARTIDL.Bits.ID3
\r
5017 #define PARTIDL_ID4 _PARTIDL.Bits.ID4
\r
5018 #define PARTIDL_ID5 _PARTIDL.Bits.ID5
\r
5019 #define PARTIDL_ID6 _PARTIDL.Bits.ID6
\r
5020 #define PARTIDL_ID7 _PARTIDL.Bits.ID7
\r
5021 #define PARTIDL_ID _PARTIDL.MergedBits.grpID
\r
5024 /*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
\r
5028 byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
\r
5029 byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
\r
5030 byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
\r
5032 byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
\r
5033 byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
\r
5035 byte reg_sw0 :1; /* Allocated System Register Space */
\r
5038 byte grpram_sw :3;
\r
5040 byte grpeep_sw :2;
\r
5042 byte grpreg_sw :1;
\r
5045 extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
\r
5046 #define MEMSIZ0 _MEMSIZ0.Byte
\r
5047 #define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
\r
5048 #define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
\r
5049 #define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
\r
5050 #define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
\r
5051 #define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
\r
5052 #define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
\r
5053 #define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
\r
5054 #define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
\r
5057 /*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
\r
5061 byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
\r
5062 byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
\r
5067 byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
\r
5068 byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
\r
5071 byte grppag_sw :2;
\r
5076 byte grprom_sw :2;
\r
5079 extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
\r
5080 #define MEMSIZ1 _MEMSIZ1.Byte
\r
5081 #define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
\r
5082 #define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
\r
5083 #define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
\r
5084 #define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
\r
5085 #define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
\r
5086 #define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
\r
5089 /*** INTCR - Interrupt Control Register; 0x0000001E ***/
\r
5099 byte IRQEN :1; /* External IRQ Enable */
\r
5100 byte IRQE :1; /* IRQ Select Edge Sensitive Only */
\r
5103 extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
\r
5104 #define INTCR _INTCR.Byte
\r
5105 #define INTCR_IRQEN _INTCR.Bits.IRQEN
\r
5106 #define INTCR_IRQE _INTCR.Bits.IRQE
\r
5109 /*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
\r
5114 byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
\r
5115 byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
\r
5116 byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
\r
5117 byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
\r
5118 byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
\r
5119 byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
\r
5120 byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
\r
5124 byte grpPSEL_1 :7;
\r
5127 extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
\r
5128 #define HPRIO _HPRIO.Byte
\r
5129 #define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
\r
5130 #define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
\r
5131 #define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
\r
5132 #define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
\r
5133 #define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
\r
5134 #define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
\r
5135 #define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
\r
5136 #define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
\r
5137 #define HPRIO_PSEL HPRIO_PSEL_1
\r
5140 /*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
\r
5148 byte BKTAG :1; /* Breakpoint on Tag */
\r
5149 byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */
\r
5150 byte BKFULL :1; /* Full Breakpoint Mode Enable */
\r
5151 byte BKEN :1; /* Breakpoint Enable */
\r
5154 extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
\r
5155 #define BKPCT0 _BKPCT0.Byte
\r
5156 #define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
\r
5157 #define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
\r
5158 #define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
\r
5159 #define BKPCT0_BKEN _BKPCT0.Bits.BKEN
\r
5162 /*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
\r
5166 byte BK1RW :1; /* R/W Compare Value 1 */
\r
5167 byte BK1RWE :1; /* R/W Compare Enable 1 */
\r
5168 byte BK0RW :1; /* R/W Compare Value 0 */
\r
5169 byte BK0RWE :1; /* R/W Compare Enable 0 */
\r
5170 byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */
\r
5171 byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */
\r
5172 byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */
\r
5173 byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */
\r
5176 extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
\r
5177 #define BKPCT1 _BKPCT1.Byte
\r
5178 #define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
\r
5179 #define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
\r
5180 #define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
\r
5181 #define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
\r
5182 #define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
\r
5183 #define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
\r
5184 #define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
\r
5185 #define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH
\r
5188 /*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
\r
5192 byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */
\r
5193 byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */
\r
5194 byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */
\r
5195 byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */
\r
5196 byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */
\r
5197 byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */
\r
5207 extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
\r
5208 #define BKP0X _BKP0X.Byte
\r
5209 #define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
\r
5210 #define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
\r
5211 #define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
\r
5212 #define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
\r
5213 #define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
\r
5214 #define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
\r
5215 #define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V
\r
5218 /*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
\r
5222 byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */
\r
5223 byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */
\r
5224 byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */
\r
5225 byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */
\r
5226 byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */
\r
5227 byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */
\r
5228 byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */
\r
5229 byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */
\r
5235 extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);
\r
5236 #define BKP0H _BKP0H.Byte
\r
5237 #define BKP0H_BIT8 _BKP0H.Bits.BIT8
\r
5238 #define BKP0H_BIT9 _BKP0H.Bits.BIT9
\r
5239 #define BKP0H_BIT10 _BKP0H.Bits.BIT10
\r
5240 #define BKP0H_BIT11 _BKP0H.Bits.BIT11
\r
5241 #define BKP0H_BIT12 _BKP0H.Bits.BIT12
\r
5242 #define BKP0H_BIT13 _BKP0H.Bits.BIT13
\r
5243 #define BKP0H_BIT14 _BKP0H.Bits.BIT14
\r
5244 #define BKP0H_BIT15 _BKP0H.Bits.BIT15
\r
5245 #define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8
\r
5246 #define BKP0H_BIT BKP0H_BIT_8
\r
5249 /*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/
\r
5253 byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */
\r
5254 byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */
\r
5255 byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */
\r
5256 byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */
\r
5257 byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */
\r
5258 byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */
\r
5259 byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */
\r
5260 byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */
\r
5266 extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);
\r
5267 #define BKP0L _BKP0L.Byte
\r
5268 #define BKP0L_BIT0 _BKP0L.Bits.BIT0
\r
5269 #define BKP0L_BIT1 _BKP0L.Bits.BIT1
\r
5270 #define BKP0L_BIT2 _BKP0L.Bits.BIT2
\r
5271 #define BKP0L_BIT3 _BKP0L.Bits.BIT3
\r
5272 #define BKP0L_BIT4 _BKP0L.Bits.BIT4
\r
5273 #define BKP0L_BIT5 _BKP0L.Bits.BIT5
\r
5274 #define BKP0L_BIT6 _BKP0L.Bits.BIT6
\r
5275 #define BKP0L_BIT7 _BKP0L.Bits.BIT7
\r
5276 #define BKP0L_BIT _BKP0L.MergedBits.grpBIT
\r
5279 /*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/
\r
5283 byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */
\r
5284 byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */
\r
5285 byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */
\r
5286 byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */
\r
5287 byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */
\r
5288 byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */
\r
5298 extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);
\r
5299 #define BKP1X _BKP1X.Byte
\r
5300 #define BKP1X_BK1V0 _BKP1X.Bits.BK1V0
\r
5301 #define BKP1X_BK1V1 _BKP1X.Bits.BK1V1
\r
5302 #define BKP1X_BK1V2 _BKP1X.Bits.BK1V2
\r
5303 #define BKP1X_BK1V3 _BKP1X.Bits.BK1V3
\r
5304 #define BKP1X_BK1V4 _BKP1X.Bits.BK1V4
\r
5305 #define BKP1X_BK1V5 _BKP1X.Bits.BK1V5
\r
5306 #define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V
\r
5309 /*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/
\r
5313 byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */
\r
5314 byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */
\r
5315 byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */
\r
5316 byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */
\r
5317 byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */
\r
5318 byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */
\r
5319 byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */
\r
5320 byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */
\r
5326 extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);
\r
5327 #define BKP1H _BKP1H.Byte
\r
5328 #define BKP1H_BIT8 _BKP1H.Bits.BIT8
\r
5329 #define BKP1H_BIT9 _BKP1H.Bits.BIT9
\r
5330 #define BKP1H_BIT10 _BKP1H.Bits.BIT10
\r
5331 #define BKP1H_BIT11 _BKP1H.Bits.BIT11
\r
5332 #define BKP1H_BIT12 _BKP1H.Bits.BIT12
\r
5333 #define BKP1H_BIT13 _BKP1H.Bits.BIT13
\r
5334 #define BKP1H_BIT14 _BKP1H.Bits.BIT14
\r
5335 #define BKP1H_BIT15 _BKP1H.Bits.BIT15
\r
5336 #define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8
\r
5337 #define BKP1H_BIT BKP1H_BIT_8
\r
5340 /*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/
\r
5344 byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */
\r
5345 byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */
\r
5346 byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */
\r
5347 byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */
\r
5348 byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */
\r
5349 byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */
\r
5350 byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */
\r
5351 byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */
\r
5357 extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);
\r
5358 #define BKP1L _BKP1L.Byte
\r
5359 #define BKP1L_BIT0 _BKP1L.Bits.BIT0
\r
5360 #define BKP1L_BIT1 _BKP1L.Bits.BIT1
\r
5361 #define BKP1L_BIT2 _BKP1L.Bits.BIT2
\r
5362 #define BKP1L_BIT3 _BKP1L.Bits.BIT3
\r
5363 #define BKP1L_BIT4 _BKP1L.Bits.BIT4
\r
5364 #define BKP1L_BIT5 _BKP1L.Bits.BIT5
\r
5365 #define BKP1L_BIT6 _BKP1L.Bits.BIT6
\r
5366 #define BKP1L_BIT7 _BKP1L.Bits.BIT7
\r
5367 #define BKP1L_BIT _BKP1L.MergedBits.grpBIT
\r
5370 /*** PPAGE - Page Index Register; 0x00000030 ***/
\r
5374 byte PIX0 :1; /* Page Index Register Bit 0 */
\r
5375 byte PIX1 :1; /* Page Index Register Bit 1 */
\r
5376 byte PIX2 :1; /* Page Index Register Bit 2 */
\r
5377 byte PIX3 :1; /* Page Index Register Bit 3 */
\r
5378 byte PIX4 :1; /* Page Index Register Bit 4 */
\r
5379 byte PIX5 :1; /* Page Index Register Bit 5 */
\r
5389 extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);
\r
5390 #define PPAGE _PPAGE.Byte
\r
5391 #define PPAGE_PIX0 _PPAGE.Bits.PIX0
\r
5392 #define PPAGE_PIX1 _PPAGE.Bits.PIX1
\r
5393 #define PPAGE_PIX2 _PPAGE.Bits.PIX2
\r
5394 #define PPAGE_PIX3 _PPAGE.Bits.PIX3
\r
5395 #define PPAGE_PIX4 _PPAGE.Bits.PIX4
\r
5396 #define PPAGE_PIX5 _PPAGE.Bits.PIX5
\r
5397 #define PPAGE_PIX _PPAGE.MergedBits.grpPIX
\r
5400 /*** PORTK - Port K Data Register; 0x00000032 ***/
\r
5404 byte BIT0 :1; /* Port K Bit 0 */
\r
5405 byte BIT1 :1; /* Port K Bit 1 */
\r
5406 byte BIT2 :1; /* Port K Bit 2 */
\r
5407 byte BIT3 :1; /* Port K Bit 3 */
\r
5408 byte BIT4 :1; /* Port K Bit 4 */
\r
5409 byte BIT5 :1; /* Port K Bit 5 */
\r
5411 byte BIT7 :1; /* Port K Bit 7 */
\r
5419 extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
\r
5420 #define PORTK _PORTK.Byte
\r
5421 #define PORTK_BIT0 _PORTK.Bits.BIT0
\r
5422 #define PORTK_BIT1 _PORTK.Bits.BIT1
\r
5423 #define PORTK_BIT2 _PORTK.Bits.BIT2
\r
5424 #define PORTK_BIT3 _PORTK.Bits.BIT3
\r
5425 #define PORTK_BIT4 _PORTK.Bits.BIT4
\r
5426 #define PORTK_BIT5 _PORTK.Bits.BIT5
\r
5427 #define PORTK_BIT7 _PORTK.Bits.BIT7
\r
5428 #define PORTK_BIT _PORTK.MergedBits.grpBIT
\r
5431 /*** DDRK - Port K Data Direction Register; 0x00000033 ***/
\r
5435 byte DDK0 :1; /* Port K Data Direction Bit 0 */
\r
5436 byte DDK1 :1; /* Port K Data Direction Bit 1 */
\r
5437 byte DDK2 :1; /* Port K Data Direction Bit 2 */
\r
5438 byte DDK3 :1; /* Port K Data Direction Bit 3 */
\r
5439 byte DDK4 :1; /* Port K Data Direction Bit 4 */
\r
5440 byte DDK5 :1; /* Port K Data Direction Bit 5 */
\r
5442 byte DDK7 :1; /* Port K Data Direction Bit 7 */
\r
5450 extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
\r
5451 #define DDRK _DDRK.Byte
\r
5452 #define DDRK_DDK0 _DDRK.Bits.DDK0
\r
5453 #define DDRK_DDK1 _DDRK.Bits.DDK1
\r
5454 #define DDRK_DDK2 _DDRK.Bits.DDK2
\r
5455 #define DDRK_DDK3 _DDRK.Bits.DDK3
\r
5456 #define DDRK_DDK4 _DDRK.Bits.DDK4
\r
5457 #define DDRK_DDK5 _DDRK.Bits.DDK5
\r
5458 #define DDRK_DDK7 _DDRK.Bits.DDK7
\r
5459 #define DDRK_DDK _DDRK.MergedBits.grpDDK
\r
5462 /*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
\r
5466 byte SYN0 :1; /* CRG Synthesizer Bit 0 */
\r
5467 byte SYN1 :1; /* CRG Synthesizer Bit 1 */
\r
5468 byte SYN2 :1; /* CRG Synthesizer Bit 2 */
\r
5469 byte SYN3 :1; /* CRG Synthesizer Bit 3 */
\r
5470 byte SYN4 :1; /* CRG Synthesizer Bit 4 */
\r
5471 byte SYN5 :1; /* CRG Synthesizer Bit 5 */
\r
5481 extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
\r
5482 #define SYNR _SYNR.Byte
\r
5483 #define SYNR_SYN0 _SYNR.Bits.SYN0
\r
5484 #define SYNR_SYN1 _SYNR.Bits.SYN1
\r
5485 #define SYNR_SYN2 _SYNR.Bits.SYN2
\r
5486 #define SYNR_SYN3 _SYNR.Bits.SYN3
\r
5487 #define SYNR_SYN4 _SYNR.Bits.SYN4
\r
5488 #define SYNR_SYN5 _SYNR.Bits.SYN5
\r
5489 #define SYNR_SYN _SYNR.MergedBits.grpSYN
\r
5492 /*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
\r
5496 byte REFDV0 :1; /* CRG Reference Divider Bit 0 */
\r
5497 byte REFDV1 :1; /* CRG Reference Divider Bit 1 */
\r
5498 byte REFDV2 :1; /* CRG Reference Divider Bit 2 */
\r
5499 byte REFDV3 :1; /* CRG Reference Divider Bit 3 */
\r
5513 extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
\r
5514 #define REFDV _REFDV.Byte
\r
5515 #define REFDV_REFDV0 _REFDV.Bits.REFDV0
\r
5516 #define REFDV_REFDV1 _REFDV.Bits.REFDV1
\r
5517 #define REFDV_REFDV2 _REFDV.Bits.REFDV2
\r
5518 #define REFDV_REFDV3 _REFDV.Bits.REFDV3
\r
5519 #define REFDV_REFDV _REFDV.MergedBits.grpREFDV
\r
5522 /*** CTFLG - CRG Test Flags Register; 0x00000036 ***/
\r
5526 byte TOUT0 :1; /* CRG Test Flags Bit 0 */
\r
5527 byte TOUT1 :1; /* CRG Test Flags Bit 1 */
\r
5528 byte TOUT2 :1; /* CRG Test Flags Bit 2 */
\r
5529 byte TOUT3 :1; /* CRG Test Flags Bit 3 */
\r
5530 byte TOUT4 :1; /* CRG Test Flags Bit 4 */
\r
5531 byte TOUT5 :1; /* CRG Test Flags Bit 5 */
\r
5532 byte TOUT6 :1; /* CRG Test Flags Bit 6 */
\r
5533 byte TOUT7 :1; /* CRG Test Flags Bit 7 */
\r
5539 extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);
\r
5540 #define CTFLG _CTFLG.Byte
\r
5541 #define CTFLG_TOUT0 _CTFLG.Bits.TOUT0
\r
5542 #define CTFLG_TOUT1 _CTFLG.Bits.TOUT1
\r
5543 #define CTFLG_TOUT2 _CTFLG.Bits.TOUT2
\r
5544 #define CTFLG_TOUT3 _CTFLG.Bits.TOUT3
\r
5545 #define CTFLG_TOUT4 _CTFLG.Bits.TOUT4
\r
5546 #define CTFLG_TOUT5 _CTFLG.Bits.TOUT5
\r
5547 #define CTFLG_TOUT6 _CTFLG.Bits.TOUT6
\r
5548 #define CTFLG_TOUT7 _CTFLG.Bits.TOUT7
\r
5549 #define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT
\r
5552 /*** CRGFLG - CRG Flags Register; 0x00000037 ***/
\r
5556 byte SCM :1; /* Self-clock mode Status */
\r
5557 byte SCMIF :1; /* Self-clock mode Interrupt Flag */
\r
5558 byte TRACK :1; /* Track Status */
\r
5559 byte LOCK :1; /* Lock Status */
\r
5560 byte LOCKIF :1; /* PLL Lock Interrupt Flag */
\r
5562 byte PORF :1; /* Power on Reset Flag */
\r
5563 byte RTIF :1; /* Real Time Interrupt Flag */
\r
5566 extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
\r
5567 #define CRGFLG _CRGFLG.Byte
\r
5568 #define CRGFLG_SCM _CRGFLG.Bits.SCM
\r
5569 #define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
\r
5570 #define CRGFLG_TRACK _CRGFLG.Bits.TRACK
\r
5571 #define CRGFLG_LOCK _CRGFLG.Bits.LOCK
\r
5572 #define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
\r
5573 #define CRGFLG_PORF _CRGFLG.Bits.PORF
\r
5574 #define CRGFLG_RTIF _CRGFLG.Bits.RTIF
\r
5577 /*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
\r
5582 byte SCMIE :1; /* Self-clock mode Interrupt Enable */
\r
5585 byte LOCKIE :1; /* Lock Interrupt Enable */
\r
5588 byte RTIE :1; /* Real Time Interrupt Enable */
\r
5591 extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);
\r
5592 #define CRGINT _CRGINT.Byte
\r
5593 #define CRGINT_SCMIE _CRGINT.Bits.SCMIE
\r
5594 #define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE
\r
5595 #define CRGINT_RTIE _CRGINT.Bits.RTIE
\r
5598 /*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/
\r
5602 byte COPWAI :1; /* COP stops in WAIT mode */
\r
5603 byte RTIWAI :1; /* RTI stops in WAIT mode */
\r
5604 byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */
\r
5605 byte PLLWAI :1; /* PLL stops in WAIT mode */
\r
5606 byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */
\r
5607 byte SYSWAI :1; /* System clocks stop in WAIT mode */
\r
5608 byte PSTP :1; /* Pseudo Stop */
\r
5609 byte PLLSEL :1; /* PLL selected for system clock */
\r
5612 extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);
\r
5613 #define CLKSEL _CLKSEL.Byte
\r
5614 #define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI
\r
5615 #define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI
\r
5616 #define CLKSEL_CWAI _CLKSEL.Bits.CWAI
\r
5617 #define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI
\r
5618 #define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI
\r
5619 #define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI
\r
5620 #define CLKSEL_PSTP _CLKSEL.Bits.PSTP
\r
5621 #define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL
\r
5624 /*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/
\r
5628 byte SCME :1; /* Self-clock mode enable */
\r
5632 byte ACQ :1; /* Acquisition */
\r
5633 byte AUTO :1; /* Automatic Bandwidth Control */
\r
5634 byte PLLON :1; /* Phase Lock Loop On */
\r
5635 byte CME :1; /* Crystal Monitor Enable */
\r
5638 extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);
\r
5639 #define PLLCTL _PLLCTL.Byte
\r
5640 #define PLLCTL_SCME _PLLCTL.Bits.SCME
\r
5641 #define PLLCTL_ACQ _PLLCTL.Bits.ACQ
\r
5642 #define PLLCTL_AUTO _PLLCTL.Bits.AUTO
\r
5643 #define PLLCTL_PLLON _PLLCTL.Bits.PLLON
\r
5644 #define PLLCTL_CME _PLLCTL.Bits.CME
\r
5647 /*** RTICTL - CRG RTI Control Register; 0x0000003B ***/
\r
5651 byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */
\r
5652 byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */
\r
5653 byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */
\r
5654 byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */
\r
5655 byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */
\r
5656 byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */
\r
5657 byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */
\r
5665 extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);
\r
5666 #define RTICTL _RTICTL.Byte
\r
5667 #define RTICTL_RTR0 _RTICTL.Bits.RTR0
\r
5668 #define RTICTL_RTR1 _RTICTL.Bits.RTR1
\r
5669 #define RTICTL_RTR2 _RTICTL.Bits.RTR2
\r
5670 #define RTICTL_RTR3 _RTICTL.Bits.RTR3
\r
5671 #define RTICTL_RTR4 _RTICTL.Bits.RTR4
\r
5672 #define RTICTL_RTR5 _RTICTL.Bits.RTR5
\r
5673 #define RTICTL_RTR6 _RTICTL.Bits.RTR6
\r
5674 #define RTICTL_RTR _RTICTL.MergedBits.grpRTR
\r
5677 /*** COPCTL - CRG COP Control Register; 0x0000003C ***/
\r
5681 byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */
\r
5682 byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */
\r
5683 byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */
\r
5687 byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */
\r
5688 byte WCOP :1; /* Window COP mode */
\r
5699 extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);
\r
5700 #define COPCTL _COPCTL.Byte
\r
5701 #define COPCTL_CR0 _COPCTL.Bits.CR0
\r
5702 #define COPCTL_CR1 _COPCTL.Bits.CR1
\r
5703 #define COPCTL_CR2 _COPCTL.Bits.CR2
\r
5704 #define COPCTL_RSBCK _COPCTL.Bits.RSBCK
\r
5705 #define COPCTL_WCOP _COPCTL.Bits.WCOP
\r
5706 #define COPCTL_CR _COPCTL.MergedBits.grpCR
\r
5709 /*** FORBYP - Crg force and bypass test register; 0x0000003D ***/
\r
5713 byte BIT0 :1; /* Bit 0 */
\r
5714 byte BIT1 :1; /* Bit 1 */
\r
5715 byte BIT2 :1; /* Bit 2 */
\r
5716 byte BIT3 :1; /* Bit 3 */
\r
5717 byte BIT4 :1; /* Bit 4 */
\r
5718 byte BIT5 :1; /* Bit 5 */
\r
5719 byte BIT6 :1; /* Bit 6 */
\r
5720 byte BIT7 :1; /* Bit 7 */
\r
5726 extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D);
\r
5727 #define FORBYP _FORBYP.Byte
\r
5728 #define FORBYP_BIT0 _FORBYP.Bits.BIT0
\r
5729 #define FORBYP_BIT1 _FORBYP.Bits.BIT1
\r
5730 #define FORBYP_BIT2 _FORBYP.Bits.BIT2
\r
5731 #define FORBYP_BIT3 _FORBYP.Bits.BIT3
\r
5732 #define FORBYP_BIT4 _FORBYP.Bits.BIT4
\r
5733 #define FORBYP_BIT5 _FORBYP.Bits.BIT5
\r
5734 #define FORBYP_BIT6 _FORBYP.Bits.BIT6
\r
5735 #define FORBYP_BIT7 _FORBYP.Bits.BIT7
\r
5736 #define FORBYP_BIT _FORBYP.MergedBits.grpBIT
\r
5739 /*** CTCTL - CRG Test Control Register; 0x0000003E ***/
\r
5743 byte TCTL0 :1; /* CRG Test Control Bit 0 */
\r
5744 byte TCTL1 :1; /* CRG Test Control Bit 1 */
\r
5745 byte TCTL2 :1; /* CRG Test Control Bit 2 */
\r
5746 byte TCTL3 :1; /* CRG Test Control Bit 3 */
\r
5747 byte TCTL4 :1; /* CRG Test Control Bit 4 */
\r
5748 byte TCTL5 :1; /* CRG Test Control Bit 5 */
\r
5749 byte TCTL6 :1; /* CRG Test Control Bit 6 */
\r
5750 byte TCTL7 :1; /* CRG Test Control Bit 7 */
\r
5756 extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);
\r
5757 #define CTCTL _CTCTL.Byte
\r
5758 #define CTCTL_TCTL0 _CTCTL.Bits.TCTL0
\r
5759 #define CTCTL_TCTL1 _CTCTL.Bits.TCTL1
\r
5760 #define CTCTL_TCTL2 _CTCTL.Bits.TCTL2
\r
5761 #define CTCTL_TCTL3 _CTCTL.Bits.TCTL3
\r
5762 #define CTCTL_TCTL4 _CTCTL.Bits.TCTL4
\r
5763 #define CTCTL_TCTL5 _CTCTL.Bits.TCTL5
\r
5764 #define CTCTL_TCTL6 _CTCTL.Bits.TCTL6
\r
5765 #define CTCTL_TCTL7 _CTCTL.Bits.TCTL7
\r
5766 #define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL
\r
5769 /*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/
\r
5773 byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */
\r
5774 byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */
\r
5775 byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */
\r
5776 byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */
\r
5777 byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */
\r
5778 byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */
\r
5779 byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */
\r
5780 byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */
\r
5786 extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);
\r
5787 #define ARMCOP _ARMCOP.Byte
\r
5788 #define ARMCOP_BIT0 _ARMCOP.Bits.BIT0
\r
5789 #define ARMCOP_BIT1 _ARMCOP.Bits.BIT1
\r
5790 #define ARMCOP_BIT2 _ARMCOP.Bits.BIT2
\r
5791 #define ARMCOP_BIT3 _ARMCOP.Bits.BIT3
\r
5792 #define ARMCOP_BIT4 _ARMCOP.Bits.BIT4
\r
5793 #define ARMCOP_BIT5 _ARMCOP.Bits.BIT5
\r
5794 #define ARMCOP_BIT6 _ARMCOP.Bits.BIT6
\r
5795 #define ARMCOP_BIT7 _ARMCOP.Bits.BIT7
\r
5796 #define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT
\r
5799 /*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/
\r
5803 byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */
\r
5804 byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */
\r
5805 byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */
\r
5806 byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */
\r
5807 byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */
\r
5808 byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */
\r
5809 byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */
\r
5810 byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */
\r
5816 extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);
\r
5817 #define TIOS _TIOS.Byte
\r
5818 #define TIOS_IOS0 _TIOS.Bits.IOS0
\r
5819 #define TIOS_IOS1 _TIOS.Bits.IOS1
\r
5820 #define TIOS_IOS2 _TIOS.Bits.IOS2
\r
5821 #define TIOS_IOS3 _TIOS.Bits.IOS3
\r
5822 #define TIOS_IOS4 _TIOS.Bits.IOS4
\r
5823 #define TIOS_IOS5 _TIOS.Bits.IOS5
\r
5824 #define TIOS_IOS6 _TIOS.Bits.IOS6
\r
5825 #define TIOS_IOS7 _TIOS.Bits.IOS7
\r
5826 #define TIOS_IOS _TIOS.MergedBits.grpIOS
\r
5829 /*** CFORC - Timer Compare Force Register; 0x00000041 ***/
\r
5833 byte FOC0 :1; /* Force Output Compare Action for Channel 0 */
\r
5834 byte FOC1 :1; /* Force Output Compare Action for Channel 1 */
\r
5835 byte FOC2 :1; /* Force Output Compare Action for Channel 2 */
\r
5836 byte FOC3 :1; /* Force Output Compare Action for Channel 3 */
\r
5837 byte FOC4 :1; /* Force Output Compare Action for Channel 4 */
\r
5838 byte FOC5 :1; /* Force Output Compare Action for Channel 5 */
\r
5839 byte FOC6 :1; /* Force Output Compare Action for Channel 6 */
\r
5840 byte FOC7 :1; /* Force Output Compare Action for Channel 7 */
\r
5846 extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);
\r
5847 #define CFORC _CFORC.Byte
\r
5848 #define CFORC_FOC0 _CFORC.Bits.FOC0
\r
5849 #define CFORC_FOC1 _CFORC.Bits.FOC1
\r
5850 #define CFORC_FOC2 _CFORC.Bits.FOC2
\r
5851 #define CFORC_FOC3 _CFORC.Bits.FOC3
\r
5852 #define CFORC_FOC4 _CFORC.Bits.FOC4
\r
5853 #define CFORC_FOC5 _CFORC.Bits.FOC5
\r
5854 #define CFORC_FOC6 _CFORC.Bits.FOC6
\r
5855 #define CFORC_FOC7 _CFORC.Bits.FOC7
\r
5856 #define CFORC_FOC _CFORC.MergedBits.grpFOC
\r
5859 /*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/
\r
5863 byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */
\r
5864 byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */
\r
5865 byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */
\r
5866 byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */
\r
5867 byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */
\r
5868 byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */
\r
5869 byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */
\r
5870 byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */
\r
5876 extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);
\r
5877 #define OC7M _OC7M.Byte
\r
5878 #define OC7M_OC7M0 _OC7M.Bits.OC7M0
\r
5879 #define OC7M_OC7M1 _OC7M.Bits.OC7M1
\r
5880 #define OC7M_OC7M2 _OC7M.Bits.OC7M2
\r
5881 #define OC7M_OC7M3 _OC7M.Bits.OC7M3
\r
5882 #define OC7M_OC7M4 _OC7M.Bits.OC7M4
\r
5883 #define OC7M_OC7M5 _OC7M.Bits.OC7M5
\r
5884 #define OC7M_OC7M6 _OC7M.Bits.OC7M6
\r
5885 #define OC7M_OC7M7 _OC7M.Bits.OC7M7
\r
5886 #define OC7M_OC7M _OC7M.MergedBits.grpOC7M
\r
5889 /*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/
\r
5896 extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);
\r
5897 #define OC7D _OC7D.Byte
\r
5898 #define OC7D_OC7D _OC7D.MergedBits.grpOC7D
\r
5901 /*** TSCR1 - Timer System Control Register1; 0x00000046 ***/
\r
5909 byte TFFCA :1; /* Timer Fast Flag Clear All */
\r
5910 byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */
\r
5911 byte TSWAI :1; /* Timer Module Stops While in Wait */
\r
5912 byte TEN :1; /* Timer Enable */
\r
5915 extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);
\r
5916 #define TSCR1 _TSCR1.Byte
\r
5917 #define TSCR1_TFFCA _TSCR1.Bits.TFFCA
\r
5918 #define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ
\r
5919 #define TSCR1_TSWAI _TSCR1.Bits.TSWAI
\r
5920 #define TSCR1_TEN _TSCR1.Bits.TEN
\r
5923 /*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/
\r
5927 byte TOV0 :1; /* Toggle On Overflow Bit 0 */
\r
5928 byte TOV1 :1; /* Toggle On Overflow Bit 1 */
\r
5929 byte TOV2 :1; /* Toggle On Overflow Bit 2 */
\r
5930 byte TOV3 :1; /* Toggle On Overflow Bit 3 */
\r
5931 byte TOV4 :1; /* Toggle On Overflow Bit 4 */
\r
5932 byte TOV5 :1; /* Toggle On Overflow Bit 5 */
\r
5933 byte TOV6 :1; /* Toggle On Overflow Bit 6 */
\r
5934 byte TOV7 :1; /* Toggle On Overflow Bit 7 */
\r
5940 extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);
\r
5941 #define TTOV _TTOV.Byte
\r
5942 #define TTOV_TOV0 _TTOV.Bits.TOV0
\r
5943 #define TTOV_TOV1 _TTOV.Bits.TOV1
\r
5944 #define TTOV_TOV2 _TTOV.Bits.TOV2
\r
5945 #define TTOV_TOV3 _TTOV.Bits.TOV3
\r
5946 #define TTOV_TOV4 _TTOV.Bits.TOV4
\r
5947 #define TTOV_TOV5 _TTOV.Bits.TOV5
\r
5948 #define TTOV_TOV6 _TTOV.Bits.TOV6
\r
5949 #define TTOV_TOV7 _TTOV.Bits.TOV7
\r
5950 #define TTOV_TOV _TTOV.MergedBits.grpTOV
\r
5953 /*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/
\r
5957 byte OL4 :1; /* Output Level Bit 4 */
\r
5958 byte OM4 :1; /* Output Mode Bit 4 */
\r
5959 byte OL5 :1; /* Output Level Bit 5 */
\r
5960 byte OM5 :1; /* Output Mode Bit 5 */
\r
5961 byte OL6 :1; /* Output Level Bit 6 */
\r
5962 byte OM6 :1; /* Output Mode Bit 6 */
\r
5963 byte OL7 :1; /* Output Level Bit 7 */
\r
5964 byte OM7 :1; /* Output Mode Bit 7 */
\r
5967 extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);
\r
5968 #define TCTL1 _TCTL1.Byte
\r
5969 #define TCTL1_OL4 _TCTL1.Bits.OL4
\r
5970 #define TCTL1_OM4 _TCTL1.Bits.OM4
\r
5971 #define TCTL1_OL5 _TCTL1.Bits.OL5
\r
5972 #define TCTL1_OM5 _TCTL1.Bits.OM5
\r
5973 #define TCTL1_OL6 _TCTL1.Bits.OL6
\r
5974 #define TCTL1_OM6 _TCTL1.Bits.OM6
\r
5975 #define TCTL1_OL7 _TCTL1.Bits.OL7
\r
5976 #define TCTL1_OM7 _TCTL1.Bits.OM7
\r
5979 /*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/
\r
5983 byte OL0 :1; /* Output Level Bit 0 */
\r
5984 byte OM0 :1; /* Output Mode Bit 0 */
\r
5985 byte OL1 :1; /* Output Level Bit 1 */
\r
5986 byte OM1 :1; /* Output Mode Bit 1 */
\r
5987 byte OL2 :1; /* Output Level Bit 2 */
\r
5988 byte OM2 :1; /* Output Mode Bit 2 */
\r
5989 byte OL3 :1; /* Output Level Bit 3 */
\r
5990 byte OM3 :1; /* Output Mode Bit 3 */
\r
5993 extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);
\r
5994 #define TCTL2 _TCTL2.Byte
\r
5995 #define TCTL2_OL0 _TCTL2.Bits.OL0
\r
5996 #define TCTL2_OM0 _TCTL2.Bits.OM0
\r
5997 #define TCTL2_OL1 _TCTL2.Bits.OL1
\r
5998 #define TCTL2_OM1 _TCTL2.Bits.OM1
\r
5999 #define TCTL2_OL2 _TCTL2.Bits.OL2
\r
6000 #define TCTL2_OM2 _TCTL2.Bits.OM2
\r
6001 #define TCTL2_OL3 _TCTL2.Bits.OL3
\r
6002 #define TCTL2_OM3 _TCTL2.Bits.OM3
\r
6005 /*** TCTL3 - Timer Control Register 3; 0x0000004A ***/
\r
6009 byte EDG4A :1; /* Input Capture Edge Control 4A */
\r
6010 byte EDG4B :1; /* Input Capture Edge Control 4B */
\r
6011 byte EDG5A :1; /* Input Capture Edge Control 5A */
\r
6012 byte EDG5B :1; /* Input Capture Edge Control 5B */
\r
6013 byte EDG6A :1; /* Input Capture Edge Control 6A */
\r
6014 byte EDG6B :1; /* Input Capture Edge Control 6B */
\r
6015 byte EDG7A :1; /* Input Capture Edge Control 7A */
\r
6016 byte EDG7B :1; /* Input Capture Edge Control 7B */
\r
6019 extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);
\r
6020 #define TCTL3 _TCTL3.Byte
\r
6021 #define TCTL3_EDG4A _TCTL3.Bits.EDG4A
\r
6022 #define TCTL3_EDG4B _TCTL3.Bits.EDG4B
\r
6023 #define TCTL3_EDG5A _TCTL3.Bits.EDG5A
\r
6024 #define TCTL3_EDG5B _TCTL3.Bits.EDG5B
\r
6025 #define TCTL3_EDG6A _TCTL3.Bits.EDG6A
\r
6026 #define TCTL3_EDG6B _TCTL3.Bits.EDG6B
\r
6027 #define TCTL3_EDG7A _TCTL3.Bits.EDG7A
\r
6028 #define TCTL3_EDG7B _TCTL3.Bits.EDG7B
\r
6031 /*** TCTL4 - Timer Control Register 4; 0x0000004B ***/
\r
6035 byte EDG0A :1; /* Input Capture Edge Control 0A */
\r
6036 byte EDG0B :1; /* Input Capture Edge Control 0B */
\r
6037 byte EDG1A :1; /* Input Capture Edge Control 1A */
\r
6038 byte EDG1B :1; /* Input Capture Edge Control 1B */
\r
6039 byte EDG2A :1; /* Input Capture Edge Control 2A */
\r
6040 byte EDG2B :1; /* Input Capture Edge Control 2B */
\r
6041 byte EDG3A :1; /* Input Capture Edge Control 3A */
\r
6042 byte EDG3B :1; /* Input Capture Edge Control 3B */
\r
6045 extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);
\r
6046 #define TCTL4 _TCTL4.Byte
\r
6047 #define TCTL4_EDG0A _TCTL4.Bits.EDG0A
\r
6048 #define TCTL4_EDG0B _TCTL4.Bits.EDG0B
\r
6049 #define TCTL4_EDG1A _TCTL4.Bits.EDG1A
\r
6050 #define TCTL4_EDG1B _TCTL4.Bits.EDG1B
\r
6051 #define TCTL4_EDG2A _TCTL4.Bits.EDG2A
\r
6052 #define TCTL4_EDG2B _TCTL4.Bits.EDG2B
\r
6053 #define TCTL4_EDG3A _TCTL4.Bits.EDG3A
\r
6054 #define TCTL4_EDG3B _TCTL4.Bits.EDG3B
\r
6057 /*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/
\r
6061 byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */
\r
6062 byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */
\r
6063 byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */
\r
6064 byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */
\r
6065 byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */
\r
6066 byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */
\r
6067 byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */
\r
6068 byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */
\r
6071 extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);
\r
6072 #define TIE _TIE.Byte
\r
6073 #define TIE_C0I _TIE.Bits.C0I
\r
6074 #define TIE_C1I _TIE.Bits.C1I
\r
6075 #define TIE_C2I _TIE.Bits.C2I
\r
6076 #define TIE_C3I _TIE.Bits.C3I
\r
6077 #define TIE_C4I _TIE.Bits.C4I
\r
6078 #define TIE_C5I _TIE.Bits.C5I
\r
6079 #define TIE_C6I _TIE.Bits.C6I
\r
6080 #define TIE_C7I _TIE.Bits.C7I
\r
6083 /*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/
\r
6087 byte PR0 :1; /* Timer Prescaler Select Bit 0 */
\r
6088 byte PR1 :1; /* Timer Prescaler Select Bit 1 */
\r
6089 byte PR2 :1; /* Timer Prescaler Select Bit 2 */
\r
6090 byte TCRE :1; /* Timer Counter Reset Enable */
\r
6094 byte TOI :1; /* Timer Overflow Interrupt Enable */
\r
6105 extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);
\r
6106 #define TSCR2 _TSCR2.Byte
\r
6107 #define TSCR2_PR0 _TSCR2.Bits.PR0
\r
6108 #define TSCR2_PR1 _TSCR2.Bits.PR1
\r
6109 #define TSCR2_PR2 _TSCR2.Bits.PR2
\r
6110 #define TSCR2_TCRE _TSCR2.Bits.TCRE
\r
6111 #define TSCR2_TOI _TSCR2.Bits.TOI
\r
6112 #define TSCR2_PR _TSCR2.MergedBits.grpPR
\r
6115 /*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/
\r
6119 byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */
\r
6120 byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */
\r
6121 byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */
\r
6122 byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */
\r
6123 byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */
\r
6124 byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */
\r
6125 byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */
\r
6126 byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */
\r
6129 extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);
\r
6130 #define TFLG1 _TFLG1.Byte
\r
6131 #define TFLG1_C0F _TFLG1.Bits.C0F
\r
6132 #define TFLG1_C1F _TFLG1.Bits.C1F
\r
6133 #define TFLG1_C2F _TFLG1.Bits.C2F
\r
6134 #define TFLG1_C3F _TFLG1.Bits.C3F
\r
6135 #define TFLG1_C4F _TFLG1.Bits.C4F
\r
6136 #define TFLG1_C5F _TFLG1.Bits.C5F
\r
6137 #define TFLG1_C6F _TFLG1.Bits.C6F
\r
6138 #define TFLG1_C7F _TFLG1.Bits.C7F
\r
6141 /*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/
\r
6152 byte TOF :1; /* Timer Overflow Flag */
\r
6155 extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);
\r
6156 #define TFLG2 _TFLG2.Byte
\r
6157 #define TFLG2_TOF _TFLG2.Bits.TOF
\r
6160 /*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/
\r
6164 byte PAI :1; /* Pulse Accumulator Input Interrupt enable */
\r
6165 byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */
\r
6166 byte CLK0 :1; /* Clock Select Bit 0 */
\r
6167 byte CLK1 :1; /* Clock Select Bit 1 */
\r
6168 byte PEDGE :1; /* Pulse Accumulator Edge Control */
\r
6169 byte PAMOD :1; /* Pulse Accumulator Mode */
\r
6170 byte PAEN :1; /* Pulse Accumulator A System Enable */
\r
6183 extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);
\r
6184 #define PACTL _PACTL.Byte
\r
6185 #define PACTL_PAI _PACTL.Bits.PAI
\r
6186 #define PACTL_PAOVI _PACTL.Bits.PAOVI
\r
6187 #define PACTL_CLK0 _PACTL.Bits.CLK0
\r
6188 #define PACTL_CLK1 _PACTL.Bits.CLK1
\r
6189 #define PACTL_PEDGE _PACTL.Bits.PEDGE
\r
6190 #define PACTL_PAMOD _PACTL.Bits.PAMOD
\r
6191 #define PACTL_PAEN _PACTL.Bits.PAEN
\r
6192 #define PACTL_CLK _PACTL.MergedBits.grpCLK
\r
6195 /*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/
\r
6199 byte PAIF :1; /* Pulse Accumulator Input edge Flag */
\r
6200 byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */
\r
6209 extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);
\r
6210 #define PAFLG _PAFLG.Byte
\r
6211 #define PAFLG_PAIF _PAFLG.Bits.PAIF
\r
6212 #define PAFLG_PAOVF _PAFLG.Bits.PAOVF
\r
6215 /*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/
\r
6219 byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */
\r
6220 byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */
\r
6221 byte MCEN :1; /* Modulus Down-Counter Enable */
\r
6222 byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */
\r
6223 byte ICLAT :1; /* Input Capture Force Latch Action */
\r
6224 byte RDMCL :1; /* Read Modulus Down-Counter Load */
\r
6225 byte MODMC :1; /* Modulus Mode Enable */
\r
6226 byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */
\r
6238 extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066);
\r
6239 #define MCCTL _MCCTL.Byte
\r
6240 #define MCCTL_MCPR0 _MCCTL.Bits.MCPR0
\r
6241 #define MCCTL_MCPR1 _MCCTL.Bits.MCPR1
\r
6242 #define MCCTL_MCEN _MCCTL.Bits.MCEN
\r
6243 #define MCCTL_FLMC _MCCTL.Bits.FLMC
\r
6244 #define MCCTL_ICLAT _MCCTL.Bits.ICLAT
\r
6245 #define MCCTL_RDMCL _MCCTL.Bits.RDMCL
\r
6246 #define MCCTL_MODMC _MCCTL.Bits.MODMC
\r
6247 #define MCCTL_MCZI _MCCTL.Bits.MCZI
\r
6248 #define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR
\r
6251 /*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/
\r
6255 byte POLF0 :1; /* First Input Capture Polarity Status 0 */
\r
6256 byte POLF1 :1; /* First Input Capture Polarity Status 1 */
\r
6257 byte POLF2 :1; /* First Input Capture Polarity Status 2 */
\r
6258 byte POLF3 :1; /* First Input Capture Polarity Status 3 */
\r
6262 byte MCZF :1; /* Modulus Counter Underflow Flag */
\r
6272 extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067);
\r
6273 #define MCFLG _MCFLG.Byte
\r
6274 #define MCFLG_POLF0 _MCFLG.Bits.POLF0
\r
6275 #define MCFLG_POLF1 _MCFLG.Bits.POLF1
\r
6276 #define MCFLG_POLF2 _MCFLG.Bits.POLF2
\r
6277 #define MCFLG_POLF3 _MCFLG.Bits.POLF3
\r
6278 #define MCFLG_MCZF _MCFLG.Bits.MCZF
\r
6279 #define MCFLG_POLF _MCFLG.MergedBits.grpPOLF
\r
6282 /*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/
\r
6286 byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */
\r
6287 byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */
\r
6288 byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */
\r
6289 byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */
\r
6296 extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068);
\r
6297 #define ICPAR _ICPAR.Byte
\r
6298 #define ICPAR_PA0EN _ICPAR.Bits.PA0EN
\r
6299 #define ICPAR_PA1EN _ICPAR.Bits.PA1EN
\r
6300 #define ICPAR_PA2EN _ICPAR.Bits.PA2EN
\r
6301 #define ICPAR_PA3EN _ICPAR.Bits.PA3EN
\r
6304 /*** DLYCT - Delay Counter Control Register; 0x00000069 ***/
\r
6308 byte DLY0 :1; /* Delay Counter Select 0 */
\r
6309 byte DLY1 :1; /* Delay Counter Select 1 */
\r
6327 extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069);
\r
6328 #define DLYCT _DLYCT.Byte
\r
6329 #define DLYCT_DLY0 _DLYCT.Bits.DLY0
\r
6330 #define DLYCT_DLY1 _DLYCT.Bits.DLY1
\r
6331 #define DLYCT_DLY _DLYCT.MergedBits.grpDLY
\r
6334 /*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/
\r
6338 byte NOVW0 :1; /* No Input Capture Overwrite 0 */
\r
6339 byte NOVW1 :1; /* No Input Capture Overwrite 1 */
\r
6340 byte NOVW2 :1; /* No Input Capture Overwrite 2 */
\r
6341 byte NOVW3 :1; /* No Input Capture Overwrite 3 */
\r
6342 byte NOVW4 :1; /* No Input Capture Overwrite 4 */
\r
6343 byte NOVW5 :1; /* No Input Capture Overwrite 5 */
\r
6344 byte NOVW6 :1; /* No Input Capture Overwrite 6 */
\r
6345 byte NOVW7 :1; /* No Input Capture Overwrite 7 */
\r
6351 extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A);
\r
6352 #define ICOVW _ICOVW.Byte
\r
6353 #define ICOVW_NOVW0 _ICOVW.Bits.NOVW0
\r
6354 #define ICOVW_NOVW1 _ICOVW.Bits.NOVW1
\r
6355 #define ICOVW_NOVW2 _ICOVW.Bits.NOVW2
\r
6356 #define ICOVW_NOVW3 _ICOVW.Bits.NOVW3
\r
6357 #define ICOVW_NOVW4 _ICOVW.Bits.NOVW4
\r
6358 #define ICOVW_NOVW5 _ICOVW.Bits.NOVW5
\r
6359 #define ICOVW_NOVW6 _ICOVW.Bits.NOVW6
\r
6360 #define ICOVW_NOVW7 _ICOVW.Bits.NOVW7
\r
6361 #define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW
\r
6364 /*** ICSYS - Input Control System Control Register; 0x0000006B ***/
\r
6368 byte LATQ :1; /* Input Control Latch or Queue Mode Enable */
\r
6369 byte BUFEN :1; /* IC Buffer Enable */
\r
6370 byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */
\r
6371 byte TFMOD :1; /* Timer Flag-setting Mode */
\r
6372 byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */
\r
6373 byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */
\r
6374 byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */
\r
6375 byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */
\r
6378 extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B);
\r
6379 #define ICSYS _ICSYS.Byte
\r
6380 #define ICSYS_LATQ _ICSYS.Bits.LATQ
\r
6381 #define ICSYS_BUFEN _ICSYS.Bits.BUFEN
\r
6382 #define ICSYS_PACMX _ICSYS.Bits.PACMX
\r
6383 #define ICSYS_TFMOD _ICSYS.Bits.TFMOD
\r
6384 #define ICSYS_SH04 _ICSYS.Bits.SH04
\r
6385 #define ICSYS_SH15 _ICSYS.Bits.SH15
\r
6386 #define ICSYS_SH26 _ICSYS.Bits.SH26
\r
6387 #define ICSYS_SH37 _ICSYS.Bits.SH37
\r
6390 /*** TIMTST - Timer Test Register; 0x0000006D ***/
\r
6395 byte TCBYP :1; /* Main Timer Divider Chain Bypass */
\r
6404 extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D);
\r
6405 #define TIMTST _TIMTST.Byte
\r
6406 #define TIMTST_TCBYP _TIMTST.Bits.TCBYP
\r
6409 /*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/
\r
6414 byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */
\r
6419 byte PBEN :1; /* Pulse Accumulator B System Enable */
\r
6423 extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070);
\r
6424 #define PBCTL _PBCTL.Byte
\r
6425 #define PBCTL_PBOVI _PBCTL.Bits.PBOVI
\r
6426 #define PBCTL_PBEN _PBCTL.Bits.PBEN
\r
6429 /*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/
\r
6434 byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */
\r
6443 extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071);
\r
6444 #define PBFLG _PBFLG.Byte
\r
6445 #define PBFLG_PBOVF _PBFLG.Bits.PBOVF
\r
6448 /*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/
\r
6452 byte CC0 :1; /* Conversion Counter 0 */
\r
6453 byte CC1 :1; /* Conversion Counter 1 */
\r
6454 byte CC2 :1; /* Conversion Counter 2 */
\r
6456 byte FIFOR :1; /* FIFO Over Run Flag */
\r
6457 byte ETORF :1; /* External Trigger Overrun Flag */
\r
6459 byte SCF :1; /* Sequence Complete Flag */
\r
6470 extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086);
\r
6471 #define ATD0STAT0 _ATD0STAT0.Byte
\r
6472 #define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0
\r
6473 #define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1
\r
6474 #define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2
\r
6475 #define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR
\r
6476 #define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF
\r
6477 #define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF
\r
6478 #define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC
\r
6481 /*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/
\r
6485 byte CCF0 :1; /* Conversion Complete Flag 0 */
\r
6486 byte CCF1 :1; /* Conversion Complete Flag 1 */
\r
6487 byte CCF2 :1; /* Conversion Complete Flag 2 */
\r
6488 byte CCF3 :1; /* Conversion Complete Flag 3 */
\r
6489 byte CCF4 :1; /* Conversion Complete Flag 4 */
\r
6490 byte CCF5 :1; /* Conversion Complete Flag 5 */
\r
6491 byte CCF6 :1; /* Conversion Complete Flag 6 */
\r
6492 byte CCF7 :1; /* Conversion Complete Flag 7 */
\r
6498 extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B);
\r
6499 #define ATD0STAT1 _ATD0STAT1.Byte
\r
6500 #define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0
\r
6501 #define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1
\r
6502 #define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2
\r
6503 #define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3
\r
6504 #define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4
\r
6505 #define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5
\r
6506 #define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6
\r
6507 #define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7
\r
6508 #define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF
\r
6511 /*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/
\r
6515 byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */
\r
6516 byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */
\r
6517 byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */
\r
6518 byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */
\r
6519 byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */
\r
6520 byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */
\r
6521 byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */
\r
6522 byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */
\r
6528 extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D);
\r
6529 #define ATD0DIEN _ATD0DIEN.Byte
\r
6530 #define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0
\r
6531 #define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1
\r
6532 #define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2
\r
6533 #define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3
\r
6534 #define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4
\r
6535 #define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5
\r
6536 #define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6
\r
6537 #define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7
\r
6538 #define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT
\r
6541 /*** PORTAD0 - Port AD0 Register; 0x0000008F ***/
\r
6545 byte BIT0 :1; /* AN0 */
\r
6546 byte BIT1 :1; /* AN1 */
\r
6547 byte BIT2 :1; /* AN2 */
\r
6548 byte BIT3 :1; /* AN3 */
\r
6549 byte BIT4 :1; /* AN4 */
\r
6550 byte BIT5 :1; /* AN5 */
\r
6551 byte BIT6 :1; /* AN6 */
\r
6552 byte BIT7 :1; /* AN7 */
\r
6558 extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);
\r
6559 #define PORTAD0 _PORTAD0.Byte
\r
6560 #define PORTAD0_BIT0 _PORTAD0.Bits.BIT0
\r
6561 #define PORTAD0_BIT1 _PORTAD0.Bits.BIT1
\r
6562 #define PORTAD0_BIT2 _PORTAD0.Bits.BIT2
\r
6563 #define PORTAD0_BIT3 _PORTAD0.Bits.BIT3
\r
6564 #define PORTAD0_BIT4 _PORTAD0.Bits.BIT4
\r
6565 #define PORTAD0_BIT5 _PORTAD0.Bits.BIT5
\r
6566 #define PORTAD0_BIT6 _PORTAD0.Bits.BIT6
\r
6567 #define PORTAD0_BIT7 _PORTAD0.Bits.BIT7
\r
6568 #define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT
\r
6571 /*** PWME - PWM Enable Register; 0x000000A0 ***/
\r
6575 byte PWME0 :1; /* Pulse Width Channel 0 Enable */
\r
6576 byte PWME1 :1; /* Pulse Width Channel 1 Enable */
\r
6577 byte PWME2 :1; /* Pulse Width Channel 2 Enable */
\r
6578 byte PWME3 :1; /* Pulse Width Channel 3 Enable */
\r
6579 byte PWME4 :1; /* Pulse Width Channel 4 Enable */
\r
6580 byte PWME5 :1; /* Pulse Width Channel 5 Enable */
\r
6581 byte PWME6 :1; /* Pulse Width Channel 6 Enable */
\r
6582 byte PWME7 :1; /* Pulse Width Channel 7 Enable */
\r
6588 extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0);
\r
6589 #define PWME _PWME.Byte
\r
6590 #define PWME_PWME0 _PWME.Bits.PWME0
\r
6591 #define PWME_PWME1 _PWME.Bits.PWME1
\r
6592 #define PWME_PWME2 _PWME.Bits.PWME2
\r
6593 #define PWME_PWME3 _PWME.Bits.PWME3
\r
6594 #define PWME_PWME4 _PWME.Bits.PWME4
\r
6595 #define PWME_PWME5 _PWME.Bits.PWME5
\r
6596 #define PWME_PWME6 _PWME.Bits.PWME6
\r
6597 #define PWME_PWME7 _PWME.Bits.PWME7
\r
6598 #define PWME_PWME _PWME.MergedBits.grpPWME
\r
6601 /*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/
\r
6605 byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */
\r
6606 byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */
\r
6607 byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */
\r
6608 byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */
\r
6609 byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */
\r
6610 byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */
\r
6611 byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */
\r
6612 byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */
\r
6618 extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1);
\r
6619 #define PWMPOL _PWMPOL.Byte
\r
6620 #define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0
\r
6621 #define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1
\r
6622 #define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2
\r
6623 #define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3
\r
6624 #define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4
\r
6625 #define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5
\r
6626 #define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6
\r
6627 #define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7
\r
6628 #define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL
\r
6631 /*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/
\r
6635 byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */
\r
6636 byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */
\r
6637 byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */
\r
6638 byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */
\r
6639 byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */
\r
6640 byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */
\r
6641 byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */
\r
6642 byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */
\r
6648 extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2);
\r
6649 #define PWMCLK _PWMCLK.Byte
\r
6650 #define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0
\r
6651 #define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1
\r
6652 #define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2
\r
6653 #define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3
\r
6654 #define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4
\r
6655 #define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5
\r
6656 #define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6
\r
6657 #define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7
\r
6658 #define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK
\r
6661 /*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/
\r
6665 byte PCKA0 :1; /* Prescaler Select for Clock A 0 */
\r
6666 byte PCKA1 :1; /* Prescaler Select for Clock A 1 */
\r
6667 byte PCKA2 :1; /* Prescaler Select for Clock A 2 */
\r
6669 byte PCKB0 :1; /* Prescaler Select for Clock B 0 */
\r
6670 byte PCKB1 :1; /* Prescaler Select for Clock B 1 */
\r
6671 byte PCKB2 :1; /* Prescaler Select for Clock B 2 */
\r
6681 extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3);
\r
6682 #define PWMPRCLK _PWMPRCLK.Byte
\r
6683 #define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0
\r
6684 #define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1
\r
6685 #define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2
\r
6686 #define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0
\r
6687 #define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1
\r
6688 #define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2
\r
6689 #define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA
\r
6690 #define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB
\r
6693 /*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/
\r
6697 byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */
\r
6698 byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */
\r
6699 byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */
\r
6700 byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */
\r
6701 byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */
\r
6702 byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */
\r
6703 byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */
\r
6704 byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */
\r
6710 extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4);
\r
6711 #define PWMCAE _PWMCAE.Byte
\r
6712 #define PWMCAE_CAE0 _PWMCAE.Bits.CAE0
\r
6713 #define PWMCAE_CAE1 _PWMCAE.Bits.CAE1
\r
6714 #define PWMCAE_CAE2 _PWMCAE.Bits.CAE2
\r
6715 #define PWMCAE_CAE3 _PWMCAE.Bits.CAE3
\r
6716 #define PWMCAE_CAE4 _PWMCAE.Bits.CAE4
\r
6717 #define PWMCAE_CAE5 _PWMCAE.Bits.CAE5
\r
6718 #define PWMCAE_CAE6 _PWMCAE.Bits.CAE6
\r
6719 #define PWMCAE_CAE7 _PWMCAE.Bits.CAE7
\r
6720 #define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE
\r
6723 /*** PWMCTL - PWM Control Register; 0x000000A5 ***/
\r
6729 byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */
\r
6730 byte PSWAI :1; /* PWM Stops in Wait Mode */
\r
6731 byte CON01 :1; /* Concatenate channels 0 and 1 */
\r
6732 byte CON23 :1; /* Concatenate channels 2 and 3 */
\r
6733 byte CON45 :1; /* Concatenate channels 4 and 5 */
\r
6734 byte CON67 :1; /* Concatenate channels 6 and 7 */
\r
6737 extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5);
\r
6738 #define PWMCTL _PWMCTL.Byte
\r
6739 #define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ
\r
6740 #define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI
\r
6741 #define PWMCTL_CON01 _PWMCTL.Bits.CON01
\r
6742 #define PWMCTL_CON23 _PWMCTL.Bits.CON23
\r
6743 #define PWMCTL_CON45 _PWMCTL.Bits.CON45
\r
6744 #define PWMCTL_CON67 _PWMCTL.Bits.CON67
\r
6747 /*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/
\r
6751 byte BIT0 :1; /* PWM Scale A Bit 0 */
\r
6752 byte BIT1 :1; /* PWM Scale A Bit 1 */
\r
6753 byte BIT2 :1; /* PWM Scale A Bit 2 */
\r
6754 byte BIT3 :1; /* PWM Scale A Bit 3 */
\r
6755 byte BIT4 :1; /* PWM Scale A Bit 4 */
\r
6756 byte BIT5 :1; /* PWM Scale A Bit 5 */
\r
6757 byte BIT6 :1; /* PWM Scale A Bit 6 */
\r
6758 byte BIT7 :1; /* PWM Scale A Bit 7 */
\r
6764 extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8);
\r
6765 #define PWMSCLA _PWMSCLA.Byte
\r
6766 #define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0
\r
6767 #define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1
\r
6768 #define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2
\r
6769 #define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3
\r
6770 #define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4
\r
6771 #define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5
\r
6772 #define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6
\r
6773 #define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7
\r
6774 #define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT
\r
6777 /*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/
\r
6781 byte BIT0 :1; /* PWM Scale B Bit 0 */
\r
6782 byte BIT1 :1; /* PWM Scale B Bit 1 */
\r
6783 byte BIT2 :1; /* PWM Scale B Bit 2 */
\r
6784 byte BIT3 :1; /* PWM Scale B Bit 3 */
\r
6785 byte BIT4 :1; /* PWM Scale B Bit 4 */
\r
6786 byte BIT5 :1; /* PWM Scale B Bit 5 */
\r
6787 byte BIT6 :1; /* PWM Scale B Bit 6 */
\r
6788 byte BIT7 :1; /* PWM Scale B Bit 7 */
\r
6794 extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9);
\r
6795 #define PWMSCLB _PWMSCLB.Byte
\r
6796 #define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0
\r
6797 #define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1
\r
6798 #define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2
\r
6799 #define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3
\r
6800 #define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4
\r
6801 #define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5
\r
6802 #define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6
\r
6803 #define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7
\r
6804 #define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT
\r
6807 /*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/
\r
6811 byte PWM7ENA :1; /* PWM emergency shutdown Enable */
\r
6812 byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */
\r
6813 byte PWM7IN :1; /* PWM channel 7 input status */
\r
6815 byte PWMLVL :1; /* PWM shutdown output Level */
\r
6816 byte PWMRSTRT :1; /* PWM Restart */
\r
6817 byte PWMIE :1; /* PWM Interrupt Enable */
\r
6818 byte PWMIF :1; /* PWM Interrupt Flag */
\r
6821 extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4);
\r
6822 #define PWMSDN _PWMSDN.Byte
\r
6823 #define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA
\r
6824 #define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL
\r
6825 #define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN
\r
6826 #define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL
\r
6827 #define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT
\r
6828 #define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE
\r
6829 #define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF
\r
6832 /*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/
\r
6836 byte PT :1; /* Parity Type Bit */
\r
6837 byte PE :1; /* Parity Enable Bit */
\r
6838 byte ILT :1; /* Idle Line Type Bit */
\r
6839 byte WAKE :1; /* Wakeup Condition Bit */
\r
6840 byte M :1; /* Data Format Mode Bit */
\r
6841 byte RSRC :1; /* Receiver Source Bit */
\r
6842 byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */
\r
6843 byte LOOPS :1; /* Loop Select Bit */
\r
6846 extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);
\r
6847 #define SCI0CR1 _SCI0CR1.Byte
\r
6848 #define SCI0CR1_PT _SCI0CR1.Bits.PT
\r
6849 #define SCI0CR1_PE _SCI0CR1.Bits.PE
\r
6850 #define SCI0CR1_ILT _SCI0CR1.Bits.ILT
\r
6851 #define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE
\r
6852 #define SCI0CR1_M _SCI0CR1.Bits.M
\r
6853 #define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC
\r
6854 #define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI
\r
6855 #define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS
\r
6858 /*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/
\r
6862 byte SBK :1; /* Send Break Bit */
\r
6863 byte RWU :1; /* Receiver Wakeup Bit */
\r
6864 byte RE :1; /* Receiver Enable Bit */
\r
6865 byte TE :1; /* Transmitter Enable Bit */
\r
6866 byte ILIE :1; /* Idle Line Interrupt Enable Bit */
\r
6867 byte RIE :1; /* Receiver Full Interrupt Enable Bit */
\r
6868 byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
\r
6869 byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
\r
6872 extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);
\r
6873 #define SCI0CR2 _SCI0CR2.Byte
\r
6874 #define SCI0CR2_SBK _SCI0CR2.Bits.SBK
\r
6875 #define SCI0CR2_RWU _SCI0CR2.Bits.RWU
\r
6876 #define SCI0CR2_RE _SCI0CR2.Bits.RE
\r
6877 #define SCI0CR2_TE _SCI0CR2.Bits.TE
\r
6878 #define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE
\r
6879 #define SCI0CR2_RIE _SCI0CR2.Bits.RIE
\r
6880 #define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE
\r
6881 #define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE
\r
6884 /*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/
\r
6888 byte PF :1; /* Parity Error Flag */
\r
6889 byte FE :1; /* Framing Error Flag */
\r
6890 byte NF :1; /* Noise Flag */
\r
6891 byte OR :1; /* Overrun Flag */
\r
6892 byte IDLE :1; /* Idle Line Flag */
\r
6893 byte RDRF :1; /* Receive Data Register Full Flag */
\r
6894 byte TC :1; /* Transmit Complete Flag */
\r
6895 byte TDRE :1; /* Transmit Data Register Empty Flag */
\r
6898 extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);
\r
6899 #define SCI0SR1 _SCI0SR1.Byte
\r
6900 #define SCI0SR1_PF _SCI0SR1.Bits.PF
\r
6901 #define SCI0SR1_FE _SCI0SR1.Bits.FE
\r
6902 #define SCI0SR1_NF _SCI0SR1.Bits.NF
\r
6903 #define SCI0SR1_OR _SCI0SR1.Bits.OR
\r
6904 #define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE
\r
6905 #define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF
\r
6906 #define SCI0SR1_TC _SCI0SR1.Bits.TC
\r
6907 #define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE
\r
6910 /*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/
\r
6914 byte RAF :1; /* Receiver Active Flag */
\r
6915 byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
\r
6916 byte BRK13 :1; /* Break Transmit character length */
\r
6924 extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);
\r
6925 #define SCI0SR2 _SCI0SR2.Byte
\r
6926 #define SCI0SR2_RAF _SCI0SR2.Bits.RAF
\r
6927 #define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR
\r
6928 #define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13
\r
6931 /*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/
\r
6941 byte T8 :1; /* Transmit Bit 8 */
\r
6942 byte R8 :1; /* Received Bit 8 */
\r
6945 extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);
\r
6946 #define SCI0DRH _SCI0DRH.Byte
\r
6947 #define SCI0DRH_T8 _SCI0DRH.Bits.T8
\r
6948 #define SCI0DRH_R8 _SCI0DRH.Bits.R8
\r
6951 /*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/
\r
6955 byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
\r
6956 byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
\r
6957 byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
\r
6958 byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
\r
6959 byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
\r
6960 byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
\r
6961 byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
\r
6962 byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
\r
6965 extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);
\r
6966 #define SCI0DRL _SCI0DRL.Byte
\r
6967 #define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0
\r
6968 #define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1
\r
6969 #define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2
\r
6970 #define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3
\r
6971 #define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4
\r
6972 #define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5
\r
6973 #define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6
\r
6974 #define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7
\r
6977 /*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/
\r
6981 byte PT :1; /* Parity Type Bit */
\r
6982 byte PE :1; /* Parity Enable Bit */
\r
6983 byte ILT :1; /* Idle Line Type Bit */
\r
6984 byte WAKE :1; /* Wakeup Condition Bit */
\r
6985 byte M :1; /* Data Format Mode Bit */
\r
6986 byte RSRC :1; /* Receiver Source Bit */
\r
6987 byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */
\r
6988 byte LOOPS :1; /* Loop Select Bit */
\r
6991 extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);
\r
6992 #define SCI1CR1 _SCI1CR1.Byte
\r
6993 #define SCI1CR1_PT _SCI1CR1.Bits.PT
\r
6994 #define SCI1CR1_PE _SCI1CR1.Bits.PE
\r
6995 #define SCI1CR1_ILT _SCI1CR1.Bits.ILT
\r
6996 #define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE
\r
6997 #define SCI1CR1_M _SCI1CR1.Bits.M
\r
6998 #define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC
\r
6999 #define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI
\r
7000 #define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS
\r
7003 /*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/
\r
7007 byte SBK :1; /* Send Break Bit */
\r
7008 byte RWU :1; /* Receiver Wakeup Bit */
\r
7009 byte RE :1; /* Receiver Enable Bit */
\r
7010 byte TE :1; /* Transmitter Enable Bit */
\r
7011 byte ILIE :1; /* Idle Line Interrupt Enable Bit */
\r
7012 byte RIE :1; /* Receiver Full Interrupt Enable Bit */
\r
7013 byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
\r
7014 byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
\r
7017 extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);
\r
7018 #define SCI1CR2 _SCI1CR2.Byte
\r
7019 #define SCI1CR2_SBK _SCI1CR2.Bits.SBK
\r
7020 #define SCI1CR2_RWU _SCI1CR2.Bits.RWU
\r
7021 #define SCI1CR2_RE _SCI1CR2.Bits.RE
\r
7022 #define SCI1CR2_TE _SCI1CR2.Bits.TE
\r
7023 #define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE
\r
7024 #define SCI1CR2_RIE _SCI1CR2.Bits.RIE
\r
7025 #define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE
\r
7026 #define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE
\r
7029 /*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/
\r
7033 byte PF :1; /* Parity Error Flag */
\r
7034 byte FE :1; /* Framing Error Flag */
\r
7035 byte NF :1; /* Noise Flag */
\r
7036 byte OR :1; /* Overrun Flag */
\r
7037 byte IDLE :1; /* Idle Line Flag */
\r
7038 byte RDRF :1; /* Receive Data Register Full Flag */
\r
7039 byte TC :1; /* Transmit Complete Flag */
\r
7040 byte TDRE :1; /* Transmit Data Register Empty Flag */
\r
7043 extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);
\r
7044 #define SCI1SR1 _SCI1SR1.Byte
\r
7045 #define SCI1SR1_PF _SCI1SR1.Bits.PF
\r
7046 #define SCI1SR1_FE _SCI1SR1.Bits.FE
\r
7047 #define SCI1SR1_NF _SCI1SR1.Bits.NF
\r
7048 #define SCI1SR1_OR _SCI1SR1.Bits.OR
\r
7049 #define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE
\r
7050 #define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF
\r
7051 #define SCI1SR1_TC _SCI1SR1.Bits.TC
\r
7052 #define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE
\r
7055 /*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/
\r
7059 byte RAF :1; /* Receiver Active Flag */
\r
7060 byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
\r
7061 byte BRK13 :1; /* Break Transmit character length */
\r
7069 extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);
\r
7070 #define SCI1SR2 _SCI1SR2.Byte
\r
7071 #define SCI1SR2_RAF _SCI1SR2.Bits.RAF
\r
7072 #define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR
\r
7073 #define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13
\r
7076 /*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/
\r
7086 byte T8 :1; /* Transmit Bit 8 */
\r
7087 byte R8 :1; /* Received Bit 8 */
\r
7090 extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);
\r
7091 #define SCI1DRH _SCI1DRH.Byte
\r
7092 #define SCI1DRH_T8 _SCI1DRH.Bits.T8
\r
7093 #define SCI1DRH_R8 _SCI1DRH.Bits.R8
\r
7096 /*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/
\r
7100 byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
\r
7101 byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
\r
7102 byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
\r
7103 byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
\r
7104 byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
\r
7105 byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
\r
7106 byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
\r
7107 byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
\r
7110 extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);
\r
7111 #define SCI1DRL _SCI1DRL.Byte
\r
7112 #define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0
\r
7113 #define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1
\r
7114 #define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2
\r
7115 #define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3
\r
7116 #define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4
\r
7117 #define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5
\r
7118 #define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6
\r
7119 #define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7
\r
7122 /*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/
\r
7126 byte LSBFE :1; /* SPI 0 LSB-First Enable */
\r
7127 byte SSOE :1; /* Slave Select Output Enable */
\r
7128 byte CPHA :1; /* SPI 0 Clock Phase Bit */
\r
7129 byte CPOL :1; /* SPI 0 Clock Polarity Bit */
\r
7130 byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */
\r
7131 byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */
\r
7132 byte SPE :1; /* SPI 0 System Enable Bit */
\r
7133 byte SPIE :1; /* SPI 0 Interrupt Enable Bit */
\r
7136 extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8);
\r
7137 #define SPI0CR1 _SPI0CR1.Byte
\r
7138 #define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE
\r
7139 #define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE
\r
7140 #define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA
\r
7141 #define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL
\r
7142 #define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR
\r
7143 #define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE
\r
7144 #define SPI0CR1_SPE _SPI0CR1.Bits.SPE
\r
7145 #define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE
\r
7148 /*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/
\r
7152 byte SPC0 :1; /* Serial Pin Control Bit 0 */
\r
7153 byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */
\r
7155 byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
\r
7156 byte MODFEN :1; /* Mode Fault Enable Bit */
\r
7162 extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9);
\r
7163 #define SPI0CR2 _SPI0CR2.Byte
\r
7164 #define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0
\r
7165 #define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI
\r
7166 #define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE
\r
7167 #define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN
\r
7170 /*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/
\r
7174 byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */
\r
7175 byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */
\r
7176 byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */
\r
7178 byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */
\r
7179 byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */
\r
7180 byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */
\r
7190 extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA);
\r
7191 #define SPI0BR _SPI0BR.Byte
\r
7192 #define SPI0BR_SPR0 _SPI0BR.Bits.SPR0
\r
7193 #define SPI0BR_SPR1 _SPI0BR.Bits.SPR1
\r
7194 #define SPI0BR_SPR2 _SPI0BR.Bits.SPR2
\r
7195 #define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0
\r
7196 #define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1
\r
7197 #define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2
\r
7198 #define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR
\r
7199 #define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR
\r
7202 /*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/
\r
7210 byte MODF :1; /* Mode Fault Flag */
\r
7211 byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */
\r
7213 byte SPIF :1; /* SPIF Receive Interrupt Flag */
\r
7216 extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB);
\r
7217 #define SPI0SR _SPI0SR.Byte
\r
7218 #define SPI0SR_MODF _SPI0SR.Bits.MODF
\r
7219 #define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF
\r
7220 #define SPI0SR_SPIF _SPI0SR.Bits.SPIF
\r
7223 /*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/
\r
7230 extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD);
\r
7231 #define SPI0DR _SPI0DR.Byte
\r
7232 #define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT
\r
7235 /*** IBAD - IIC Address Register; 0x000000E0 ***/
\r
7240 byte ADR1 :1; /* Slave Address Bit 1 */
\r
7241 byte ADR2 :1; /* Slave Address Bit 2 */
\r
7242 byte ADR3 :1; /* Slave Address Bit 3 */
\r
7243 byte ADR4 :1; /* Slave Address Bit 4 */
\r
7244 byte ADR5 :1; /* Slave Address Bit 5 */
\r
7245 byte ADR6 :1; /* Slave Address Bit 6 */
\r
7246 byte ADR7 :1; /* Slave Address Bit 7 */
\r
7253 extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0);
\r
7254 #define IBAD _IBAD.Byte
\r
7255 #define IBAD_ADR1 _IBAD.Bits.ADR1
\r
7256 #define IBAD_ADR2 _IBAD.Bits.ADR2
\r
7257 #define IBAD_ADR3 _IBAD.Bits.ADR3
\r
7258 #define IBAD_ADR4 _IBAD.Bits.ADR4
\r
7259 #define IBAD_ADR5 _IBAD.Bits.ADR5
\r
7260 #define IBAD_ADR6 _IBAD.Bits.ADR6
\r
7261 #define IBAD_ADR7 _IBAD.Bits.ADR7
\r
7262 #define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1
\r
7263 #define IBAD_ADR IBAD_ADR_1
\r
7266 /*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/
\r
7270 byte IBC0 :1; /* I-Bus Clock Rate 0 */
\r
7271 byte IBC1 :1; /* I-Bus Clock Rate 1 */
\r
7272 byte IBC2 :1; /* I-Bus Clock Rate 2 */
\r
7273 byte IBC3 :1; /* I-Bus Clock Rate 3 */
\r
7274 byte IBC4 :1; /* I-Bus Clock Rate 4 */
\r
7275 byte IBC5 :1; /* I-Bus Clock Rate 5 */
\r
7276 byte IBC6 :1; /* I-Bus Clock Rate 6 */
\r
7277 byte IBC7 :1; /* I-Bus Clock Rate 7 */
\r
7283 extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1);
\r
7284 #define IBFD _IBFD.Byte
\r
7285 #define IBFD_IBC0 _IBFD.Bits.IBC0
\r
7286 #define IBFD_IBC1 _IBFD.Bits.IBC1
\r
7287 #define IBFD_IBC2 _IBFD.Bits.IBC2
\r
7288 #define IBFD_IBC3 _IBFD.Bits.IBC3
\r
7289 #define IBFD_IBC4 _IBFD.Bits.IBC4
\r
7290 #define IBFD_IBC5 _IBFD.Bits.IBC5
\r
7291 #define IBFD_IBC6 _IBFD.Bits.IBC6
\r
7292 #define IBFD_IBC7 _IBFD.Bits.IBC7
\r
7293 #define IBFD_IBC _IBFD.MergedBits.grpIBC
\r
7296 /*** IBCR - IIC Control Register; 0x000000E2 ***/
\r
7300 byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */
\r
7302 byte RSTA :1; /* Repeat Start */
\r
7303 byte TXAK :1; /* Transmit Acknowledge enable */
\r
7304 byte TX_RX :1; /* Transmit/Receive mode select bit */
\r
7305 byte MS_SL :1; /* Master/Slave mode select bit */
\r
7306 byte IBIE :1; /* I-Bus Interrupt Enable */
\r
7307 byte IBEN :1; /* I-Bus Enable */
\r
7310 extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2);
\r
7311 #define IBCR _IBCR.Byte
\r
7312 #define IBCR_IBSWAI _IBCR.Bits.IBSWAI
\r
7313 #define IBCR_RSTA _IBCR.Bits.RSTA
\r
7314 #define IBCR_TXAK _IBCR.Bits.TXAK
\r
7315 #define IBCR_TX_RX _IBCR.Bits.TX_RX
\r
7316 #define IBCR_MS_SL _IBCR.Bits.MS_SL
\r
7317 #define IBCR_IBIE _IBCR.Bits.IBIE
\r
7318 #define IBCR_IBEN _IBCR.Bits.IBEN
\r
7321 /*** IBSR - IIC Status Register; 0x000000E3 ***/
\r
7325 byte RXAK :1; /* Received Acknowledge */
\r
7326 byte IBIF :1; /* I-Bus Interrupt */
\r
7327 byte SRW :1; /* Slave Read/Write */
\r
7329 byte IBAL :1; /* Arbitration Lost */
\r
7330 byte IBB :1; /* Bus busy bit */
\r
7331 byte IAAS :1; /* Addressed as a slave bit */
\r
7332 byte TCF :1; /* Data transferring bit */
\r
7335 extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3);
\r
7336 #define IBSR _IBSR.Byte
\r
7337 #define IBSR_RXAK _IBSR.Bits.RXAK
\r
7338 #define IBSR_IBIF _IBSR.Bits.IBIF
\r
7339 #define IBSR_SRW _IBSR.Bits.SRW
\r
7340 #define IBSR_IBAL _IBSR.Bits.IBAL
\r
7341 #define IBSR_IBB _IBSR.Bits.IBB
\r
7342 #define IBSR_IAAS _IBSR.Bits.IAAS
\r
7343 #define IBSR_TCF _IBSR.Bits.TCF
\r
7346 /*** IBDR - IIC Data I/O Register; 0x000000E4 ***/
\r
7350 byte D0 :1; /* IIC Data Bit 0 */
\r
7351 byte D1 :1; /* IIC Data Bit 1 */
\r
7352 byte D2 :1; /* IIC Data Bit 2 */
\r
7353 byte D3 :1; /* IIC Data Bit 3 */
\r
7354 byte D4 :1; /* IIC Data Bit 4 */
\r
7355 byte D5 :1; /* IIC Data Bit 5 */
\r
7356 byte D6 :1; /* IIC Data Bit 6 */
\r
7357 byte D7 :1; /* IIC Data Bit 7 */
\r
7363 extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4);
\r
7364 #define IBDR _IBDR.Byte
\r
7365 #define IBDR_D0 _IBDR.Bits.D0
\r
7366 #define IBDR_D1 _IBDR.Bits.D1
\r
7367 #define IBDR_D2 _IBDR.Bits.D2
\r
7368 #define IBDR_D3 _IBDR.Bits.D3
\r
7369 #define IBDR_D4 _IBDR.Bits.D4
\r
7370 #define IBDR_D5 _IBDR.Bits.D5
\r
7371 #define IBDR_D6 _IBDR.Bits.D6
\r
7372 #define IBDR_D7 _IBDR.Bits.D7
\r
7373 #define IBDR_D _IBDR.MergedBits.grpD
\r
7376 /*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/
\r
7380 byte WCM :1; /* Wait Clock Mode */
\r
7381 byte IE :1; /* Interrupt Enable */
\r
7386 byte CLKS :1; /* Clock Select */
\r
7387 byte IMSG :1; /* Ignore Message */
\r
7390 extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8);
\r
7391 #define DLCBCR1 _DLCBCR1.Byte
\r
7392 #define DLCBCR1_WCM _DLCBCR1.Bits.WCM
\r
7393 #define DLCBCR1_IE _DLCBCR1.Bits.IE
\r
7394 #define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS
\r
7395 #define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG
\r
7398 /*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/
\r
7404 byte I0 :1; /* Interrupt State Vector Bit 0 */
\r
7405 byte I1 :1; /* Interrupt State Vector Bit 1 */
\r
7406 byte I2 :1; /* Interrupt State Vector Bit 2 */
\r
7407 byte I3 :1; /* Interrupt State Vector Bit 3 */
\r
7419 extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9);
\r
7420 #define DLCBSVR _DLCBSVR.Byte
\r
7421 #define DLCBSVR_I0 _DLCBSVR.Bits.I0
\r
7422 #define DLCBSVR_I1 _DLCBSVR.Bits.I1
\r
7423 #define DLCBSVR_I2 _DLCBSVR.Bits.I2
\r
7424 #define DLCBSVR_I3 _DLCBSVR.Bits.I3
\r
7425 #define DLCBSVR_I _DLCBSVR.MergedBits.grpI
\r
7428 /*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/
\r
7432 byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */
\r
7433 byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */
\r
7434 byte TSIFR :1; /* Transmit In-Frame Response Control 2 */
\r
7435 byte TEOD :1; /* Transmit End of Data */
\r
7436 byte NBFS :1; /* Normalization Bit Format Select */
\r
7437 byte RX4XE :1; /* Receive 4X Enable */
\r
7438 byte DLOOP :1; /* Digital Loopback Mode */
\r
7439 byte SMRST :1; /* State Machine Reset */
\r
7451 extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA);
\r
7452 #define DLCBCR2 _DLCBCR2.Byte
\r
7453 #define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0
\r
7454 #define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1
\r
7455 #define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR
\r
7456 #define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD
\r
7457 #define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS
\r
7458 #define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE
\r
7459 #define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP
\r
7460 #define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST
\r
7461 #define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR
\r
7464 /*** DLCBDR - BDLC Data Register; 0x000000EB ***/
\r
7468 byte D0 :1; /* Receive/Transmit Data Bit 0 */
\r
7469 byte D1 :1; /* Receive/Transmit Data Bit 1 */
\r
7470 byte D2 :1; /* Receive/Transmit Data Bit 2 */
\r
7471 byte D3 :1; /* Receive/Transmit Data Bit 3 */
\r
7472 byte D4 :1; /* Receive/Transmit Data Bit 4 */
\r
7473 byte D5 :1; /* Receive/Transmit Data Bit 5 */
\r
7474 byte D6 :1; /* Receive/Transmit Data Bit 6 */
\r
7475 byte D7 :1; /* Receive/Transmit Data Bit 7 */
\r
7481 extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB);
\r
7482 #define DLCBDR _DLCBDR.Byte
\r
7483 #define DLCBDR_D0 _DLCBDR.Bits.D0
\r
7484 #define DLCBDR_D1 _DLCBDR.Bits.D1
\r
7485 #define DLCBDR_D2 _DLCBDR.Bits.D2
\r
7486 #define DLCBDR_D3 _DLCBDR.Bits.D3
\r
7487 #define DLCBDR_D4 _DLCBDR.Bits.D4
\r
7488 #define DLCBDR_D5 _DLCBDR.Bits.D5
\r
7489 #define DLCBDR_D6 _DLCBDR.Bits.D6
\r
7490 #define DLCBDR_D7 _DLCBDR.Bits.D7
\r
7491 #define DLCBDR_D _DLCBDR.MergedBits.grpD
\r
7494 /*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/
\r
7498 byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */
\r
7499 byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */
\r
7500 byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */
\r
7501 byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */
\r
7504 byte RXPOL :1; /* Receive Pin Polarity */
\r
7515 extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC);
\r
7516 #define DLCBARD _DLCBARD.Byte
\r
7517 #define DLCBARD_BO0 _DLCBARD.Bits.BO0
\r
7518 #define DLCBARD_BO1 _DLCBARD.Bits.BO1
\r
7519 #define DLCBARD_BO2 _DLCBARD.Bits.BO2
\r
7520 #define DLCBARD_BO3 _DLCBARD.Bits.BO3
\r
7521 #define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL
\r
7522 #define DLCBARD_BO _DLCBARD.MergedBits.grpBO
\r
7525 /*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/
\r
7529 byte R0 :1; /* Rate Select 0 */
\r
7530 byte R1 :1; /* Rate Select 1 */
\r
7531 byte R2 :1; /* Rate Select 2 */
\r
7532 byte R3 :1; /* Rate Select 3 */
\r
7533 byte R4 :1; /* Rate Select 4 */
\r
7534 byte R5 :1; /* Rate Select 5 */
\r
7544 extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED);
\r
7545 #define DLCBRSR _DLCBRSR.Byte
\r
7546 #define DLCBRSR_R0 _DLCBRSR.Bits.R0
\r
7547 #define DLCBRSR_R1 _DLCBRSR.Bits.R1
\r
7548 #define DLCBRSR_R2 _DLCBRSR.Bits.R2
\r
7549 #define DLCBRSR_R3 _DLCBRSR.Bits.R3
\r
7550 #define DLCBRSR_R4 _DLCBRSR.Bits.R4
\r
7551 #define DLCBRSR_R5 _DLCBRSR.Bits.R5
\r
7552 #define DLCBRSR_R _DLCBRSR.MergedBits.grpR
\r
7555 /*** DLCSCR - BDLC Control Register; 0x000000EE ***/
\r
7563 byte BDLCE :1; /* BDLC Enable */
\r
7569 extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE);
\r
7570 #define DLCSCR _DLCSCR.Byte
\r
7571 #define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE
\r
7574 /*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/
\r
7578 byte LSBFE :1; /* SPI 1 LSB-First Enable */
\r
7579 byte SSOE :1; /* Slave Select Output Enable */
\r
7580 byte CPHA :1; /* SPI 1 Clock Phase Bit */
\r
7581 byte CPOL :1; /* SPI 1 Clock Polarity Bit */
\r
7582 byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */
\r
7583 byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */
\r
7584 byte SPE :1; /* SPI 1 System Enable Bit */
\r
7585 byte SPIE :1; /* SPI 1 Interrupt Enable Bit */
\r
7588 extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0);
\r
7589 #define SPI1CR1 _SPI1CR1.Byte
\r
7590 #define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE
\r
7591 #define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE
\r
7592 #define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA
\r
7593 #define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL
\r
7594 #define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR
\r
7595 #define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE
\r
7596 #define SPI1CR1_SPE _SPI1CR1.Bits.SPE
\r
7597 #define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE
\r
7600 /*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/
\r
7604 byte SPC0 :1; /* Serial Pin Control Bit 0 */
\r
7605 byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */
\r
7607 byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
\r
7608 byte MODFEN :1; /* Mode Fault Enable Bit */
\r
7614 extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1);
\r
7615 #define SPI1CR2 _SPI1CR2.Byte
\r
7616 #define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0
\r
7617 #define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI
\r
7618 #define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE
\r
7619 #define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN
\r
7622 /*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/
\r
7626 byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */
\r
7627 byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */
\r
7628 byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */
\r
7630 byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */
\r
7631 byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */
\r
7632 byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */
\r
7642 extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2);
\r
7643 #define SPI1BR _SPI1BR.Byte
\r
7644 #define SPI1BR_SPR0 _SPI1BR.Bits.SPR0
\r
7645 #define SPI1BR_SPR1 _SPI1BR.Bits.SPR1
\r
7646 #define SPI1BR_SPR2 _SPI1BR.Bits.SPR2
\r
7647 #define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0
\r
7648 #define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1
\r
7649 #define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2
\r
7650 #define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR
\r
7651 #define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR
\r
7654 /*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/
\r
7662 byte MODF :1; /* Mode Fault Flag */
\r
7663 byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */
\r
7665 byte SPIF :1; /* SPIF Receive Interrupt Flag */
\r
7668 extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3);
\r
7669 #define SPI1SR _SPI1SR.Byte
\r
7670 #define SPI1SR_MODF _SPI1SR.Bits.MODF
\r
7671 #define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF
\r
7672 #define SPI1SR_SPIF _SPI1SR.Bits.SPIF
\r
7675 /*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/
\r
7682 extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5);
\r
7683 #define SPI1DR _SPI1DR.Byte
\r
7684 #define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT
\r
7687 /*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/
\r
7691 byte LSBFE :1; /* SPI 2 LSB-First Enable */
\r
7692 byte SSOE :1; /* Slave Select Output Enable */
\r
7693 byte CPHA :1; /* SPI 2 Clock Phase Bit */
\r
7694 byte CPOL :1; /* SPI 2 Clock Polarity Bit */
\r
7695 byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */
\r
7696 byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */
\r
7697 byte SPE :1; /* SPI 2 System Enable Bit */
\r
7698 byte SPIE :1; /* SPI 2 Interrupt Enable Bit */
\r
7701 extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8);
\r
7702 #define SPI2CR1 _SPI2CR1.Byte
\r
7703 #define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE
\r
7704 #define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE
\r
7705 #define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA
\r
7706 #define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL
\r
7707 #define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR
\r
7708 #define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE
\r
7709 #define SPI2CR1_SPE _SPI2CR1.Bits.SPE
\r
7710 #define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE
\r
7713 /*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/
\r
7717 byte SPC0 :1; /* Serial Pin Control Bit 0 */
\r
7718 byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */
\r
7720 byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
\r
7721 byte MODFEN :1; /* Mode Fault Enable Bit */
\r
7727 extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9);
\r
7728 #define SPI2CR2 _SPI2CR2.Byte
\r
7729 #define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0
\r
7730 #define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI
\r
7731 #define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE
\r
7732 #define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN
\r
7735 /*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/
\r
7739 byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */
\r
7740 byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */
\r
7741 byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */
\r
7743 byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */
\r
7744 byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */
\r
7745 byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */
\r
7755 extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA);
\r
7756 #define SPI2BR _SPI2BR.Byte
\r
7757 #define SPI2BR_SPR0 _SPI2BR.Bits.SPR0
\r
7758 #define SPI2BR_SPR1 _SPI2BR.Bits.SPR1
\r
7759 #define SPI2BR_SPR2 _SPI2BR.Bits.SPR2
\r
7760 #define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0
\r
7761 #define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1
\r
7762 #define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2
\r
7763 #define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR
\r
7764 #define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR
\r
7767 /*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/
\r
7775 byte MODF :1; /* Mode Fault Flag */
\r
7776 byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */
\r
7778 byte SPIF :1; /* SPIF Receive Interrupt Flag */
\r
7781 extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB);
\r
7782 #define SPI2SR _SPI2SR.Byte
\r
7783 #define SPI2SR_MODF _SPI2SR.Bits.MODF
\r
7784 #define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF
\r
7785 #define SPI2SR_SPIF _SPI2SR.Bits.SPIF
\r
7788 /*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/
\r
7795 extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD);
\r
7796 #define SPI2DR _SPI2DR.Byte
\r
7797 #define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT
\r
7800 /*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/
\r
7804 byte FDIV0 :1; /* Flash Clock Divider Bit 0 */
\r
7805 byte FDIV1 :1; /* Flash Clock Divider Bit 1 */
\r
7806 byte FDIV2 :1; /* Flash Clock Divider Bit 2 */
\r
7807 byte FDIV3 :1; /* Flash Clock Divider Bit 3 */
\r
7808 byte FDIV4 :1; /* Flash Clock Divider Bit 4 */
\r
7809 byte FDIV5 :1; /* Flash Clock Divider Bit 5 */
\r
7810 byte PRDIV8 :1; /* Enable Prescaler by 8 */
\r
7811 byte FDIVLD :1; /* Flash Clock Divider Loaded */
\r
7815 byte grpPRDIV_8 :1;
\r
7819 extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);
\r
7820 #define FCLKDIV _FCLKDIV.Byte
\r
7821 #define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0
\r
7822 #define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1
\r
7823 #define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2
\r
7824 #define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3
\r
7825 #define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4
\r
7826 #define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5
\r
7827 #define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8
\r
7828 #define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD
\r
7829 #define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV
\r
7832 /*** FSEC - Flash Security Register; 0x00000101 ***/
\r
7836 byte SEC0 :1; /* Memory security bit 0 */
\r
7837 byte SEC1 :1; /* Memory security bit 1 */
\r
7838 byte NV2 :1; /* Non Volatile flag bit 2 */
\r
7839 byte NV3 :1; /* Non Volatile flag bit 3 */
\r
7840 byte NV4 :1; /* Non Volatile flag bit 4 */
\r
7841 byte NV5 :1; /* Non Volatile flag bit 5 */
\r
7842 byte NV6 :1; /* Non Volatile flag bit 6 */
\r
7843 byte KEYEN :1; /* Enable backdoor key to security */
\r
7851 extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);
\r
7852 #define FSEC _FSEC.Byte
\r
7853 #define FSEC_SEC0 _FSEC.Bits.SEC0
\r
7854 #define FSEC_SEC1 _FSEC.Bits.SEC1
\r
7855 #define FSEC_NV2 _FSEC.Bits.NV2
\r
7856 #define FSEC_NV3 _FSEC.Bits.NV3
\r
7857 #define FSEC_NV4 _FSEC.Bits.NV4
\r
7858 #define FSEC_NV5 _FSEC.Bits.NV5
\r
7859 #define FSEC_NV6 _FSEC.Bits.NV6
\r
7860 #define FSEC_KEYEN _FSEC.Bits.KEYEN
\r
7861 #define FSEC_SEC _FSEC.MergedBits.grpSEC
\r
7862 #define FSEC_NV_2 _FSEC.MergedBits.grpNV_2
\r
7863 #define FSEC_NV FSEC_NV_2
\r
7866 /*** FCNFG - Flash Configuration Register; 0x00000103 ***/
\r
7870 byte BKSEL0 :1; /* Register bank select 0 */
\r
7871 byte BKSEL1 :1; /* Register bank select 1 */
\r
7875 byte KEYACC :1; /* Enable Security Key Writing */
\r
7876 byte CCIE :1; /* Command Complete Interrupt Enable */
\r
7877 byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
\r
7889 extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);
\r
7890 #define FCNFG _FCNFG.Byte
\r
7891 #define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0
\r
7892 #define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1
\r
7893 #define FCNFG_KEYACC _FCNFG.Bits.KEYACC
\r
7894 #define FCNFG_CCIE _FCNFG.Bits.CCIE
\r
7895 #define FCNFG_CBEIE _FCNFG.Bits.CBEIE
\r
7896 #define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL
\r
7899 /*** FPROT - Flash Protection Register; 0x00000104 ***/
\r
7903 byte FPLS0 :1; /* Flash Protection Lower Address size 0 */
\r
7904 byte FPLS1 :1; /* Flash Protection Lower Address size 1 */
\r
7905 byte FPLDIS :1; /* Flash Protection Lower address range disable */
\r
7906 byte FPHS0 :1; /* Flash Protection Higher address size 0 */
\r
7907 byte FPHS1 :1; /* Flash Protection Higher address size 1 */
\r
7908 byte FPHDIS :1; /* Flash Protection Higher address range disable */
\r
7909 byte NV6 :1; /* Non Volatile Flag Bit */
\r
7910 byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */
\r
7921 extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);
\r
7922 #define FPROT _FPROT.Byte
\r
7923 #define FPROT_FPLS0 _FPROT.Bits.FPLS0
\r
7924 #define FPROT_FPLS1 _FPROT.Bits.FPLS1
\r
7925 #define FPROT_FPLDIS _FPROT.Bits.FPLDIS
\r
7926 #define FPROT_FPHS0 _FPROT.Bits.FPHS0
\r
7927 #define FPROT_FPHS1 _FPROT.Bits.FPHS1
\r
7928 #define FPROT_FPHDIS _FPROT.Bits.FPHDIS
\r
7929 #define FPROT_NV6 _FPROT.Bits.NV6
\r
7930 #define FPROT_FPOPEN _FPROT.Bits.FPOPEN
\r
7931 #define FPROT_FPLS _FPROT.MergedBits.grpFPLS
\r
7932 #define FPROT_FPHS _FPROT.MergedBits.grpFPHS
\r
7935 /*** FSTAT - Flash Status Register; 0x00000105 ***/
\r
7941 byte BLANK :1; /* Blank Verify Flag */
\r
7943 byte ACCERR :1; /* Access error */
\r
7944 byte PVIOL :1; /* Protection violation */
\r
7945 byte CCIF :1; /* Command Complete Interrupt Flag */
\r
7946 byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */
\r
7949 extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);
\r
7950 #define FSTAT _FSTAT.Byte
\r
7951 #define FSTAT_BLANK _FSTAT.Bits.BLANK
\r
7952 #define FSTAT_ACCERR _FSTAT.Bits.ACCERR
\r
7953 #define FSTAT_PVIOL _FSTAT.Bits.PVIOL
\r
7954 #define FSTAT_CCIF _FSTAT.Bits.CCIF
\r
7955 #define FSTAT_CBEIF _FSTAT.Bits.CBEIF
\r
7958 /*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/
\r
7962 byte CMDB0 :1; /* NVM User Mode Command Bit 0 */
\r
7964 byte CMDB2 :1; /* NVM User Mode Command Bit 2 */
\r
7967 byte CMDB5 :1; /* NVM User Mode Command Bit 5 */
\r
7968 byte CMDB6 :1; /* NVM User Mode Command Bit 6 */
\r
7974 byte grpCMDB_2 :1;
\r
7977 byte grpCMDB_5 :2;
\r
7981 extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);
\r
7982 #define FCMD _FCMD.Byte
\r
7983 #define FCMD_CMDB0 _FCMD.Bits.CMDB0
\r
7984 #define FCMD_CMDB2 _FCMD.Bits.CMDB2
\r
7985 #define FCMD_CMDB5 _FCMD.Bits.CMDB5
\r
7986 #define FCMD_CMDB6 _FCMD.Bits.CMDB6
\r
7987 #define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5
\r
7988 #define FCMD_CMDB FCMD_CMDB_5
\r
7991 /*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/
\r
7995 byte EDIV0 :1; /* EEPROM Clock Divider 0 */
\r
7996 byte EDIV1 :1; /* EEPROM Clock Divider 1 */
\r
7997 byte EDIV2 :1; /* EEPROM Clock Divider 2 */
\r
7998 byte EDIV3 :1; /* EEPROM Clock Divider 3 */
\r
7999 byte EDIV4 :1; /* EEPROM Clock Divider 4 */
\r
8000 byte EDIV5 :1; /* EEPROM Clock Divider 5 */
\r
8001 byte PRDIV8 :1; /* Enable Prescaler by 8 */
\r
8002 byte EDIVLD :1; /* EEPROM Clock Divider Loaded */
\r
8006 byte grpPRDIV_8 :1;
\r
8010 extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);
\r
8011 #define ECLKDIV _ECLKDIV.Byte
\r
8012 #define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0
\r
8013 #define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1
\r
8014 #define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2
\r
8015 #define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3
\r
8016 #define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4
\r
8017 #define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5
\r
8018 #define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8
\r
8019 #define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD
\r
8020 #define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV
\r
8023 /*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/
\r
8033 byte CCIE :1; /* Command Complete Interrupt Enable */
\r
8034 byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
\r
8037 extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);
\r
8038 #define ECNFG _ECNFG.Byte
\r
8039 #define ECNFG_CCIE _ECNFG.Bits.CCIE
\r
8040 #define ECNFG_CBEIE _ECNFG.Bits.CBEIE
\r
8043 /*** EPROT - EEPROM Protection Register; 0x00000114 ***/
\r
8047 byte EP0 :1; /* EEPROM Protection address size 0 */
\r
8048 byte EP1 :1; /* EEPROM Protection address size 1 */
\r
8049 byte EP2 :1; /* EEPROM Protection address size 2 */
\r
8050 byte EPDIS :1; /* EEPROM Protection disable */
\r
8054 byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */
\r
8065 extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);
\r
8066 #define EPROT _EPROT.Byte
\r
8067 #define EPROT_EP0 _EPROT.Bits.EP0
\r
8068 #define EPROT_EP1 _EPROT.Bits.EP1
\r
8069 #define EPROT_EP2 _EPROT.Bits.EP2
\r
8070 #define EPROT_EPDIS _EPROT.Bits.EPDIS
\r
8071 #define EPROT_EPOPEN _EPROT.Bits.EPOPEN
\r
8072 #define EPROT_EP _EPROT.MergedBits.grpEP
\r
8075 /*** ESTAT - EEPROM Status Register; 0x00000115 ***/
\r
8081 byte BLANK :1; /* Blank Verify Flag */
\r
8083 byte ACCERR :1; /* Access error */
\r
8084 byte PVIOL :1; /* Protection violation */
\r
8085 byte CCIF :1; /* Command Complete Interrupt Flag */
\r
8086 byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */
\r
8089 extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);
\r
8090 #define ESTAT _ESTAT.Byte
\r
8091 #define ESTAT_BLANK _ESTAT.Bits.BLANK
\r
8092 #define ESTAT_ACCERR _ESTAT.Bits.ACCERR
\r
8093 #define ESTAT_PVIOL _ESTAT.Bits.PVIOL
\r
8094 #define ESTAT_CCIF _ESTAT.Bits.CCIF
\r
8095 #define ESTAT_CBEIF _ESTAT.Bits.CBEIF
\r
8098 /*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/
\r
8102 byte CMDB0 :1; /* EEPROM User Mode Command 0 */
\r
8104 byte CMDB2 :1; /* EEPROM User Mode Command 2 */
\r
8107 byte CMDB5 :1; /* EEPROM User Mode Command 5 */
\r
8108 byte CMDB6 :1; /* EEPROM User Mode Command 6 */
\r
8114 byte grpCMDB_2 :1;
\r
8117 byte grpCMDB_5 :2;
\r
8121 extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);
\r
8122 #define ECMD _ECMD.Byte
\r
8123 #define ECMD_CMDB0 _ECMD.Bits.CMDB0
\r
8124 #define ECMD_CMDB2 _ECMD.Bits.CMDB2
\r
8125 #define ECMD_CMDB5 _ECMD.Bits.CMDB5
\r
8126 #define ECMD_CMDB6 _ECMD.Bits.CMDB6
\r
8127 #define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5
\r
8128 #define ECMD_CMDB ECMD_CMDB_5
\r
8131 /*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/
\r
8135 byte CC0 :1; /* Conversion Counter 0 */
\r
8136 byte CC1 :1; /* Conversion Counter 1 */
\r
8137 byte CC2 :1; /* Conversion Counter 2 */
\r
8139 byte FIFOR :1; /* FIFO Over Run Flag */
\r
8140 byte ETORF :1; /* External Trigger Overrun Flag */
\r
8142 byte SCF :1; /* Sequence Complete Flag */
\r
8153 extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126);
\r
8154 #define ATD1STAT0 _ATD1STAT0.Byte
\r
8155 #define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0
\r
8156 #define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1
\r
8157 #define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2
\r
8158 #define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR
\r
8159 #define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF
\r
8160 #define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF
\r
8161 #define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC
\r
8164 /*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/
\r
8168 byte CCF0 :1; /* Conversion Complete Flag 0 */
\r
8169 byte CCF1 :1; /* Conversion Complete Flag 1 */
\r
8170 byte CCF2 :1; /* Conversion Complete Flag 2 */
\r
8171 byte CCF3 :1; /* Conversion Complete Flag 3 */
\r
8172 byte CCF4 :1; /* Conversion Complete Flag 4 */
\r
8173 byte CCF5 :1; /* Conversion Complete Flag 5 */
\r
8174 byte CCF6 :1; /* Conversion Complete Flag 6 */
\r
8175 byte CCF7 :1; /* Conversion Complete Flag 7 */
\r
8181 extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B);
\r
8182 #define ATD1STAT1 _ATD1STAT1.Byte
\r
8183 #define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0
\r
8184 #define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1
\r
8185 #define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2
\r
8186 #define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3
\r
8187 #define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4
\r
8188 #define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5
\r
8189 #define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6
\r
8190 #define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7
\r
8191 #define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF
\r
8194 /*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/
\r
8198 byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */
\r
8199 byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */
\r
8200 byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */
\r
8201 byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */
\r
8202 byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */
\r
8203 byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */
\r
8204 byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */
\r
8205 byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */
\r
8211 extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D);
\r
8212 #define ATD1DIEN _ATD1DIEN.Byte
\r
8213 #define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0
\r
8214 #define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1
\r
8215 #define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2
\r
8216 #define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3
\r
8217 #define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4
\r
8218 #define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5
\r
8219 #define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6
\r
8220 #define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7
\r
8221 #define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT
\r
8224 /*** PORTAD1 - Port AD1 Register; 0x0000012F ***/
\r
8228 byte BIT0 :1; /* AN0 */
\r
8229 byte BIT1 :1; /* AN1 */
\r
8230 byte BIT2 :1; /* AN2 */
\r
8231 byte BIT3 :1; /* AN3 */
\r
8232 byte BIT4 :1; /* AN4 */
\r
8233 byte BIT5 :1; /* AN5 */
\r
8234 byte BIT6 :1; /* AN6 */
\r
8235 byte BIT7 :1; /* AN7 */
\r
8241 extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F);
\r
8242 #define PORTAD1 _PORTAD1.Byte
\r
8243 #define PORTAD1_BIT0 _PORTAD1.Bits.BIT0
\r
8244 #define PORTAD1_BIT1 _PORTAD1.Bits.BIT1
\r
8245 #define PORTAD1_BIT2 _PORTAD1.Bits.BIT2
\r
8246 #define PORTAD1_BIT3 _PORTAD1.Bits.BIT3
\r
8247 #define PORTAD1_BIT4 _PORTAD1.Bits.BIT4
\r
8248 #define PORTAD1_BIT5 _PORTAD1.Bits.BIT5
\r
8249 #define PORTAD1_BIT6 _PORTAD1.Bits.BIT6
\r
8250 #define PORTAD1_BIT7 _PORTAD1.Bits.BIT7
\r
8251 #define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT
\r
8254 /*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/
\r
8258 byte INITRQ :1; /* Initialization Mode Request */
\r
8259 byte SLPRQ :1; /* Sleep Mode Request */
\r
8260 byte WUPE :1; /* Wake-Up Enable */
\r
8261 byte TIME :1; /* Timer Enable */
\r
8262 byte SYNCH :1; /* Synchronized Status */
\r
8263 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
8264 byte RXACT :1; /* Receiver Active Status */
\r
8265 byte RXFRM :1; /* Received Frame Flag */
\r
8268 extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);
\r
8269 #define CAN0CTL0 _CAN0CTL0.Byte
\r
8270 #define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ
\r
8271 #define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ
\r
8272 #define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE
\r
8273 #define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME
\r
8274 #define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH
\r
8275 #define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI
\r
8276 #define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT
\r
8277 #define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM
\r
8280 /*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/
\r
8284 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
8285 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
8286 byte WUPM :1; /* Wake-Up Mode */
\r
8288 byte LISTEN :1; /* Listen Only Mode */
\r
8289 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
8290 byte CLKSRC :1; /* MSCAN 0 Clock Source */
\r
8291 byte CANE :1; /* MSCAN 0 Enable */
\r
8294 extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);
\r
8295 #define CAN0CTL1 _CAN0CTL1.Byte
\r
8296 #define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK
\r
8297 #define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK
\r
8298 #define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM
\r
8299 #define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN
\r
8300 #define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB
\r
8301 #define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC
\r
8302 #define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE
\r
8305 /*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/
\r
8309 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
8310 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
8311 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
8312 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
8313 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
8314 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
8315 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
8316 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
8323 extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);
\r
8324 #define CAN0BTR0 _CAN0BTR0.Byte
\r
8325 #define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0
\r
8326 #define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1
\r
8327 #define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2
\r
8328 #define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3
\r
8329 #define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4
\r
8330 #define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5
\r
8331 #define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0
\r
8332 #define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1
\r
8333 #define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP
\r
8334 #define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW
\r
8337 /*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/
\r
8341 byte TSEG10 :1; /* Time Segment 1 */
\r
8342 byte TSEG11 :1; /* Time Segment 1 */
\r
8343 byte TSEG12 :1; /* Time Segment 1 */
\r
8344 byte TSEG13 :1; /* Time Segment 1 */
\r
8345 byte TSEG20 :1; /* Time Segment 2 */
\r
8346 byte TSEG21 :1; /* Time Segment 2 */
\r
8347 byte TSEG22 :1; /* Time Segment 2 */
\r
8348 byte SAMP :1; /* Sampling */
\r
8351 byte grpTSEG_10 :4;
\r
8352 byte grpTSEG_20 :3;
\r
8356 extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);
\r
8357 #define CAN0BTR1 _CAN0BTR1.Byte
\r
8358 #define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10
\r
8359 #define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11
\r
8360 #define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12
\r
8361 #define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13
\r
8362 #define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20
\r
8363 #define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21
\r
8364 #define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22
\r
8365 #define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP
\r
8366 #define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10
\r
8367 #define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20
\r
8368 #define CAN0BTR1_TSEG CAN0BTR1_TSEG_10
\r
8371 /*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/
\r
8375 byte RXF :1; /* Receive Buffer Full */
\r
8376 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
8377 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
8378 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
8379 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
8380 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
8381 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
8382 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
8393 extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);
\r
8394 #define CAN0RFLG _CAN0RFLG.Byte
\r
8395 #define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF
\r
8396 #define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF
\r
8397 #define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0
\r
8398 #define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1
\r
8399 #define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0
\r
8400 #define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1
\r
8401 #define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF
\r
8402 #define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF
\r
8403 #define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT
\r
8404 #define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT
\r
8407 /*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/
\r
8411 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
8412 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
8413 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
8414 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
8415 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
8416 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
8417 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
8418 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
8423 byte grpTSTATE :2;
\r
8424 byte grpRSTATE :2;
\r
8429 extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145);
\r
8430 #define CAN0RIER _CAN0RIER.Byte
\r
8431 #define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE
\r
8432 #define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE
\r
8433 #define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0
\r
8434 #define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1
\r
8435 #define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0
\r
8436 #define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1
\r
8437 #define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE
\r
8438 #define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE
\r
8439 #define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE
\r
8440 #define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE
\r
8443 /*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/
\r
8447 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
8448 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
8449 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
8465 extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146);
\r
8466 #define CAN0TFLG _CAN0TFLG.Byte
\r
8467 #define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0
\r
8468 #define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1
\r
8469 #define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2
\r
8470 #define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE
\r
8473 /*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/
\r
8477 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
8478 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
8479 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
8495 extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147);
\r
8496 #define CAN0TIER _CAN0TIER.Byte
\r
8497 #define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0
\r
8498 #define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1
\r
8499 #define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2
\r
8500 #define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE
\r
8503 /*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/
\r
8507 byte ABTRQ0 :1; /* Abort Request 0 */
\r
8508 byte ABTRQ1 :1; /* Abort Request 1 */
\r
8509 byte ABTRQ2 :1; /* Abort Request 2 */
\r
8525 extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148);
\r
8526 #define CAN0TARQ _CAN0TARQ.Byte
\r
8527 #define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0
\r
8528 #define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1
\r
8529 #define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2
\r
8530 #define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ
\r
8533 /*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/
\r
8537 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
8538 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
8539 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
8555 extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149);
\r
8556 #define CAN0TAAK _CAN0TAAK.Byte
\r
8557 #define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0
\r
8558 #define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1
\r
8559 #define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2
\r
8560 #define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK
\r
8563 /*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/
\r
8567 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
8568 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
8569 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
8585 extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A);
\r
8586 #define CAN0TBSEL _CAN0TBSEL.Byte
\r
8587 #define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0
\r
8588 #define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1
\r
8589 #define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2
\r
8590 #define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX
\r
8593 /*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/
\r
8597 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
8598 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
8599 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
8601 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
8602 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
8614 extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B);
\r
8615 #define CAN0IDAC _CAN0IDAC.Byte
\r
8616 #define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0
\r
8617 #define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1
\r
8618 #define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2
\r
8619 #define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0
\r
8620 #define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1
\r
8621 #define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT
\r
8622 #define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM
\r
8625 /*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/
\r
8629 byte RXERR0 :1; /* Bit 0 */
\r
8630 byte RXERR1 :1; /* Bit 1 */
\r
8631 byte RXERR2 :1; /* Bit 2 */
\r
8632 byte RXERR3 :1; /* Bit 3 */
\r
8633 byte RXERR4 :1; /* Bit 4 */
\r
8634 byte RXERR5 :1; /* Bit 5 */
\r
8635 byte RXERR6 :1; /* Bit 6 */
\r
8636 byte RXERR7 :1; /* Bit 7 */
\r
8642 extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E);
\r
8643 #define CAN0RXERR _CAN0RXERR.Byte
\r
8644 #define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0
\r
8645 #define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1
\r
8646 #define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2
\r
8647 #define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3
\r
8648 #define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4
\r
8649 #define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5
\r
8650 #define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6
\r
8651 #define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7
\r
8652 #define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR
\r
8655 /*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/
\r
8659 byte TXERR0 :1; /* Bit 0 */
\r
8660 byte TXERR1 :1; /* Bit 1 */
\r
8661 byte TXERR2 :1; /* Bit 2 */
\r
8662 byte TXERR3 :1; /* Bit 3 */
\r
8663 byte TXERR4 :1; /* Bit 4 */
\r
8664 byte TXERR5 :1; /* Bit 5 */
\r
8665 byte TXERR6 :1; /* Bit 6 */
\r
8666 byte TXERR7 :1; /* Bit 7 */
\r
8672 extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F);
\r
8673 #define CAN0TXERR _CAN0TXERR.Byte
\r
8674 #define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0
\r
8675 #define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1
\r
8676 #define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2
\r
8677 #define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3
\r
8678 #define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4
\r
8679 #define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5
\r
8680 #define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6
\r
8681 #define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7
\r
8682 #define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR
\r
8685 /*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/
\r
8689 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8690 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8691 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8692 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8693 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8694 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8695 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8696 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8702 extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150);
\r
8703 #define CAN0IDAR0 _CAN0IDAR0.Byte
\r
8704 #define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0
\r
8705 #define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1
\r
8706 #define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2
\r
8707 #define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3
\r
8708 #define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4
\r
8709 #define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5
\r
8710 #define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6
\r
8711 #define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7
\r
8712 #define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC
\r
8715 /*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/
\r
8719 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8720 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8721 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8722 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8723 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8724 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8725 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8726 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8732 extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151);
\r
8733 #define CAN0IDAR1 _CAN0IDAR1.Byte
\r
8734 #define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0
\r
8735 #define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1
\r
8736 #define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2
\r
8737 #define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3
\r
8738 #define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4
\r
8739 #define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5
\r
8740 #define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6
\r
8741 #define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7
\r
8742 #define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC
\r
8745 /*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/
\r
8749 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8750 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8751 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8752 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8753 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8754 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8755 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8756 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8762 extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152);
\r
8763 #define CAN0IDAR2 _CAN0IDAR2.Byte
\r
8764 #define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0
\r
8765 #define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1
\r
8766 #define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2
\r
8767 #define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3
\r
8768 #define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4
\r
8769 #define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5
\r
8770 #define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6
\r
8771 #define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7
\r
8772 #define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC
\r
8775 /*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/
\r
8779 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8780 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8781 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8782 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8783 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8784 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8785 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8786 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8792 extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153);
\r
8793 #define CAN0IDAR3 _CAN0IDAR3.Byte
\r
8794 #define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0
\r
8795 #define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1
\r
8796 #define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2
\r
8797 #define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3
\r
8798 #define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4
\r
8799 #define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5
\r
8800 #define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6
\r
8801 #define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7
\r
8802 #define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC
\r
8805 /*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/
\r
8809 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
8810 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
8811 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
8812 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
8813 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
8814 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
8815 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
8816 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
8822 extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154);
\r
8823 #define CAN0IDMR0 _CAN0IDMR0.Byte
\r
8824 #define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0
\r
8825 #define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1
\r
8826 #define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2
\r
8827 #define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3
\r
8828 #define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4
\r
8829 #define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5
\r
8830 #define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6
\r
8831 #define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7
\r
8832 #define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM
\r
8835 /*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/
\r
8839 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
8840 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
8841 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
8842 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
8843 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
8844 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
8845 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
8846 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
8852 extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155);
\r
8853 #define CAN0IDMR1 _CAN0IDMR1.Byte
\r
8854 #define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0
\r
8855 #define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1
\r
8856 #define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2
\r
8857 #define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3
\r
8858 #define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4
\r
8859 #define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5
\r
8860 #define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6
\r
8861 #define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7
\r
8862 #define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM
\r
8865 /*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/
\r
8869 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
8870 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
8871 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
8872 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
8873 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
8874 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
8875 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
8876 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
8882 extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156);
\r
8883 #define CAN0IDMR2 _CAN0IDMR2.Byte
\r
8884 #define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0
\r
8885 #define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1
\r
8886 #define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2
\r
8887 #define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3
\r
8888 #define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4
\r
8889 #define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5
\r
8890 #define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6
\r
8891 #define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7
\r
8892 #define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM
\r
8895 /*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/
\r
8899 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
8900 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
8901 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
8902 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
8903 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
8904 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
8905 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
8906 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
8912 extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157);
\r
8913 #define CAN0IDMR3 _CAN0IDMR3.Byte
\r
8914 #define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0
\r
8915 #define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1
\r
8916 #define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2
\r
8917 #define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3
\r
8918 #define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4
\r
8919 #define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5
\r
8920 #define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6
\r
8921 #define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7
\r
8922 #define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM
\r
8925 /*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/
\r
8929 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8930 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8931 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8932 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8933 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8934 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8935 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8936 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8942 extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158);
\r
8943 #define CAN0IDAR4 _CAN0IDAR4.Byte
\r
8944 #define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0
\r
8945 #define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1
\r
8946 #define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2
\r
8947 #define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3
\r
8948 #define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4
\r
8949 #define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5
\r
8950 #define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6
\r
8951 #define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7
\r
8952 #define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC
\r
8955 /*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/
\r
8959 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8960 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8961 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8962 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8963 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8964 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8965 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8966 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
8972 extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159);
\r
8973 #define CAN0IDAR5 _CAN0IDAR5.Byte
\r
8974 #define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0
\r
8975 #define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1
\r
8976 #define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2
\r
8977 #define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3
\r
8978 #define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4
\r
8979 #define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5
\r
8980 #define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6
\r
8981 #define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7
\r
8982 #define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC
\r
8985 /*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/
\r
8989 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
8990 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
8991 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
8992 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
8993 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
8994 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
8995 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
8996 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
9002 extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A);
\r
9003 #define CAN0IDAR6 _CAN0IDAR6.Byte
\r
9004 #define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0
\r
9005 #define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1
\r
9006 #define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2
\r
9007 #define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3
\r
9008 #define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4
\r
9009 #define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5
\r
9010 #define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6
\r
9011 #define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7
\r
9012 #define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC
\r
9015 /*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/
\r
9019 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
9020 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
9021 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
9022 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
9023 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
9024 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
9025 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
9026 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
9032 extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B);
\r
9033 #define CAN0IDAR7 _CAN0IDAR7.Byte
\r
9034 #define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0
\r
9035 #define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1
\r
9036 #define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2
\r
9037 #define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3
\r
9038 #define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4
\r
9039 #define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5
\r
9040 #define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6
\r
9041 #define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7
\r
9042 #define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC
\r
9045 /*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/
\r
9049 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
9050 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
9051 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
9052 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
9053 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
9054 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
9055 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
9056 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
9062 extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C);
\r
9063 #define CAN0IDMR4 _CAN0IDMR4.Byte
\r
9064 #define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0
\r
9065 #define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1
\r
9066 #define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2
\r
9067 #define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3
\r
9068 #define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4
\r
9069 #define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5
\r
9070 #define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6
\r
9071 #define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7
\r
9072 #define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM
\r
9075 /*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/
\r
9079 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
9080 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
9081 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
9082 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
9083 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
9084 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
9085 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
9086 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
9092 extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D);
\r
9093 #define CAN0IDMR5 _CAN0IDMR5.Byte
\r
9094 #define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0
\r
9095 #define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1
\r
9096 #define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2
\r
9097 #define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3
\r
9098 #define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4
\r
9099 #define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5
\r
9100 #define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6
\r
9101 #define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7
\r
9102 #define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM
\r
9105 /*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/
\r
9109 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
9110 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
9111 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
9112 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
9113 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
9114 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
9115 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
9116 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
9122 extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E);
\r
9123 #define CAN0IDMR6 _CAN0IDMR6.Byte
\r
9124 #define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0
\r
9125 #define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1
\r
9126 #define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2
\r
9127 #define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3
\r
9128 #define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4
\r
9129 #define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5
\r
9130 #define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6
\r
9131 #define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7
\r
9132 #define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM
\r
9135 /*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/
\r
9139 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
9140 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
9141 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
9142 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
9143 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
9144 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
9145 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
9146 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
9152 extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F);
\r
9153 #define CAN0IDMR7 _CAN0IDMR7.Byte
\r
9154 #define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0
\r
9155 #define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1
\r
9156 #define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2
\r
9157 #define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3
\r
9158 #define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4
\r
9159 #define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5
\r
9160 #define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6
\r
9161 #define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7
\r
9162 #define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM
\r
9165 /*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/
\r
9169 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
9170 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
9171 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
9172 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
9173 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
9174 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
9175 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
9176 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
9182 extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160);
\r
9183 #define CAN0RXIDR0 _CAN0RXIDR0.Byte
\r
9184 #define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21
\r
9185 #define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22
\r
9186 #define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23
\r
9187 #define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24
\r
9188 #define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25
\r
9189 #define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26
\r
9190 #define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27
\r
9191 #define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28
\r
9192 #define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21
\r
9193 #define CAN0RXIDR0_ID CAN0RXIDR0_ID_21
\r
9196 /*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/
\r
9200 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
9201 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
9202 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
9203 byte IDE :1; /* ID Extended */
\r
9204 byte SRR :1; /* Substitute Remote Request */
\r
9205 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
9206 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
9207 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
9216 extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161);
\r
9217 #define CAN0RXIDR1 _CAN0RXIDR1.Byte
\r
9218 #define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15
\r
9219 #define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16
\r
9220 #define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17
\r
9221 #define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE
\r
9222 #define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR
\r
9223 #define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18
\r
9224 #define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19
\r
9225 #define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20
\r
9226 #define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15
\r
9227 #define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18
\r
9228 #define CAN0RXIDR1_ID CAN0RXIDR1_ID_15
\r
9231 /*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/
\r
9235 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
9236 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
9237 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
9238 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
9239 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
9240 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
9241 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
9242 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
9248 extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162);
\r
9249 #define CAN0RXIDR2 _CAN0RXIDR2.Byte
\r
9250 #define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7
\r
9251 #define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8
\r
9252 #define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9
\r
9253 #define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10
\r
9254 #define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11
\r
9255 #define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12
\r
9256 #define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13
\r
9257 #define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14
\r
9258 #define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7
\r
9259 #define CAN0RXIDR2_ID CAN0RXIDR2_ID_7
\r
9262 /*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/
\r
9266 byte RTR :1; /* Remote Transmission Request */
\r
9267 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
9268 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
9269 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
9270 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
9271 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
9272 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
9273 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
9280 extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163);
\r
9281 #define CAN0RXIDR3 _CAN0RXIDR3.Byte
\r
9282 #define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR
\r
9283 #define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0
\r
9284 #define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1
\r
9285 #define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2
\r
9286 #define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3
\r
9287 #define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4
\r
9288 #define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5
\r
9289 #define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6
\r
9290 #define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID
\r
9293 /*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/
\r
9297 byte DB0 :1; /* Data Bit 0 */
\r
9298 byte DB1 :1; /* Data Bit 1 */
\r
9299 byte DB2 :1; /* Data Bit 2 */
\r
9300 byte DB3 :1; /* Data Bit 3 */
\r
9301 byte DB4 :1; /* Data Bit 4 */
\r
9302 byte DB5 :1; /* Data Bit 5 */
\r
9303 byte DB6 :1; /* Data Bit 6 */
\r
9304 byte DB7 :1; /* Data Bit 7 */
\r
9310 extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164);
\r
9311 #define CAN0RXDSR0 _CAN0RXDSR0.Byte
\r
9312 #define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0
\r
9313 #define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1
\r
9314 #define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2
\r
9315 #define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3
\r
9316 #define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4
\r
9317 #define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5
\r
9318 #define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6
\r
9319 #define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7
\r
9320 #define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB
\r
9323 /*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/
\r
9327 byte DB0 :1; /* Data Bit 0 */
\r
9328 byte DB1 :1; /* Data Bit 1 */
\r
9329 byte DB2 :1; /* Data Bit 2 */
\r
9330 byte DB3 :1; /* Data Bit 3 */
\r
9331 byte DB4 :1; /* Data Bit 4 */
\r
9332 byte DB5 :1; /* Data Bit 5 */
\r
9333 byte DB6 :1; /* Data Bit 6 */
\r
9334 byte DB7 :1; /* Data Bit 7 */
\r
9340 extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165);
\r
9341 #define CAN0RXDSR1 _CAN0RXDSR1.Byte
\r
9342 #define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0
\r
9343 #define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1
\r
9344 #define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2
\r
9345 #define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3
\r
9346 #define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4
\r
9347 #define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5
\r
9348 #define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6
\r
9349 #define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7
\r
9350 #define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB
\r
9353 /*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/
\r
9357 byte DB0 :1; /* Data Bit 0 */
\r
9358 byte DB1 :1; /* Data Bit 1 */
\r
9359 byte DB2 :1; /* Data Bit 2 */
\r
9360 byte DB3 :1; /* Data Bit 3 */
\r
9361 byte DB4 :1; /* Data Bit 4 */
\r
9362 byte DB5 :1; /* Data Bit 5 */
\r
9363 byte DB6 :1; /* Data Bit 6 */
\r
9364 byte DB7 :1; /* Data Bit 7 */
\r
9370 extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166);
\r
9371 #define CAN0RXDSR2 _CAN0RXDSR2.Byte
\r
9372 #define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0
\r
9373 #define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1
\r
9374 #define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2
\r
9375 #define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3
\r
9376 #define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4
\r
9377 #define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5
\r
9378 #define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6
\r
9379 #define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7
\r
9380 #define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB
\r
9383 /*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/
\r
9387 byte DB0 :1; /* Data Bit 0 */
\r
9388 byte DB1 :1; /* Data Bit 1 */
\r
9389 byte DB2 :1; /* Data Bit 2 */
\r
9390 byte DB3 :1; /* Data Bit 3 */
\r
9391 byte DB4 :1; /* Data Bit 4 */
\r
9392 byte DB5 :1; /* Data Bit 5 */
\r
9393 byte DB6 :1; /* Data Bit 6 */
\r
9394 byte DB7 :1; /* Data Bit 7 */
\r
9400 extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167);
\r
9401 #define CAN0RXDSR3 _CAN0RXDSR3.Byte
\r
9402 #define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0
\r
9403 #define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1
\r
9404 #define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2
\r
9405 #define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3
\r
9406 #define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4
\r
9407 #define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5
\r
9408 #define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6
\r
9409 #define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7
\r
9410 #define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB
\r
9413 /*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/
\r
9417 byte DB0 :1; /* Data Bit 0 */
\r
9418 byte DB1 :1; /* Data Bit 1 */
\r
9419 byte DB2 :1; /* Data Bit 2 */
\r
9420 byte DB3 :1; /* Data Bit 3 */
\r
9421 byte DB4 :1; /* Data Bit 4 */
\r
9422 byte DB5 :1; /* Data Bit 5 */
\r
9423 byte DB6 :1; /* Data Bit 6 */
\r
9424 byte DB7 :1; /* Data Bit 7 */
\r
9430 extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168);
\r
9431 #define CAN0RXDSR4 _CAN0RXDSR4.Byte
\r
9432 #define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0
\r
9433 #define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1
\r
9434 #define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2
\r
9435 #define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3
\r
9436 #define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4
\r
9437 #define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5
\r
9438 #define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6
\r
9439 #define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7
\r
9440 #define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB
\r
9443 /*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/
\r
9447 byte DB0 :1; /* Data Bit 0 */
\r
9448 byte DB1 :1; /* Data Bit 1 */
\r
9449 byte DB2 :1; /* Data Bit 2 */
\r
9450 byte DB3 :1; /* Data Bit 3 */
\r
9451 byte DB4 :1; /* Data Bit 4 */
\r
9452 byte DB5 :1; /* Data Bit 5 */
\r
9453 byte DB6 :1; /* Data Bit 6 */
\r
9454 byte DB7 :1; /* Data Bit 7 */
\r
9460 extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169);
\r
9461 #define CAN0RXDSR5 _CAN0RXDSR5.Byte
\r
9462 #define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0
\r
9463 #define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1
\r
9464 #define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2
\r
9465 #define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3
\r
9466 #define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4
\r
9467 #define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5
\r
9468 #define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6
\r
9469 #define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7
\r
9470 #define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB
\r
9473 /*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/
\r
9477 byte DB0 :1; /* Data Bit 0 */
\r
9478 byte DB1 :1; /* Data Bit 1 */
\r
9479 byte DB2 :1; /* Data Bit 2 */
\r
9480 byte DB3 :1; /* Data Bit 3 */
\r
9481 byte DB4 :1; /* Data Bit 4 */
\r
9482 byte DB5 :1; /* Data Bit 5 */
\r
9483 byte DB6 :1; /* Data Bit 6 */
\r
9484 byte DB7 :1; /* Data Bit 7 */
\r
9490 extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A);
\r
9491 #define CAN0RXDSR6 _CAN0RXDSR6.Byte
\r
9492 #define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0
\r
9493 #define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1
\r
9494 #define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2
\r
9495 #define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3
\r
9496 #define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4
\r
9497 #define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5
\r
9498 #define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6
\r
9499 #define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7
\r
9500 #define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB
\r
9503 /*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/
\r
9507 byte DB0 :1; /* Data Bit 0 */
\r
9508 byte DB1 :1; /* Data Bit 1 */
\r
9509 byte DB2 :1; /* Data Bit 2 */
\r
9510 byte DB3 :1; /* Data Bit 3 */
\r
9511 byte DB4 :1; /* Data Bit 4 */
\r
9512 byte DB5 :1; /* Data Bit 5 */
\r
9513 byte DB6 :1; /* Data Bit 6 */
\r
9514 byte DB7 :1; /* Data Bit 7 */
\r
9520 extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B);
\r
9521 #define CAN0RXDSR7 _CAN0RXDSR7.Byte
\r
9522 #define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0
\r
9523 #define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1
\r
9524 #define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2
\r
9525 #define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3
\r
9526 #define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4
\r
9527 #define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5
\r
9528 #define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6
\r
9529 #define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7
\r
9530 #define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB
\r
9533 /*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/
\r
9537 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
9538 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
9539 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
9540 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
9554 extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C);
\r
9555 #define CAN0RXDLR _CAN0RXDLR.Byte
\r
9556 #define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0
\r
9557 #define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1
\r
9558 #define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2
\r
9559 #define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3
\r
9560 #define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC
\r
9563 /*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/
\r
9567 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
9568 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
9569 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
9570 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
9571 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
9572 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
9573 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
9574 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
9580 extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170);
\r
9581 #define CAN0TXIDR0 _CAN0TXIDR0.Byte
\r
9582 #define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21
\r
9583 #define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22
\r
9584 #define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23
\r
9585 #define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24
\r
9586 #define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25
\r
9587 #define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26
\r
9588 #define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27
\r
9589 #define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28
\r
9590 #define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21
\r
9591 #define CAN0TXIDR0_ID CAN0TXIDR0_ID_21
\r
9594 /*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/
\r
9598 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
9599 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
9600 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
9601 byte IDE :1; /* ID Extended */
\r
9602 byte SRR :1; /* Substitute Remote Request */
\r
9603 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
9604 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
9605 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
9614 extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171);
\r
9615 #define CAN0TXIDR1 _CAN0TXIDR1.Byte
\r
9616 #define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15
\r
9617 #define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16
\r
9618 #define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17
\r
9619 #define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE
\r
9620 #define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR
\r
9621 #define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18
\r
9622 #define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19
\r
9623 #define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20
\r
9624 #define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15
\r
9625 #define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18
\r
9626 #define CAN0TXIDR1_ID CAN0TXIDR1_ID_15
\r
9629 /*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/
\r
9633 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
9634 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
9635 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
9636 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
9637 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
9638 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
9639 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
9640 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
9646 extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172);
\r
9647 #define CAN0TXIDR2 _CAN0TXIDR2.Byte
\r
9648 #define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7
\r
9649 #define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8
\r
9650 #define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9
\r
9651 #define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10
\r
9652 #define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11
\r
9653 #define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12
\r
9654 #define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13
\r
9655 #define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14
\r
9656 #define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7
\r
9657 #define CAN0TXIDR2_ID CAN0TXIDR2_ID_7
\r
9660 /*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/
\r
9664 byte RTR :1; /* Remote Transmission Request */
\r
9665 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
9666 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
9667 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
9668 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
9669 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
9670 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
9671 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
9678 extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173);
\r
9679 #define CAN0TXIDR3 _CAN0TXIDR3.Byte
\r
9680 #define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR
\r
9681 #define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0
\r
9682 #define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1
\r
9683 #define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2
\r
9684 #define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3
\r
9685 #define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4
\r
9686 #define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5
\r
9687 #define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6
\r
9688 #define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID
\r
9691 /*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/
\r
9695 byte DB0 :1; /* Data Bit 0 */
\r
9696 byte DB1 :1; /* Data Bit 1 */
\r
9697 byte DB2 :1; /* Data Bit 2 */
\r
9698 byte DB3 :1; /* Data Bit 3 */
\r
9699 byte DB4 :1; /* Data Bit 4 */
\r
9700 byte DB5 :1; /* Data Bit 5 */
\r
9701 byte DB6 :1; /* Data Bit 6 */
\r
9702 byte DB7 :1; /* Data Bit 7 */
\r
9708 extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174);
\r
9709 #define CAN0TXDSR0 _CAN0TXDSR0.Byte
\r
9710 #define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0
\r
9711 #define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1
\r
9712 #define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2
\r
9713 #define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3
\r
9714 #define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4
\r
9715 #define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5
\r
9716 #define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6
\r
9717 #define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7
\r
9718 #define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB
\r
9721 /*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/
\r
9725 byte DB0 :1; /* Data Bit 0 */
\r
9726 byte DB1 :1; /* Data Bit 1 */
\r
9727 byte DB2 :1; /* Data Bit 2 */
\r
9728 byte DB3 :1; /* Data Bit 3 */
\r
9729 byte DB4 :1; /* Data Bit 4 */
\r
9730 byte DB5 :1; /* Data Bit 5 */
\r
9731 byte DB6 :1; /* Data Bit 6 */
\r
9732 byte DB7 :1; /* Data Bit 7 */
\r
9738 extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175);
\r
9739 #define CAN0TXDSR1 _CAN0TXDSR1.Byte
\r
9740 #define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0
\r
9741 #define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1
\r
9742 #define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2
\r
9743 #define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3
\r
9744 #define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4
\r
9745 #define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5
\r
9746 #define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6
\r
9747 #define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7
\r
9748 #define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB
\r
9751 /*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/
\r
9755 byte DB0 :1; /* Data Bit 0 */
\r
9756 byte DB1 :1; /* Data Bit 1 */
\r
9757 byte DB2 :1; /* Data Bit 2 */
\r
9758 byte DB3 :1; /* Data Bit 3 */
\r
9759 byte DB4 :1; /* Data Bit 4 */
\r
9760 byte DB5 :1; /* Data Bit 5 */
\r
9761 byte DB6 :1; /* Data Bit 6 */
\r
9762 byte DB7 :1; /* Data Bit 7 */
\r
9768 extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176);
\r
9769 #define CAN0TXDSR2 _CAN0TXDSR2.Byte
\r
9770 #define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0
\r
9771 #define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1
\r
9772 #define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2
\r
9773 #define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3
\r
9774 #define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4
\r
9775 #define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5
\r
9776 #define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6
\r
9777 #define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7
\r
9778 #define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB
\r
9781 /*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/
\r
9785 byte DB0 :1; /* Data Bit 0 */
\r
9786 byte DB1 :1; /* Data Bit 1 */
\r
9787 byte DB2 :1; /* Data Bit 2 */
\r
9788 byte DB3 :1; /* Data Bit 3 */
\r
9789 byte DB4 :1; /* Data Bit 4 */
\r
9790 byte DB5 :1; /* Data Bit 5 */
\r
9791 byte DB6 :1; /* Data Bit 6 */
\r
9792 byte DB7 :1; /* Data Bit 7 */
\r
9798 extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177);
\r
9799 #define CAN0TXDSR3 _CAN0TXDSR3.Byte
\r
9800 #define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0
\r
9801 #define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1
\r
9802 #define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2
\r
9803 #define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3
\r
9804 #define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4
\r
9805 #define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5
\r
9806 #define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6
\r
9807 #define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7
\r
9808 #define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB
\r
9811 /*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/
\r
9815 byte DB0 :1; /* Data Bit 0 */
\r
9816 byte DB1 :1; /* Data Bit 1 */
\r
9817 byte DB2 :1; /* Data Bit 2 */
\r
9818 byte DB3 :1; /* Data Bit 3 */
\r
9819 byte DB4 :1; /* Data Bit 4 */
\r
9820 byte DB5 :1; /* Data Bit 5 */
\r
9821 byte DB6 :1; /* Data Bit 6 */
\r
9822 byte DB7 :1; /* Data Bit 7 */
\r
9828 extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178);
\r
9829 #define CAN0TXDSR4 _CAN0TXDSR4.Byte
\r
9830 #define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0
\r
9831 #define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1
\r
9832 #define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2
\r
9833 #define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3
\r
9834 #define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4
\r
9835 #define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5
\r
9836 #define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6
\r
9837 #define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7
\r
9838 #define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB
\r
9841 /*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/
\r
9845 byte DB0 :1; /* Data Bit 0 */
\r
9846 byte DB1 :1; /* Data Bit 1 */
\r
9847 byte DB2 :1; /* Data Bit 2 */
\r
9848 byte DB3 :1; /* Data Bit 3 */
\r
9849 byte DB4 :1; /* Data Bit 4 */
\r
9850 byte DB5 :1; /* Data Bit 5 */
\r
9851 byte DB6 :1; /* Data Bit 6 */
\r
9852 byte DB7 :1; /* Data Bit 7 */
\r
9858 extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179);
\r
9859 #define CAN0TXDSR5 _CAN0TXDSR5.Byte
\r
9860 #define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0
\r
9861 #define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1
\r
9862 #define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2
\r
9863 #define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3
\r
9864 #define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4
\r
9865 #define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5
\r
9866 #define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6
\r
9867 #define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7
\r
9868 #define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB
\r
9871 /*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/
\r
9875 byte DB0 :1; /* Data Bit 0 */
\r
9876 byte DB1 :1; /* Data Bit 1 */
\r
9877 byte DB2 :1; /* Data Bit 2 */
\r
9878 byte DB3 :1; /* Data Bit 3 */
\r
9879 byte DB4 :1; /* Data Bit 4 */
\r
9880 byte DB5 :1; /* Data Bit 5 */
\r
9881 byte DB6 :1; /* Data Bit 6 */
\r
9882 byte DB7 :1; /* Data Bit 7 */
\r
9888 extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A);
\r
9889 #define CAN0TXDSR6 _CAN0TXDSR6.Byte
\r
9890 #define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0
\r
9891 #define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1
\r
9892 #define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2
\r
9893 #define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3
\r
9894 #define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4
\r
9895 #define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5
\r
9896 #define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6
\r
9897 #define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7
\r
9898 #define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB
\r
9901 /*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/
\r
9905 byte DB0 :1; /* Data Bit 0 */
\r
9906 byte DB1 :1; /* Data Bit 1 */
\r
9907 byte DB2 :1; /* Data Bit 2 */
\r
9908 byte DB3 :1; /* Data Bit 3 */
\r
9909 byte DB4 :1; /* Data Bit 4 */
\r
9910 byte DB5 :1; /* Data Bit 5 */
\r
9911 byte DB6 :1; /* Data Bit 6 */
\r
9912 byte DB7 :1; /* Data Bit 7 */
\r
9918 extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B);
\r
9919 #define CAN0TXDSR7 _CAN0TXDSR7.Byte
\r
9920 #define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0
\r
9921 #define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1
\r
9922 #define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2
\r
9923 #define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3
\r
9924 #define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4
\r
9925 #define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5
\r
9926 #define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6
\r
9927 #define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7
\r
9928 #define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB
\r
9931 /*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/
\r
9935 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
9936 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
9937 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
9938 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
9952 extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C);
\r
9953 #define CAN0TXDLR _CAN0TXDLR.Byte
\r
9954 #define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0
\r
9955 #define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1
\r
9956 #define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2
\r
9957 #define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3
\r
9958 #define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC
\r
9961 /*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/
\r
9965 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
9966 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
9967 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
9968 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
9969 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
9970 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
9971 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
9972 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
9978 extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F);
\r
9979 #define CAN0TXTBPR _CAN0TXTBPR.Byte
\r
9980 #define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0
\r
9981 #define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1
\r
9982 #define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2
\r
9983 #define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3
\r
9984 #define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4
\r
9985 #define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5
\r
9986 #define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6
\r
9987 #define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7
\r
9988 #define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO
\r
9991 /*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/
\r
9995 byte INITRQ :1; /* Initialization Mode Request */
\r
9996 byte SLPRQ :1; /* Sleep Mode Request */
\r
9997 byte WUPE :1; /* Wake-Up Enable */
\r
9998 byte TIME :1; /* Timer Enable */
\r
9999 byte SYNCH :1; /* Synchronized Status */
\r
10000 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
10001 byte RXACT :1; /* Receiver Active Status */
\r
10002 byte RXFRM :1; /* Received Frame Flag */
\r
10005 extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180);
\r
10006 #define CAN1CTL0 _CAN1CTL0.Byte
\r
10007 #define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ
\r
10008 #define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ
\r
10009 #define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE
\r
10010 #define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME
\r
10011 #define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH
\r
10012 #define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI
\r
10013 #define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT
\r
10014 #define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM
\r
10017 /*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/
\r
10021 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
10022 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
10023 byte WUPM :1; /* Wake-Up Mode */
\r
10025 byte LISTEN :1; /* Listen Only Mode */
\r
10026 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
10027 byte CLKSRC :1; /* MSCAN 1 Clock Source */
\r
10028 byte CANE :1; /* MSCAN 1 Enable */
\r
10031 extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181);
\r
10032 #define CAN1CTL1 _CAN1CTL1.Byte
\r
10033 #define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK
\r
10034 #define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK
\r
10035 #define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM
\r
10036 #define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN
\r
10037 #define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB
\r
10038 #define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC
\r
10039 #define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE
\r
10042 /*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/
\r
10046 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
10047 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
10048 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
10049 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
10050 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
10051 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
10052 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
10053 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
10060 extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182);
\r
10061 #define CAN1BTR0 _CAN1BTR0.Byte
\r
10062 #define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0
\r
10063 #define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1
\r
10064 #define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2
\r
10065 #define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3
\r
10066 #define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4
\r
10067 #define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5
\r
10068 #define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0
\r
10069 #define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1
\r
10070 #define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP
\r
10071 #define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW
\r
10074 /*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/
\r
10078 byte TSEG10 :1; /* Time Segment 1 */
\r
10079 byte TSEG11 :1; /* Time Segment 1 */
\r
10080 byte TSEG12 :1; /* Time Segment 1 */
\r
10081 byte TSEG13 :1; /* Time Segment 1 */
\r
10082 byte TSEG20 :1; /* Time Segment 2 */
\r
10083 byte TSEG21 :1; /* Time Segment 2 */
\r
10084 byte TSEG22 :1; /* Time Segment 2 */
\r
10085 byte SAMP :1; /* Sampling */
\r
10088 byte grpTSEG_10 :4;
\r
10089 byte grpTSEG_20 :3;
\r
10093 extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183);
\r
10094 #define CAN1BTR1 _CAN1BTR1.Byte
\r
10095 #define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10
\r
10096 #define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11
\r
10097 #define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12
\r
10098 #define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13
\r
10099 #define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20
\r
10100 #define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21
\r
10101 #define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22
\r
10102 #define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP
\r
10103 #define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10
\r
10104 #define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20
\r
10105 #define CAN1BTR1_TSEG CAN1BTR1_TSEG_10
\r
10108 /*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/
\r
10112 byte RXF :1; /* Receive Buffer Full */
\r
10113 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
10114 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
10115 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
10116 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
10117 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
10118 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
10119 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
10124 byte grpTSTAT :2;
\r
10125 byte grpRSTAT :2;
\r
10130 extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184);
\r
10131 #define CAN1RFLG _CAN1RFLG.Byte
\r
10132 #define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF
\r
10133 #define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF
\r
10134 #define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0
\r
10135 #define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1
\r
10136 #define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0
\r
10137 #define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1
\r
10138 #define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF
\r
10139 #define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF
\r
10140 #define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT
\r
10141 #define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT
\r
10144 /*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/
\r
10148 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
10149 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
10150 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
10151 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
10152 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
10153 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
10154 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
10155 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
10160 byte grpTSTATE :2;
\r
10161 byte grpRSTATE :2;
\r
10166 extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185);
\r
10167 #define CAN1RIER _CAN1RIER.Byte
\r
10168 #define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE
\r
10169 #define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE
\r
10170 #define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0
\r
10171 #define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1
\r
10172 #define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0
\r
10173 #define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1
\r
10174 #define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE
\r
10175 #define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE
\r
10176 #define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE
\r
10177 #define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE
\r
10180 /*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/
\r
10184 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
10185 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
10186 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
10202 extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186);
\r
10203 #define CAN1TFLG _CAN1TFLG.Byte
\r
10204 #define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0
\r
10205 #define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1
\r
10206 #define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2
\r
10207 #define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE
\r
10210 /*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/
\r
10214 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
10215 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
10216 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
10224 byte grpTXEIE :3;
\r
10232 extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187);
\r
10233 #define CAN1TIER _CAN1TIER.Byte
\r
10234 #define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0
\r
10235 #define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1
\r
10236 #define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2
\r
10237 #define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE
\r
10240 /*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/
\r
10244 byte ABTRQ0 :1; /* Abort Request 0 */
\r
10245 byte ABTRQ1 :1; /* Abort Request 1 */
\r
10246 byte ABTRQ2 :1; /* Abort Request 2 */
\r
10254 byte grpABTRQ :3;
\r
10262 extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188);
\r
10263 #define CAN1TARQ _CAN1TARQ.Byte
\r
10264 #define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0
\r
10265 #define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1
\r
10266 #define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2
\r
10267 #define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ
\r
10270 /*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/
\r
10274 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
10275 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
10276 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
10284 byte grpABTAK :3;
\r
10292 extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189);
\r
10293 #define CAN1TAAK _CAN1TAAK.Byte
\r
10294 #define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0
\r
10295 #define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1
\r
10296 #define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2
\r
10297 #define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK
\r
10300 /*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/
\r
10304 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
10305 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
10306 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
10322 extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A);
\r
10323 #define CAN1TBSEL _CAN1TBSEL.Byte
\r
10324 #define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0
\r
10325 #define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1
\r
10326 #define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2
\r
10327 #define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX
\r
10330 /*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/
\r
10334 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
10335 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
10336 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
10338 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
10339 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
10344 byte grpIDHIT :3;
\r
10351 extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B);
\r
10352 #define CAN1IDAC _CAN1IDAC.Byte
\r
10353 #define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0
\r
10354 #define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1
\r
10355 #define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2
\r
10356 #define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0
\r
10357 #define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1
\r
10358 #define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT
\r
10359 #define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM
\r
10362 /*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/
\r
10366 byte RXERR0 :1; /* Bit 0 */
\r
10367 byte RXERR1 :1; /* Bit 1 */
\r
10368 byte RXERR2 :1; /* Bit 2 */
\r
10369 byte RXERR3 :1; /* Bit 3 */
\r
10370 byte RXERR4 :1; /* Bit 4 */
\r
10371 byte RXERR5 :1; /* Bit 5 */
\r
10372 byte RXERR6 :1; /* Bit 6 */
\r
10373 byte RXERR7 :1; /* Bit 7 */
\r
10376 byte grpRXERR :8;
\r
10379 extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E);
\r
10380 #define CAN1RXERR _CAN1RXERR.Byte
\r
10381 #define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0
\r
10382 #define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1
\r
10383 #define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2
\r
10384 #define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3
\r
10385 #define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4
\r
10386 #define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5
\r
10387 #define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6
\r
10388 #define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7
\r
10389 #define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR
\r
10392 /*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/
\r
10396 byte TXERR0 :1; /* Bit 0 */
\r
10397 byte TXERR1 :1; /* Bit 1 */
\r
10398 byte TXERR2 :1; /* Bit 2 */
\r
10399 byte TXERR3 :1; /* Bit 3 */
\r
10400 byte TXERR4 :1; /* Bit 4 */
\r
10401 byte TXERR5 :1; /* Bit 5 */
\r
10402 byte TXERR6 :1; /* Bit 6 */
\r
10403 byte TXERR7 :1; /* Bit 7 */
\r
10406 byte grpTXERR :8;
\r
10409 extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F);
\r
10410 #define CAN1TXERR _CAN1TXERR.Byte
\r
10411 #define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0
\r
10412 #define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1
\r
10413 #define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2
\r
10414 #define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3
\r
10415 #define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4
\r
10416 #define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5
\r
10417 #define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6
\r
10418 #define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7
\r
10419 #define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR
\r
10422 /*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/
\r
10426 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10427 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10428 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10429 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10430 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10431 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10432 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10433 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10439 extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190);
\r
10440 #define CAN1IDAR0 _CAN1IDAR0.Byte
\r
10441 #define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0
\r
10442 #define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1
\r
10443 #define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2
\r
10444 #define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3
\r
10445 #define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4
\r
10446 #define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5
\r
10447 #define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6
\r
10448 #define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7
\r
10449 #define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC
\r
10452 /*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/
\r
10456 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10457 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10458 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10459 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10460 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10461 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10462 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10463 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10469 extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191);
\r
10470 #define CAN1IDAR1 _CAN1IDAR1.Byte
\r
10471 #define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0
\r
10472 #define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1
\r
10473 #define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2
\r
10474 #define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3
\r
10475 #define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4
\r
10476 #define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5
\r
10477 #define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6
\r
10478 #define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7
\r
10479 #define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC
\r
10482 /*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/
\r
10486 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10487 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10488 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10489 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10490 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10491 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10492 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10493 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10499 extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192);
\r
10500 #define CAN1IDAR2 _CAN1IDAR2.Byte
\r
10501 #define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0
\r
10502 #define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1
\r
10503 #define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2
\r
10504 #define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3
\r
10505 #define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4
\r
10506 #define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5
\r
10507 #define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6
\r
10508 #define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7
\r
10509 #define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC
\r
10512 /*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/
\r
10516 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10517 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10518 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10519 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10520 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10521 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10522 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10523 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10529 extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193);
\r
10530 #define CAN1IDAR3 _CAN1IDAR3.Byte
\r
10531 #define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0
\r
10532 #define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1
\r
10533 #define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2
\r
10534 #define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3
\r
10535 #define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4
\r
10536 #define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5
\r
10537 #define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6
\r
10538 #define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7
\r
10539 #define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC
\r
10542 /*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/
\r
10546 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10547 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10548 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10549 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10550 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10551 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10552 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10553 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10559 extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194);
\r
10560 #define CAN1IDMR0 _CAN1IDMR0.Byte
\r
10561 #define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0
\r
10562 #define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1
\r
10563 #define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2
\r
10564 #define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3
\r
10565 #define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4
\r
10566 #define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5
\r
10567 #define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6
\r
10568 #define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7
\r
10569 #define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM
\r
10572 /*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/
\r
10576 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10577 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10578 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10579 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10580 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10581 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10582 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10583 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10589 extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195);
\r
10590 #define CAN1IDMR1 _CAN1IDMR1.Byte
\r
10591 #define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0
\r
10592 #define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1
\r
10593 #define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2
\r
10594 #define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3
\r
10595 #define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4
\r
10596 #define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5
\r
10597 #define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6
\r
10598 #define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7
\r
10599 #define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM
\r
10602 /*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/
\r
10606 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10607 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10608 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10609 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10610 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10611 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10612 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10613 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10619 extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196);
\r
10620 #define CAN1IDMR2 _CAN1IDMR2.Byte
\r
10621 #define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0
\r
10622 #define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1
\r
10623 #define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2
\r
10624 #define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3
\r
10625 #define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4
\r
10626 #define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5
\r
10627 #define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6
\r
10628 #define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7
\r
10629 #define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM
\r
10632 /*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/
\r
10636 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10637 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10638 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10639 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10640 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10641 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10642 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10643 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10649 extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197);
\r
10650 #define CAN1IDMR3 _CAN1IDMR3.Byte
\r
10651 #define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0
\r
10652 #define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1
\r
10653 #define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2
\r
10654 #define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3
\r
10655 #define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4
\r
10656 #define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5
\r
10657 #define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6
\r
10658 #define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7
\r
10659 #define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM
\r
10662 /*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/
\r
10666 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10667 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10668 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10669 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10670 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10671 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10672 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10673 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10679 extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198);
\r
10680 #define CAN1IDAR4 _CAN1IDAR4.Byte
\r
10681 #define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0
\r
10682 #define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1
\r
10683 #define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2
\r
10684 #define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3
\r
10685 #define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4
\r
10686 #define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5
\r
10687 #define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6
\r
10688 #define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7
\r
10689 #define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC
\r
10692 /*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/
\r
10696 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10697 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10698 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10699 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10700 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10701 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10702 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10703 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10709 extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199);
\r
10710 #define CAN1IDAR5 _CAN1IDAR5.Byte
\r
10711 #define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0
\r
10712 #define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1
\r
10713 #define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2
\r
10714 #define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3
\r
10715 #define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4
\r
10716 #define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5
\r
10717 #define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6
\r
10718 #define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7
\r
10719 #define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC
\r
10722 /*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/
\r
10726 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10727 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10728 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10729 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10730 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10731 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10732 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10733 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10739 extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A);
\r
10740 #define CAN1IDAR6 _CAN1IDAR6.Byte
\r
10741 #define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0
\r
10742 #define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1
\r
10743 #define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2
\r
10744 #define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3
\r
10745 #define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4
\r
10746 #define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5
\r
10747 #define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6
\r
10748 #define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7
\r
10749 #define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC
\r
10752 /*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/
\r
10756 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
10757 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
10758 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
10759 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
10760 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
10761 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
10762 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
10763 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
10769 extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B);
\r
10770 #define CAN1IDAR7 _CAN1IDAR7.Byte
\r
10771 #define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0
\r
10772 #define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1
\r
10773 #define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2
\r
10774 #define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3
\r
10775 #define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4
\r
10776 #define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5
\r
10777 #define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6
\r
10778 #define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7
\r
10779 #define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC
\r
10782 /*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/
\r
10786 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10787 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10788 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10789 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10790 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10791 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10792 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10793 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10799 extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C);
\r
10800 #define CAN1IDMR4 _CAN1IDMR4.Byte
\r
10801 #define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0
\r
10802 #define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1
\r
10803 #define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2
\r
10804 #define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3
\r
10805 #define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4
\r
10806 #define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5
\r
10807 #define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6
\r
10808 #define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7
\r
10809 #define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM
\r
10812 /*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/
\r
10816 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10817 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10818 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10819 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10820 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10821 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10822 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10823 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10829 extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D);
\r
10830 #define CAN1IDMR5 _CAN1IDMR5.Byte
\r
10831 #define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0
\r
10832 #define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1
\r
10833 #define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2
\r
10834 #define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3
\r
10835 #define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4
\r
10836 #define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5
\r
10837 #define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6
\r
10838 #define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7
\r
10839 #define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM
\r
10842 /*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/
\r
10846 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10847 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10848 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10849 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10850 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10851 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10852 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10853 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10859 extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E);
\r
10860 #define CAN1IDMR6 _CAN1IDMR6.Byte
\r
10861 #define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0
\r
10862 #define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1
\r
10863 #define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2
\r
10864 #define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3
\r
10865 #define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4
\r
10866 #define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5
\r
10867 #define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6
\r
10868 #define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7
\r
10869 #define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM
\r
10872 /*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/
\r
10876 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
10877 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
10878 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
10879 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
10880 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
10881 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
10882 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
10883 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
10889 extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F);
\r
10890 #define CAN1IDMR7 _CAN1IDMR7.Byte
\r
10891 #define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0
\r
10892 #define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1
\r
10893 #define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2
\r
10894 #define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3
\r
10895 #define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4
\r
10896 #define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5
\r
10897 #define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6
\r
10898 #define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7
\r
10899 #define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM
\r
10902 /*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/
\r
10906 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
10907 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
10908 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
10909 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
10910 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
10911 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
10912 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
10913 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
10916 byte grpID_21 :8;
\r
10919 extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0);
\r
10920 #define CAN1RXIDR0 _CAN1RXIDR0.Byte
\r
10921 #define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21
\r
10922 #define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22
\r
10923 #define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23
\r
10924 #define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24
\r
10925 #define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25
\r
10926 #define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26
\r
10927 #define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27
\r
10928 #define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28
\r
10929 #define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21
\r
10930 #define CAN1RXIDR0_ID CAN1RXIDR0_ID_21
\r
10933 /*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/
\r
10937 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
10938 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
10939 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
10940 byte IDE :1; /* ID Extended */
\r
10941 byte SRR :1; /* Substitute Remote Request */
\r
10942 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
10943 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
10944 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
10947 byte grpID_15 :3;
\r
10950 byte grpID_18 :3;
\r
10953 extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1);
\r
10954 #define CAN1RXIDR1 _CAN1RXIDR1.Byte
\r
10955 #define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15
\r
10956 #define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16
\r
10957 #define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17
\r
10958 #define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE
\r
10959 #define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR
\r
10960 #define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18
\r
10961 #define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19
\r
10962 #define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20
\r
10963 #define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15
\r
10964 #define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18
\r
10965 #define CAN1RXIDR1_ID CAN1RXIDR1_ID_15
\r
10968 /*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/
\r
10972 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
10973 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
10974 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
10975 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
10976 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
10977 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
10978 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
10979 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
10985 extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2);
\r
10986 #define CAN1RXIDR2 _CAN1RXIDR2.Byte
\r
10987 #define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7
\r
10988 #define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8
\r
10989 #define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9
\r
10990 #define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10
\r
10991 #define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11
\r
10992 #define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12
\r
10993 #define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13
\r
10994 #define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14
\r
10995 #define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7
\r
10996 #define CAN1RXIDR2_ID CAN1RXIDR2_ID_7
\r
10999 /*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/
\r
11003 byte RTR :1; /* Remote Transmission Request */
\r
11004 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
11005 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
11006 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
11007 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
11008 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
11009 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
11010 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
11017 extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3);
\r
11018 #define CAN1RXIDR3 _CAN1RXIDR3.Byte
\r
11019 #define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR
\r
11020 #define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0
\r
11021 #define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1
\r
11022 #define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2
\r
11023 #define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3
\r
11024 #define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4
\r
11025 #define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5
\r
11026 #define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6
\r
11027 #define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID
\r
11030 /*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/
\r
11034 byte DB0 :1; /* Data Bit 0 */
\r
11035 byte DB1 :1; /* Data Bit 1 */
\r
11036 byte DB2 :1; /* Data Bit 2 */
\r
11037 byte DB3 :1; /* Data Bit 3 */
\r
11038 byte DB4 :1; /* Data Bit 4 */
\r
11039 byte DB5 :1; /* Data Bit 5 */
\r
11040 byte DB6 :1; /* Data Bit 6 */
\r
11041 byte DB7 :1; /* Data Bit 7 */
\r
11047 extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4);
\r
11048 #define CAN1RXDSR0 _CAN1RXDSR0.Byte
\r
11049 #define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0
\r
11050 #define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1
\r
11051 #define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2
\r
11052 #define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3
\r
11053 #define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4
\r
11054 #define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5
\r
11055 #define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6
\r
11056 #define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7
\r
11057 #define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB
\r
11060 /*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/
\r
11064 byte DB0 :1; /* Data Bit 0 */
\r
11065 byte DB1 :1; /* Data Bit 1 */
\r
11066 byte DB2 :1; /* Data Bit 2 */
\r
11067 byte DB3 :1; /* Data Bit 3 */
\r
11068 byte DB4 :1; /* Data Bit 4 */
\r
11069 byte DB5 :1; /* Data Bit 5 */
\r
11070 byte DB6 :1; /* Data Bit 6 */
\r
11071 byte DB7 :1; /* Data Bit 7 */
\r
11077 extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5);
\r
11078 #define CAN1RXDSR1 _CAN1RXDSR1.Byte
\r
11079 #define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0
\r
11080 #define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1
\r
11081 #define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2
\r
11082 #define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3
\r
11083 #define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4
\r
11084 #define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5
\r
11085 #define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6
\r
11086 #define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7
\r
11087 #define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB
\r
11090 /*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/
\r
11094 byte DB0 :1; /* Data Bit 0 */
\r
11095 byte DB1 :1; /* Data Bit 1 */
\r
11096 byte DB2 :1; /* Data Bit 2 */
\r
11097 byte DB3 :1; /* Data Bit 3 */
\r
11098 byte DB4 :1; /* Data Bit 4 */
\r
11099 byte DB5 :1; /* Data Bit 5 */
\r
11100 byte DB6 :1; /* Data Bit 6 */
\r
11101 byte DB7 :1; /* Data Bit 7 */
\r
11107 extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6);
\r
11108 #define CAN1RXDSR2 _CAN1RXDSR2.Byte
\r
11109 #define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0
\r
11110 #define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1
\r
11111 #define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2
\r
11112 #define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3
\r
11113 #define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4
\r
11114 #define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5
\r
11115 #define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6
\r
11116 #define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7
\r
11117 #define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB
\r
11120 /*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/
\r
11124 byte DB0 :1; /* Data Bit 0 */
\r
11125 byte DB1 :1; /* Data Bit 1 */
\r
11126 byte DB2 :1; /* Data Bit 2 */
\r
11127 byte DB3 :1; /* Data Bit 3 */
\r
11128 byte DB4 :1; /* Data Bit 4 */
\r
11129 byte DB5 :1; /* Data Bit 5 */
\r
11130 byte DB6 :1; /* Data Bit 6 */
\r
11131 byte DB7 :1; /* Data Bit 7 */
\r
11137 extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7);
\r
11138 #define CAN1RXDSR3 _CAN1RXDSR3.Byte
\r
11139 #define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0
\r
11140 #define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1
\r
11141 #define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2
\r
11142 #define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3
\r
11143 #define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4
\r
11144 #define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5
\r
11145 #define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6
\r
11146 #define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7
\r
11147 #define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB
\r
11150 /*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/
\r
11154 byte DB0 :1; /* Data Bit 0 */
\r
11155 byte DB1 :1; /* Data Bit 1 */
\r
11156 byte DB2 :1; /* Data Bit 2 */
\r
11157 byte DB3 :1; /* Data Bit 3 */
\r
11158 byte DB4 :1; /* Data Bit 4 */
\r
11159 byte DB5 :1; /* Data Bit 5 */
\r
11160 byte DB6 :1; /* Data Bit 6 */
\r
11161 byte DB7 :1; /* Data Bit 7 */
\r
11167 extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8);
\r
11168 #define CAN1RXDSR4 _CAN1RXDSR4.Byte
\r
11169 #define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0
\r
11170 #define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1
\r
11171 #define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2
\r
11172 #define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3
\r
11173 #define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4
\r
11174 #define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5
\r
11175 #define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6
\r
11176 #define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7
\r
11177 #define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB
\r
11180 /*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/
\r
11184 byte DB0 :1; /* Data Bit 0 */
\r
11185 byte DB1 :1; /* Data Bit 1 */
\r
11186 byte DB2 :1; /* Data Bit 2 */
\r
11187 byte DB3 :1; /* Data Bit 3 */
\r
11188 byte DB4 :1; /* Data Bit 4 */
\r
11189 byte DB5 :1; /* Data Bit 5 */
\r
11190 byte DB6 :1; /* Data Bit 6 */
\r
11191 byte DB7 :1; /* Data Bit 7 */
\r
11197 extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9);
\r
11198 #define CAN1RXDSR5 _CAN1RXDSR5.Byte
\r
11199 #define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0
\r
11200 #define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1
\r
11201 #define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2
\r
11202 #define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3
\r
11203 #define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4
\r
11204 #define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5
\r
11205 #define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6
\r
11206 #define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7
\r
11207 #define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB
\r
11210 /*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/
\r
11214 byte DB0 :1; /* Data Bit 0 */
\r
11215 byte DB1 :1; /* Data Bit 1 */
\r
11216 byte DB2 :1; /* Data Bit 2 */
\r
11217 byte DB3 :1; /* Data Bit 3 */
\r
11218 byte DB4 :1; /* Data Bit 4 */
\r
11219 byte DB5 :1; /* Data Bit 5 */
\r
11220 byte DB6 :1; /* Data Bit 6 */
\r
11221 byte DB7 :1; /* Data Bit 7 */
\r
11227 extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA);
\r
11228 #define CAN1RXDSR6 _CAN1RXDSR6.Byte
\r
11229 #define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0
\r
11230 #define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1
\r
11231 #define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2
\r
11232 #define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3
\r
11233 #define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4
\r
11234 #define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5
\r
11235 #define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6
\r
11236 #define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7
\r
11237 #define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB
\r
11240 /*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/
\r
11244 byte DB0 :1; /* Data Bit 0 */
\r
11245 byte DB1 :1; /* Data Bit 1 */
\r
11246 byte DB2 :1; /* Data Bit 2 */
\r
11247 byte DB3 :1; /* Data Bit 3 */
\r
11248 byte DB4 :1; /* Data Bit 4 */
\r
11249 byte DB5 :1; /* Data Bit 5 */
\r
11250 byte DB6 :1; /* Data Bit 6 */
\r
11251 byte DB7 :1; /* Data Bit 7 */
\r
11257 extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB);
\r
11258 #define CAN1RXDSR7 _CAN1RXDSR7.Byte
\r
11259 #define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0
\r
11260 #define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1
\r
11261 #define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2
\r
11262 #define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3
\r
11263 #define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4
\r
11264 #define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5
\r
11265 #define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6
\r
11266 #define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7
\r
11267 #define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB
\r
11270 /*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/
\r
11274 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
11275 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
11276 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
11277 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
11291 extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC);
\r
11292 #define CAN1RXDLR _CAN1RXDLR.Byte
\r
11293 #define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0
\r
11294 #define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1
\r
11295 #define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2
\r
11296 #define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3
\r
11297 #define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC
\r
11300 /*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/
\r
11304 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
11305 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
11306 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
11307 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
11308 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
11309 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
11310 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
11311 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
11314 byte grpID_21 :8;
\r
11317 extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0);
\r
11318 #define CAN1TXIDR0 _CAN1TXIDR0.Byte
\r
11319 #define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21
\r
11320 #define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22
\r
11321 #define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23
\r
11322 #define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24
\r
11323 #define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25
\r
11324 #define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26
\r
11325 #define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27
\r
11326 #define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28
\r
11327 #define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21
\r
11328 #define CAN1TXIDR0_ID CAN1TXIDR0_ID_21
\r
11331 /*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/
\r
11335 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
11336 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
11337 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
11338 byte IDE :1; /* ID Extended */
\r
11339 byte SRR :1; /* Substitute Remote Request */
\r
11340 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
11341 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
11342 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
11345 byte grpID_15 :3;
\r
11348 byte grpID_18 :3;
\r
11351 extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1);
\r
11352 #define CAN1TXIDR1 _CAN1TXIDR1.Byte
\r
11353 #define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15
\r
11354 #define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16
\r
11355 #define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17
\r
11356 #define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE
\r
11357 #define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR
\r
11358 #define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18
\r
11359 #define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19
\r
11360 #define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20
\r
11361 #define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15
\r
11362 #define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18
\r
11363 #define CAN1TXIDR1_ID CAN1TXIDR1_ID_15
\r
11366 /*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/
\r
11370 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
11371 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
11372 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
11373 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
11374 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
11375 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
11376 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
11377 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
11383 extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2);
\r
11384 #define CAN1TXIDR2 _CAN1TXIDR2.Byte
\r
11385 #define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7
\r
11386 #define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8
\r
11387 #define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9
\r
11388 #define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10
\r
11389 #define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11
\r
11390 #define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12
\r
11391 #define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13
\r
11392 #define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14
\r
11393 #define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7
\r
11394 #define CAN1TXIDR2_ID CAN1TXIDR2_ID_7
\r
11397 /*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/
\r
11401 byte RTR :1; /* Remote Transmission Request */
\r
11402 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
11403 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
11404 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
11405 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
11406 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
11407 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
11408 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
11415 extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3);
\r
11416 #define CAN1TXIDR3 _CAN1TXIDR3.Byte
\r
11417 #define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR
\r
11418 #define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0
\r
11419 #define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1
\r
11420 #define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2
\r
11421 #define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3
\r
11422 #define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4
\r
11423 #define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5
\r
11424 #define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6
\r
11425 #define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID
\r
11428 /*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/
\r
11432 byte DB0 :1; /* Data Bit 0 */
\r
11433 byte DB1 :1; /* Data Bit 1 */
\r
11434 byte DB2 :1; /* Data Bit 2 */
\r
11435 byte DB3 :1; /* Data Bit 3 */
\r
11436 byte DB4 :1; /* Data Bit 4 */
\r
11437 byte DB5 :1; /* Data Bit 5 */
\r
11438 byte DB6 :1; /* Data Bit 6 */
\r
11439 byte DB7 :1; /* Data Bit 7 */
\r
11445 extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4);
\r
11446 #define CAN1TXDSR0 _CAN1TXDSR0.Byte
\r
11447 #define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0
\r
11448 #define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1
\r
11449 #define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2
\r
11450 #define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3
\r
11451 #define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4
\r
11452 #define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5
\r
11453 #define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6
\r
11454 #define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7
\r
11455 #define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB
\r
11458 /*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/
\r
11462 byte DB0 :1; /* Data Bit 0 */
\r
11463 byte DB1 :1; /* Data Bit 1 */
\r
11464 byte DB2 :1; /* Data Bit 2 */
\r
11465 byte DB3 :1; /* Data Bit 3 */
\r
11466 byte DB4 :1; /* Data Bit 4 */
\r
11467 byte DB5 :1; /* Data Bit 5 */
\r
11468 byte DB6 :1; /* Data Bit 6 */
\r
11469 byte DB7 :1; /* Data Bit 7 */
\r
11475 extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5);
\r
11476 #define CAN1TXDSR1 _CAN1TXDSR1.Byte
\r
11477 #define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0
\r
11478 #define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1
\r
11479 #define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2
\r
11480 #define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3
\r
11481 #define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4
\r
11482 #define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5
\r
11483 #define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6
\r
11484 #define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7
\r
11485 #define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB
\r
11488 /*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/
\r
11492 byte DB0 :1; /* Data Bit 0 */
\r
11493 byte DB1 :1; /* Data Bit 1 */
\r
11494 byte DB2 :1; /* Data Bit 2 */
\r
11495 byte DB3 :1; /* Data Bit 3 */
\r
11496 byte DB4 :1; /* Data Bit 4 */
\r
11497 byte DB5 :1; /* Data Bit 5 */
\r
11498 byte DB6 :1; /* Data Bit 6 */
\r
11499 byte DB7 :1; /* Data Bit 7 */
\r
11505 extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6);
\r
11506 #define CAN1TXDSR2 _CAN1TXDSR2.Byte
\r
11507 #define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0
\r
11508 #define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1
\r
11509 #define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2
\r
11510 #define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3
\r
11511 #define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4
\r
11512 #define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5
\r
11513 #define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6
\r
11514 #define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7
\r
11515 #define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB
\r
11518 /*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/
\r
11522 byte DB0 :1; /* Data Bit 0 */
\r
11523 byte DB1 :1; /* Data Bit 1 */
\r
11524 byte DB2 :1; /* Data Bit 2 */
\r
11525 byte DB3 :1; /* Data Bit 3 */
\r
11526 byte DB4 :1; /* Data Bit 4 */
\r
11527 byte DB5 :1; /* Data Bit 5 */
\r
11528 byte DB6 :1; /* Data Bit 6 */
\r
11529 byte DB7 :1; /* Data Bit 7 */
\r
11535 extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7);
\r
11536 #define CAN1TXDSR3 _CAN1TXDSR3.Byte
\r
11537 #define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0
\r
11538 #define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1
\r
11539 #define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2
\r
11540 #define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3
\r
11541 #define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4
\r
11542 #define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5
\r
11543 #define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6
\r
11544 #define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7
\r
11545 #define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB
\r
11548 /*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/
\r
11552 byte DB0 :1; /* Data Bit 0 */
\r
11553 byte DB1 :1; /* Data Bit 1 */
\r
11554 byte DB2 :1; /* Data Bit 2 */
\r
11555 byte DB3 :1; /* Data Bit 3 */
\r
11556 byte DB4 :1; /* Data Bit 4 */
\r
11557 byte DB5 :1; /* Data Bit 5 */
\r
11558 byte DB6 :1; /* Data Bit 6 */
\r
11559 byte DB7 :1; /* Data Bit 7 */
\r
11565 extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8);
\r
11566 #define CAN1TXDSR4 _CAN1TXDSR4.Byte
\r
11567 #define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0
\r
11568 #define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1
\r
11569 #define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2
\r
11570 #define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3
\r
11571 #define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4
\r
11572 #define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5
\r
11573 #define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6
\r
11574 #define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7
\r
11575 #define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB
\r
11578 /*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/
\r
11582 byte DB0 :1; /* Data Bit 0 */
\r
11583 byte DB1 :1; /* Data Bit 1 */
\r
11584 byte DB2 :1; /* Data Bit 2 */
\r
11585 byte DB3 :1; /* Data Bit 3 */
\r
11586 byte DB4 :1; /* Data Bit 4 */
\r
11587 byte DB5 :1; /* Data Bit 5 */
\r
11588 byte DB6 :1; /* Data Bit 6 */
\r
11589 byte DB7 :1; /* Data Bit 7 */
\r
11595 extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9);
\r
11596 #define CAN1TXDSR5 _CAN1TXDSR5.Byte
\r
11597 #define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0
\r
11598 #define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1
\r
11599 #define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2
\r
11600 #define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3
\r
11601 #define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4
\r
11602 #define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5
\r
11603 #define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6
\r
11604 #define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7
\r
11605 #define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB
\r
11608 /*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/
\r
11612 byte DB0 :1; /* Data Bit 0 */
\r
11613 byte DB1 :1; /* Data Bit 1 */
\r
11614 byte DB2 :1; /* Data Bit 2 */
\r
11615 byte DB3 :1; /* Data Bit 3 */
\r
11616 byte DB4 :1; /* Data Bit 4 */
\r
11617 byte DB5 :1; /* Data Bit 5 */
\r
11618 byte DB6 :1; /* Data Bit 6 */
\r
11619 byte DB7 :1; /* Data Bit 7 */
\r
11625 extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA);
\r
11626 #define CAN1TXDSR6 _CAN1TXDSR6.Byte
\r
11627 #define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0
\r
11628 #define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1
\r
11629 #define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2
\r
11630 #define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3
\r
11631 #define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4
\r
11632 #define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5
\r
11633 #define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6
\r
11634 #define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7
\r
11635 #define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB
\r
11638 /*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/
\r
11642 byte DB0 :1; /* Data Bit 0 */
\r
11643 byte DB1 :1; /* Data Bit 1 */
\r
11644 byte DB2 :1; /* Data Bit 2 */
\r
11645 byte DB3 :1; /* Data Bit 3 */
\r
11646 byte DB4 :1; /* Data Bit 4 */
\r
11647 byte DB5 :1; /* Data Bit 5 */
\r
11648 byte DB6 :1; /* Data Bit 6 */
\r
11649 byte DB7 :1; /* Data Bit 7 */
\r
11655 extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB);
\r
11656 #define CAN1TXDSR7 _CAN1TXDSR7.Byte
\r
11657 #define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0
\r
11658 #define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1
\r
11659 #define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2
\r
11660 #define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3
\r
11661 #define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4
\r
11662 #define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5
\r
11663 #define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6
\r
11664 #define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7
\r
11665 #define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB
\r
11668 /*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/
\r
11672 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
11673 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
11674 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
11675 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
11689 extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC);
\r
11690 #define CAN1TXDLR _CAN1TXDLR.Byte
\r
11691 #define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0
\r
11692 #define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1
\r
11693 #define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2
\r
11694 #define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3
\r
11695 #define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC
\r
11698 /*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/
\r
11702 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
11703 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
11704 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
11705 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
11706 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
11707 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
11708 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
11709 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
11715 extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF);
\r
11716 #define CAN1TXTBPR _CAN1TXTBPR.Byte
\r
11717 #define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0
\r
11718 #define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1
\r
11719 #define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2
\r
11720 #define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3
\r
11721 #define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4
\r
11722 #define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5
\r
11723 #define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6
\r
11724 #define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7
\r
11725 #define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO
\r
11728 /*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/
\r
11732 byte INITRQ :1; /* Initialization Mode Request */
\r
11733 byte SLPRQ :1; /* Sleep Mode Request */
\r
11734 byte WUPE :1; /* Wake-Up Enable */
\r
11735 byte TIME :1; /* Timer Enable */
\r
11736 byte SYNCH :1; /* Synchronized Status */
\r
11737 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
11738 byte RXACT :1; /* Receiver Active Status */
\r
11739 byte RXFRM :1; /* Received Frame Flag */
\r
11742 extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0);
\r
11743 #define CAN2CTL0 _CAN2CTL0.Byte
\r
11744 #define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ
\r
11745 #define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ
\r
11746 #define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE
\r
11747 #define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME
\r
11748 #define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH
\r
11749 #define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI
\r
11750 #define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT
\r
11751 #define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM
\r
11754 /*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/
\r
11758 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
11759 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
11760 byte WUPM :1; /* Wake-Up Mode */
\r
11762 byte LISTEN :1; /* Listen Only Mode */
\r
11763 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
11764 byte CLKSRC :1; /* MSCAN 2 Clock Source */
\r
11765 byte CANE :1; /* MSCAN 2 Enable */
\r
11768 extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1);
\r
11769 #define CAN2CTL1 _CAN2CTL1.Byte
\r
11770 #define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK
\r
11771 #define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK
\r
11772 #define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM
\r
11773 #define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN
\r
11774 #define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB
\r
11775 #define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC
\r
11776 #define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE
\r
11779 /*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/
\r
11783 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
11784 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
11785 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
11786 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
11787 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
11788 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
11789 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
11790 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
11797 extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2);
\r
11798 #define CAN2BTR0 _CAN2BTR0.Byte
\r
11799 #define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0
\r
11800 #define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1
\r
11801 #define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2
\r
11802 #define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3
\r
11803 #define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4
\r
11804 #define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5
\r
11805 #define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0
\r
11806 #define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1
\r
11807 #define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP
\r
11808 #define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW
\r
11811 /*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/
\r
11815 byte TSEG10 :1; /* Time Segment 1 */
\r
11816 byte TSEG11 :1; /* Time Segment 1 */
\r
11817 byte TSEG12 :1; /* Time Segment 1 */
\r
11818 byte TSEG13 :1; /* Time Segment 1 */
\r
11819 byte TSEG20 :1; /* Time Segment 2 */
\r
11820 byte TSEG21 :1; /* Time Segment 2 */
\r
11821 byte TSEG22 :1; /* Time Segment 2 */
\r
11822 byte SAMP :1; /* Sampling */
\r
11825 byte grpTSEG_10 :4;
\r
11826 byte grpTSEG_20 :3;
\r
11830 extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3);
\r
11831 #define CAN2BTR1 _CAN2BTR1.Byte
\r
11832 #define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10
\r
11833 #define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11
\r
11834 #define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12
\r
11835 #define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13
\r
11836 #define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20
\r
11837 #define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21
\r
11838 #define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22
\r
11839 #define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP
\r
11840 #define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10
\r
11841 #define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20
\r
11842 #define CAN2BTR1_TSEG CAN2BTR1_TSEG_10
\r
11845 /*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/
\r
11849 byte RXF :1; /* Receive Buffer Full */
\r
11850 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
11851 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
11852 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
11853 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
11854 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
11855 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
11856 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
11861 byte grpTSTAT :2;
\r
11862 byte grpRSTAT :2;
\r
11867 extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4);
\r
11868 #define CAN2RFLG _CAN2RFLG.Byte
\r
11869 #define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF
\r
11870 #define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF
\r
11871 #define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0
\r
11872 #define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1
\r
11873 #define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0
\r
11874 #define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1
\r
11875 #define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF
\r
11876 #define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF
\r
11877 #define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT
\r
11878 #define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT
\r
11881 /*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/
\r
11885 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
11886 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
11887 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
11888 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
11889 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
11890 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
11891 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
11892 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
11897 byte grpTSTATE :2;
\r
11898 byte grpRSTATE :2;
\r
11903 extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5);
\r
11904 #define CAN2RIER _CAN2RIER.Byte
\r
11905 #define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE
\r
11906 #define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE
\r
11907 #define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0
\r
11908 #define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1
\r
11909 #define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0
\r
11910 #define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1
\r
11911 #define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE
\r
11912 #define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE
\r
11913 #define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE
\r
11914 #define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE
\r
11917 /*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/
\r
11921 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
11922 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
11923 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
11939 extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6);
\r
11940 #define CAN2TFLG _CAN2TFLG.Byte
\r
11941 #define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0
\r
11942 #define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1
\r
11943 #define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2
\r
11944 #define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE
\r
11947 /*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/
\r
11951 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
11952 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
11953 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
11961 byte grpTXEIE :3;
\r
11969 extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7);
\r
11970 #define CAN2TIER _CAN2TIER.Byte
\r
11971 #define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0
\r
11972 #define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1
\r
11973 #define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2
\r
11974 #define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE
\r
11977 /*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/
\r
11981 byte ABTRQ0 :1; /* Abort Request 0 */
\r
11982 byte ABTRQ1 :1; /* Abort Request 1 */
\r
11983 byte ABTRQ2 :1; /* Abort Request 2 */
\r
11991 byte grpABTRQ :3;
\r
11999 extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8);
\r
12000 #define CAN2TARQ _CAN2TARQ.Byte
\r
12001 #define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0
\r
12002 #define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1
\r
12003 #define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2
\r
12004 #define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ
\r
12007 /*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/
\r
12011 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
12012 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
12013 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
12021 byte grpABTAK :3;
\r
12029 extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9);
\r
12030 #define CAN2TAAK _CAN2TAAK.Byte
\r
12031 #define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0
\r
12032 #define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1
\r
12033 #define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2
\r
12034 #define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK
\r
12037 /*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/
\r
12041 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
12042 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
12043 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
12059 extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA);
\r
12060 #define CAN2TBSEL _CAN2TBSEL.Byte
\r
12061 #define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0
\r
12062 #define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1
\r
12063 #define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2
\r
12064 #define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX
\r
12067 /*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/
\r
12071 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
12072 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
12073 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
12075 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
12076 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
12081 byte grpIDHIT :3;
\r
12088 extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB);
\r
12089 #define CAN2IDAC _CAN2IDAC.Byte
\r
12090 #define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0
\r
12091 #define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1
\r
12092 #define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2
\r
12093 #define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0
\r
12094 #define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1
\r
12095 #define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT
\r
12096 #define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM
\r
12099 /*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/
\r
12103 byte RXERR0 :1; /* Bit 0 */
\r
12104 byte RXERR1 :1; /* Bit 1 */
\r
12105 byte RXERR2 :1; /* Bit 2 */
\r
12106 byte RXERR3 :1; /* Bit 3 */
\r
12107 byte RXERR4 :1; /* Bit 4 */
\r
12108 byte RXERR5 :1; /* Bit 5 */
\r
12109 byte RXERR6 :1; /* Bit 6 */
\r
12110 byte RXERR7 :1; /* Bit 7 */
\r
12113 byte grpRXERR :8;
\r
12116 extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE);
\r
12117 #define CAN2RXERR _CAN2RXERR.Byte
\r
12118 #define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0
\r
12119 #define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1
\r
12120 #define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2
\r
12121 #define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3
\r
12122 #define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4
\r
12123 #define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5
\r
12124 #define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6
\r
12125 #define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7
\r
12126 #define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR
\r
12129 /*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/
\r
12133 byte TXERR0 :1; /* Bit 0 */
\r
12134 byte TXERR1 :1; /* Bit 1 */
\r
12135 byte TXERR2 :1; /* Bit 2 */
\r
12136 byte TXERR3 :1; /* Bit 3 */
\r
12137 byte TXERR4 :1; /* Bit 4 */
\r
12138 byte TXERR5 :1; /* Bit 5 */
\r
12139 byte TXERR6 :1; /* Bit 6 */
\r
12140 byte TXERR7 :1; /* Bit 7 */
\r
12143 byte grpTXERR :8;
\r
12146 extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF);
\r
12147 #define CAN2TXERR _CAN2TXERR.Byte
\r
12148 #define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0
\r
12149 #define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1
\r
12150 #define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2
\r
12151 #define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3
\r
12152 #define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4
\r
12153 #define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5
\r
12154 #define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6
\r
12155 #define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7
\r
12156 #define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR
\r
12159 /*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/
\r
12163 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12164 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12165 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12166 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12167 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12168 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12169 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12170 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12176 extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0);
\r
12177 #define CAN2IDAR0 _CAN2IDAR0.Byte
\r
12178 #define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0
\r
12179 #define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1
\r
12180 #define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2
\r
12181 #define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3
\r
12182 #define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4
\r
12183 #define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5
\r
12184 #define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6
\r
12185 #define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7
\r
12186 #define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC
\r
12189 /*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/
\r
12193 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12194 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12195 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12196 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12197 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12198 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12199 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12200 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12206 extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1);
\r
12207 #define CAN2IDAR1 _CAN2IDAR1.Byte
\r
12208 #define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0
\r
12209 #define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1
\r
12210 #define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2
\r
12211 #define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3
\r
12212 #define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4
\r
12213 #define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5
\r
12214 #define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6
\r
12215 #define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7
\r
12216 #define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC
\r
12219 /*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/
\r
12223 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12224 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12225 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12226 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12227 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12228 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12229 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12230 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12236 extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2);
\r
12237 #define CAN2IDAR2 _CAN2IDAR2.Byte
\r
12238 #define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0
\r
12239 #define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1
\r
12240 #define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2
\r
12241 #define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3
\r
12242 #define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4
\r
12243 #define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5
\r
12244 #define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6
\r
12245 #define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7
\r
12246 #define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC
\r
12249 /*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/
\r
12253 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12254 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12255 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12256 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12257 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12258 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12259 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12260 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12266 extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3);
\r
12267 #define CAN2IDAR3 _CAN2IDAR3.Byte
\r
12268 #define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0
\r
12269 #define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1
\r
12270 #define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2
\r
12271 #define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3
\r
12272 #define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4
\r
12273 #define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5
\r
12274 #define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6
\r
12275 #define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7
\r
12276 #define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC
\r
12279 /*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/
\r
12283 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12284 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12285 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12286 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12287 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12288 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12289 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12290 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12296 extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4);
\r
12297 #define CAN2IDMR0 _CAN2IDMR0.Byte
\r
12298 #define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0
\r
12299 #define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1
\r
12300 #define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2
\r
12301 #define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3
\r
12302 #define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4
\r
12303 #define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5
\r
12304 #define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6
\r
12305 #define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7
\r
12306 #define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM
\r
12309 /*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/
\r
12313 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12314 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12315 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12316 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12317 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12318 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12319 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12320 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12326 extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5);
\r
12327 #define CAN2IDMR1 _CAN2IDMR1.Byte
\r
12328 #define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0
\r
12329 #define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1
\r
12330 #define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2
\r
12331 #define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3
\r
12332 #define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4
\r
12333 #define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5
\r
12334 #define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6
\r
12335 #define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7
\r
12336 #define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM
\r
12339 /*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/
\r
12343 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12344 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12345 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12346 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12347 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12348 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12349 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12350 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12356 extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6);
\r
12357 #define CAN2IDMR2 _CAN2IDMR2.Byte
\r
12358 #define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0
\r
12359 #define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1
\r
12360 #define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2
\r
12361 #define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3
\r
12362 #define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4
\r
12363 #define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5
\r
12364 #define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6
\r
12365 #define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7
\r
12366 #define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM
\r
12369 /*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/
\r
12373 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12374 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12375 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12376 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12377 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12378 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12379 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12380 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12386 extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7);
\r
12387 #define CAN2IDMR3 _CAN2IDMR3.Byte
\r
12388 #define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0
\r
12389 #define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1
\r
12390 #define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2
\r
12391 #define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3
\r
12392 #define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4
\r
12393 #define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5
\r
12394 #define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6
\r
12395 #define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7
\r
12396 #define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM
\r
12399 /*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/
\r
12403 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12404 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12405 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12406 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12407 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12408 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12409 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12410 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12416 extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8);
\r
12417 #define CAN2IDAR4 _CAN2IDAR4.Byte
\r
12418 #define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0
\r
12419 #define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1
\r
12420 #define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2
\r
12421 #define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3
\r
12422 #define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4
\r
12423 #define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5
\r
12424 #define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6
\r
12425 #define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7
\r
12426 #define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC
\r
12429 /*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/
\r
12433 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12434 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12435 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12436 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12437 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12438 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12439 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12440 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12446 extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9);
\r
12447 #define CAN2IDAR5 _CAN2IDAR5.Byte
\r
12448 #define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0
\r
12449 #define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1
\r
12450 #define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2
\r
12451 #define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3
\r
12452 #define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4
\r
12453 #define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5
\r
12454 #define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6
\r
12455 #define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7
\r
12456 #define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC
\r
12459 /*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/
\r
12463 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12464 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12465 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12466 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12467 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12468 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12469 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12470 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12476 extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA);
\r
12477 #define CAN2IDAR6 _CAN2IDAR6.Byte
\r
12478 #define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0
\r
12479 #define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1
\r
12480 #define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2
\r
12481 #define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3
\r
12482 #define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4
\r
12483 #define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5
\r
12484 #define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6
\r
12485 #define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7
\r
12486 #define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC
\r
12489 /*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/
\r
12493 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
12494 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
12495 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
12496 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
12497 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
12498 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
12499 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
12500 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
12506 extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB);
\r
12507 #define CAN2IDAR7 _CAN2IDAR7.Byte
\r
12508 #define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0
\r
12509 #define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1
\r
12510 #define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2
\r
12511 #define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3
\r
12512 #define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4
\r
12513 #define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5
\r
12514 #define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6
\r
12515 #define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7
\r
12516 #define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC
\r
12519 /*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/
\r
12523 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12524 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12525 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12526 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12527 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12528 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12529 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12530 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12536 extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC);
\r
12537 #define CAN2IDMR4 _CAN2IDMR4.Byte
\r
12538 #define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0
\r
12539 #define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1
\r
12540 #define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2
\r
12541 #define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3
\r
12542 #define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4
\r
12543 #define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5
\r
12544 #define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6
\r
12545 #define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7
\r
12546 #define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM
\r
12549 /*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/
\r
12553 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12554 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12555 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12556 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12557 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12558 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12559 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12560 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12566 extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD);
\r
12567 #define CAN2IDMR5 _CAN2IDMR5.Byte
\r
12568 #define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0
\r
12569 #define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1
\r
12570 #define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2
\r
12571 #define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3
\r
12572 #define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4
\r
12573 #define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5
\r
12574 #define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6
\r
12575 #define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7
\r
12576 #define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM
\r
12579 /*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/
\r
12583 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12584 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12585 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12586 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12587 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12588 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12589 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12590 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12596 extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE);
\r
12597 #define CAN2IDMR6 _CAN2IDMR6.Byte
\r
12598 #define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0
\r
12599 #define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1
\r
12600 #define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2
\r
12601 #define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3
\r
12602 #define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4
\r
12603 #define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5
\r
12604 #define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6
\r
12605 #define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7
\r
12606 #define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM
\r
12609 /*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/
\r
12613 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
12614 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
12615 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
12616 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
12617 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
12618 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
12619 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
12620 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
12626 extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF);
\r
12627 #define CAN2IDMR7 _CAN2IDMR7.Byte
\r
12628 #define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0
\r
12629 #define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1
\r
12630 #define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2
\r
12631 #define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3
\r
12632 #define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4
\r
12633 #define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5
\r
12634 #define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6
\r
12635 #define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7
\r
12636 #define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM
\r
12639 /*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/
\r
12643 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
12644 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
12645 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
12646 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
12647 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
12648 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
12649 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
12650 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
12653 byte grpID_21 :8;
\r
12656 extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0);
\r
12657 #define CAN2RXIDR0 _CAN2RXIDR0.Byte
\r
12658 #define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21
\r
12659 #define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22
\r
12660 #define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23
\r
12661 #define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24
\r
12662 #define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25
\r
12663 #define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26
\r
12664 #define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27
\r
12665 #define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28
\r
12666 #define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21
\r
12667 #define CAN2RXIDR0_ID CAN2RXIDR0_ID_21
\r
12670 /*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/
\r
12674 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
12675 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
12676 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
12677 byte IDE :1; /* ID Extended */
\r
12678 byte SRR :1; /* Substitute Remote Request */
\r
12679 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
12680 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
12681 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
12684 byte grpID_15 :3;
\r
12687 byte grpID_18 :3;
\r
12690 extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1);
\r
12691 #define CAN2RXIDR1 _CAN2RXIDR1.Byte
\r
12692 #define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15
\r
12693 #define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16
\r
12694 #define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17
\r
12695 #define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE
\r
12696 #define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR
\r
12697 #define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18
\r
12698 #define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19
\r
12699 #define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20
\r
12700 #define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15
\r
12701 #define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18
\r
12702 #define CAN2RXIDR1_ID CAN2RXIDR1_ID_15
\r
12705 /*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/
\r
12709 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
12710 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
12711 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
12712 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
12713 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
12714 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
12715 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
12716 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
12722 extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2);
\r
12723 #define CAN2RXIDR2 _CAN2RXIDR2.Byte
\r
12724 #define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7
\r
12725 #define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8
\r
12726 #define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9
\r
12727 #define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10
\r
12728 #define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11
\r
12729 #define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12
\r
12730 #define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13
\r
12731 #define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14
\r
12732 #define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7
\r
12733 #define CAN2RXIDR2_ID CAN2RXIDR2_ID_7
\r
12736 /*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/
\r
12740 byte RTR :1; /* Remote Transmission Request */
\r
12741 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
12742 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
12743 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
12744 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
12745 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
12746 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
12747 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
12754 extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3);
\r
12755 #define CAN2RXIDR3 _CAN2RXIDR3.Byte
\r
12756 #define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR
\r
12757 #define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0
\r
12758 #define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1
\r
12759 #define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2
\r
12760 #define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3
\r
12761 #define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4
\r
12762 #define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5
\r
12763 #define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6
\r
12764 #define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID
\r
12767 /*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/
\r
12771 byte DB0 :1; /* Data Bit 0 */
\r
12772 byte DB1 :1; /* Data Bit 1 */
\r
12773 byte DB2 :1; /* Data Bit 2 */
\r
12774 byte DB3 :1; /* Data Bit 3 */
\r
12775 byte DB4 :1; /* Data Bit 4 */
\r
12776 byte DB5 :1; /* Data Bit 5 */
\r
12777 byte DB6 :1; /* Data Bit 6 */
\r
12778 byte DB7 :1; /* Data Bit 7 */
\r
12784 extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4);
\r
12785 #define CAN2RXDSR0 _CAN2RXDSR0.Byte
\r
12786 #define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0
\r
12787 #define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1
\r
12788 #define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2
\r
12789 #define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3
\r
12790 #define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4
\r
12791 #define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5
\r
12792 #define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6
\r
12793 #define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7
\r
12794 #define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB
\r
12797 /*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/
\r
12801 byte DB0 :1; /* Data Bit 0 */
\r
12802 byte DB1 :1; /* Data Bit 1 */
\r
12803 byte DB2 :1; /* Data Bit 2 */
\r
12804 byte DB3 :1; /* Data Bit 3 */
\r
12805 byte DB4 :1; /* Data Bit 4 */
\r
12806 byte DB5 :1; /* Data Bit 5 */
\r
12807 byte DB6 :1; /* Data Bit 6 */
\r
12808 byte DB7 :1; /* Data Bit 7 */
\r
12814 extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5);
\r
12815 #define CAN2RXDSR1 _CAN2RXDSR1.Byte
\r
12816 #define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0
\r
12817 #define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1
\r
12818 #define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2
\r
12819 #define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3
\r
12820 #define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4
\r
12821 #define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5
\r
12822 #define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6
\r
12823 #define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7
\r
12824 #define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB
\r
12827 /*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/
\r
12831 byte DB0 :1; /* Data Bit 0 */
\r
12832 byte DB1 :1; /* Data Bit 1 */
\r
12833 byte DB2 :1; /* Data Bit 2 */
\r
12834 byte DB3 :1; /* Data Bit 3 */
\r
12835 byte DB4 :1; /* Data Bit 4 */
\r
12836 byte DB5 :1; /* Data Bit 5 */
\r
12837 byte DB6 :1; /* Data Bit 6 */
\r
12838 byte DB7 :1; /* Data Bit 7 */
\r
12844 extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6);
\r
12845 #define CAN2RXDSR2 _CAN2RXDSR2.Byte
\r
12846 #define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0
\r
12847 #define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1
\r
12848 #define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2
\r
12849 #define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3
\r
12850 #define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4
\r
12851 #define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5
\r
12852 #define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6
\r
12853 #define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7
\r
12854 #define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB
\r
12857 /*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/
\r
12861 byte DB0 :1; /* Data Bit 0 */
\r
12862 byte DB1 :1; /* Data Bit 1 */
\r
12863 byte DB2 :1; /* Data Bit 2 */
\r
12864 byte DB3 :1; /* Data Bit 3 */
\r
12865 byte DB4 :1; /* Data Bit 4 */
\r
12866 byte DB5 :1; /* Data Bit 5 */
\r
12867 byte DB6 :1; /* Data Bit 6 */
\r
12868 byte DB7 :1; /* Data Bit 7 */
\r
12874 extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7);
\r
12875 #define CAN2RXDSR3 _CAN2RXDSR3.Byte
\r
12876 #define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0
\r
12877 #define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1
\r
12878 #define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2
\r
12879 #define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3
\r
12880 #define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4
\r
12881 #define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5
\r
12882 #define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6
\r
12883 #define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7
\r
12884 #define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB
\r
12887 /*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/
\r
12891 byte DB0 :1; /* Data Bit 0 */
\r
12892 byte DB1 :1; /* Data Bit 1 */
\r
12893 byte DB2 :1; /* Data Bit 2 */
\r
12894 byte DB3 :1; /* Data Bit 3 */
\r
12895 byte DB4 :1; /* Data Bit 4 */
\r
12896 byte DB5 :1; /* Data Bit 5 */
\r
12897 byte DB6 :1; /* Data Bit 6 */
\r
12898 byte DB7 :1; /* Data Bit 7 */
\r
12904 extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8);
\r
12905 #define CAN2RXDSR4 _CAN2RXDSR4.Byte
\r
12906 #define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0
\r
12907 #define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1
\r
12908 #define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2
\r
12909 #define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3
\r
12910 #define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4
\r
12911 #define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5
\r
12912 #define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6
\r
12913 #define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7
\r
12914 #define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB
\r
12917 /*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/
\r
12921 byte DB0 :1; /* Data Bit 0 */
\r
12922 byte DB1 :1; /* Data Bit 1 */
\r
12923 byte DB2 :1; /* Data Bit 2 */
\r
12924 byte DB3 :1; /* Data Bit 3 */
\r
12925 byte DB4 :1; /* Data Bit 4 */
\r
12926 byte DB5 :1; /* Data Bit 5 */
\r
12927 byte DB6 :1; /* Data Bit 6 */
\r
12928 byte DB7 :1; /* Data Bit 7 */
\r
12934 extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9);
\r
12935 #define CAN2RXDSR5 _CAN2RXDSR5.Byte
\r
12936 #define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0
\r
12937 #define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1
\r
12938 #define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2
\r
12939 #define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3
\r
12940 #define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4
\r
12941 #define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5
\r
12942 #define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6
\r
12943 #define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7
\r
12944 #define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB
\r
12947 /*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/
\r
12951 byte DB0 :1; /* Data Bit 0 */
\r
12952 byte DB1 :1; /* Data Bit 1 */
\r
12953 byte DB2 :1; /* Data Bit 2 */
\r
12954 byte DB3 :1; /* Data Bit 3 */
\r
12955 byte DB4 :1; /* Data Bit 4 */
\r
12956 byte DB5 :1; /* Data Bit 5 */
\r
12957 byte DB6 :1; /* Data Bit 6 */
\r
12958 byte DB7 :1; /* Data Bit 7 */
\r
12964 extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA);
\r
12965 #define CAN2RXDSR6 _CAN2RXDSR6.Byte
\r
12966 #define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0
\r
12967 #define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1
\r
12968 #define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2
\r
12969 #define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3
\r
12970 #define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4
\r
12971 #define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5
\r
12972 #define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6
\r
12973 #define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7
\r
12974 #define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB
\r
12977 /*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/
\r
12981 byte DB0 :1; /* Data Bit 0 */
\r
12982 byte DB1 :1; /* Data Bit 1 */
\r
12983 byte DB2 :1; /* Data Bit 2 */
\r
12984 byte DB3 :1; /* Data Bit 3 */
\r
12985 byte DB4 :1; /* Data Bit 4 */
\r
12986 byte DB5 :1; /* Data Bit 5 */
\r
12987 byte DB6 :1; /* Data Bit 6 */
\r
12988 byte DB7 :1; /* Data Bit 7 */
\r
12994 extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB);
\r
12995 #define CAN2RXDSR7 _CAN2RXDSR7.Byte
\r
12996 #define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0
\r
12997 #define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1
\r
12998 #define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2
\r
12999 #define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3
\r
13000 #define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4
\r
13001 #define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5
\r
13002 #define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6
\r
13003 #define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7
\r
13004 #define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB
\r
13007 /*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/
\r
13011 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
13012 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
13013 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
13014 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
13028 extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC);
\r
13029 #define CAN2RXDLR _CAN2RXDLR.Byte
\r
13030 #define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0
\r
13031 #define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1
\r
13032 #define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2
\r
13033 #define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3
\r
13034 #define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC
\r
13037 /*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/
\r
13041 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
13042 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
13043 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
13044 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
13045 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
13046 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
13047 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
13048 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
13051 byte grpID_21 :8;
\r
13054 extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0);
\r
13055 #define CAN2TXIDR0 _CAN2TXIDR0.Byte
\r
13056 #define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21
\r
13057 #define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22
\r
13058 #define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23
\r
13059 #define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24
\r
13060 #define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25
\r
13061 #define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26
\r
13062 #define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27
\r
13063 #define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28
\r
13064 #define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21
\r
13065 #define CAN2TXIDR0_ID CAN2TXIDR0_ID_21
\r
13068 /*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/
\r
13072 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
13073 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
13074 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
13075 byte IDE :1; /* ID Extended */
\r
13076 byte SRR :1; /* Substitute Remote Request */
\r
13077 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
13078 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
13079 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
13082 byte grpID_15 :3;
\r
13085 byte grpID_18 :3;
\r
13088 extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1);
\r
13089 #define CAN2TXIDR1 _CAN2TXIDR1.Byte
\r
13090 #define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15
\r
13091 #define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16
\r
13092 #define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17
\r
13093 #define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE
\r
13094 #define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR
\r
13095 #define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18
\r
13096 #define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19
\r
13097 #define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20
\r
13098 #define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15
\r
13099 #define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18
\r
13100 #define CAN2TXIDR1_ID CAN2TXIDR1_ID_15
\r
13103 /*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/
\r
13107 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
13108 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
13109 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
13110 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
13111 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
13112 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
13113 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
13114 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
13120 extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2);
\r
13121 #define CAN2TXIDR2 _CAN2TXIDR2.Byte
\r
13122 #define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7
\r
13123 #define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8
\r
13124 #define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9
\r
13125 #define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10
\r
13126 #define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11
\r
13127 #define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12
\r
13128 #define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13
\r
13129 #define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14
\r
13130 #define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7
\r
13131 #define CAN2TXIDR2_ID CAN2TXIDR2_ID_7
\r
13134 /*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/
\r
13138 byte RTR :1; /* Remote Transmission Request */
\r
13139 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
13140 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
13141 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
13142 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
13143 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
13144 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
13145 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
13152 extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3);
\r
13153 #define CAN2TXIDR3 _CAN2TXIDR3.Byte
\r
13154 #define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR
\r
13155 #define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0
\r
13156 #define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1
\r
13157 #define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2
\r
13158 #define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3
\r
13159 #define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4
\r
13160 #define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5
\r
13161 #define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6
\r
13162 #define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID
\r
13165 /*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/
\r
13169 byte DB0 :1; /* Data Bit 0 */
\r
13170 byte DB1 :1; /* Data Bit 1 */
\r
13171 byte DB2 :1; /* Data Bit 2 */
\r
13172 byte DB3 :1; /* Data Bit 3 */
\r
13173 byte DB4 :1; /* Data Bit 4 */
\r
13174 byte DB5 :1; /* Data Bit 5 */
\r
13175 byte DB6 :1; /* Data Bit 6 */
\r
13176 byte DB7 :1; /* Data Bit 7 */
\r
13182 extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4);
\r
13183 #define CAN2TXDSR0 _CAN2TXDSR0.Byte
\r
13184 #define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0
\r
13185 #define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1
\r
13186 #define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2
\r
13187 #define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3
\r
13188 #define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4
\r
13189 #define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5
\r
13190 #define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6
\r
13191 #define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7
\r
13192 #define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB
\r
13195 /*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/
\r
13199 byte DB0 :1; /* Data Bit 0 */
\r
13200 byte DB1 :1; /* Data Bit 1 */
\r
13201 byte DB2 :1; /* Data Bit 2 */
\r
13202 byte DB3 :1; /* Data Bit 3 */
\r
13203 byte DB4 :1; /* Data Bit 4 */
\r
13204 byte DB5 :1; /* Data Bit 5 */
\r
13205 byte DB6 :1; /* Data Bit 6 */
\r
13206 byte DB7 :1; /* Data Bit 7 */
\r
13212 extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5);
\r
13213 #define CAN2TXDSR1 _CAN2TXDSR1.Byte
\r
13214 #define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0
\r
13215 #define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1
\r
13216 #define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2
\r
13217 #define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3
\r
13218 #define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4
\r
13219 #define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5
\r
13220 #define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6
\r
13221 #define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7
\r
13222 #define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB
\r
13225 /*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/
\r
13229 byte DB0 :1; /* Data Bit 0 */
\r
13230 byte DB1 :1; /* Data Bit 1 */
\r
13231 byte DB2 :1; /* Data Bit 2 */
\r
13232 byte DB3 :1; /* Data Bit 3 */
\r
13233 byte DB4 :1; /* Data Bit 4 */
\r
13234 byte DB5 :1; /* Data Bit 5 */
\r
13235 byte DB6 :1; /* Data Bit 6 */
\r
13236 byte DB7 :1; /* Data Bit 7 */
\r
13242 extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6);
\r
13243 #define CAN2TXDSR2 _CAN2TXDSR2.Byte
\r
13244 #define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0
\r
13245 #define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1
\r
13246 #define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2
\r
13247 #define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3
\r
13248 #define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4
\r
13249 #define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5
\r
13250 #define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6
\r
13251 #define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7
\r
13252 #define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB
\r
13255 /*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/
\r
13259 byte DB0 :1; /* Data Bit 0 */
\r
13260 byte DB1 :1; /* Data Bit 1 */
\r
13261 byte DB2 :1; /* Data Bit 2 */
\r
13262 byte DB3 :1; /* Data Bit 3 */
\r
13263 byte DB4 :1; /* Data Bit 4 */
\r
13264 byte DB5 :1; /* Data Bit 5 */
\r
13265 byte DB6 :1; /* Data Bit 6 */
\r
13266 byte DB7 :1; /* Data Bit 7 */
\r
13272 extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7);
\r
13273 #define CAN2TXDSR3 _CAN2TXDSR3.Byte
\r
13274 #define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0
\r
13275 #define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1
\r
13276 #define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2
\r
13277 #define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3
\r
13278 #define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4
\r
13279 #define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5
\r
13280 #define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6
\r
13281 #define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7
\r
13282 #define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB
\r
13285 /*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/
\r
13289 byte DB0 :1; /* Data Bit 0 */
\r
13290 byte DB1 :1; /* Data Bit 1 */
\r
13291 byte DB2 :1; /* Data Bit 2 */
\r
13292 byte DB3 :1; /* Data Bit 3 */
\r
13293 byte DB4 :1; /* Data Bit 4 */
\r
13294 byte DB5 :1; /* Data Bit 5 */
\r
13295 byte DB6 :1; /* Data Bit 6 */
\r
13296 byte DB7 :1; /* Data Bit 7 */
\r
13302 extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8);
\r
13303 #define CAN2TXDSR4 _CAN2TXDSR4.Byte
\r
13304 #define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0
\r
13305 #define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1
\r
13306 #define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2
\r
13307 #define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3
\r
13308 #define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4
\r
13309 #define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5
\r
13310 #define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6
\r
13311 #define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7
\r
13312 #define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB
\r
13315 /*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/
\r
13319 byte DB0 :1; /* Data Bit 0 */
\r
13320 byte DB1 :1; /* Data Bit 1 */
\r
13321 byte DB2 :1; /* Data Bit 2 */
\r
13322 byte DB3 :1; /* Data Bit 3 */
\r
13323 byte DB4 :1; /* Data Bit 4 */
\r
13324 byte DB5 :1; /* Data Bit 5 */
\r
13325 byte DB6 :1; /* Data Bit 6 */
\r
13326 byte DB7 :1; /* Data Bit 7 */
\r
13332 extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9);
\r
13333 #define CAN2TXDSR5 _CAN2TXDSR5.Byte
\r
13334 #define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0
\r
13335 #define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1
\r
13336 #define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2
\r
13337 #define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3
\r
13338 #define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4
\r
13339 #define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5
\r
13340 #define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6
\r
13341 #define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7
\r
13342 #define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB
\r
13345 /*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/
\r
13349 byte DB0 :1; /* Data Bit 0 */
\r
13350 byte DB1 :1; /* Data Bit 1 */
\r
13351 byte DB2 :1; /* Data Bit 2 */
\r
13352 byte DB3 :1; /* Data Bit 3 */
\r
13353 byte DB4 :1; /* Data Bit 4 */
\r
13354 byte DB5 :1; /* Data Bit 5 */
\r
13355 byte DB6 :1; /* Data Bit 6 */
\r
13356 byte DB7 :1; /* Data Bit 7 */
\r
13362 extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA);
\r
13363 #define CAN2TXDSR6 _CAN2TXDSR6.Byte
\r
13364 #define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0
\r
13365 #define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1
\r
13366 #define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2
\r
13367 #define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3
\r
13368 #define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4
\r
13369 #define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5
\r
13370 #define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6
\r
13371 #define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7
\r
13372 #define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB
\r
13375 /*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/
\r
13379 byte DB0 :1; /* Data Bit 0 */
\r
13380 byte DB1 :1; /* Data Bit 1 */
\r
13381 byte DB2 :1; /* Data Bit 2 */
\r
13382 byte DB3 :1; /* Data Bit 3 */
\r
13383 byte DB4 :1; /* Data Bit 4 */
\r
13384 byte DB5 :1; /* Data Bit 5 */
\r
13385 byte DB6 :1; /* Data Bit 6 */
\r
13386 byte DB7 :1; /* Data Bit 7 */
\r
13392 extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB);
\r
13393 #define CAN2TXDSR7 _CAN2TXDSR7.Byte
\r
13394 #define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0
\r
13395 #define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1
\r
13396 #define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2
\r
13397 #define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3
\r
13398 #define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4
\r
13399 #define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5
\r
13400 #define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6
\r
13401 #define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7
\r
13402 #define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB
\r
13405 /*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/
\r
13409 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
13410 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
13411 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
13412 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
13426 extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC);
\r
13427 #define CAN2TXDLR _CAN2TXDLR.Byte
\r
13428 #define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0
\r
13429 #define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1
\r
13430 #define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2
\r
13431 #define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3
\r
13432 #define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC
\r
13435 /*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/
\r
13439 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
13440 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
13441 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
13442 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
13443 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
13444 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
13445 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
13446 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
13452 extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF);
\r
13453 #define CAN2TXTBPR _CAN2TXTBPR.Byte
\r
13454 #define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0
\r
13455 #define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1
\r
13456 #define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2
\r
13457 #define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3
\r
13458 #define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4
\r
13459 #define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5
\r
13460 #define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6
\r
13461 #define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7
\r
13462 #define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO
\r
13465 /*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/
\r
13469 byte INITRQ :1; /* Initialization Mode Request */
\r
13470 byte SLPRQ :1; /* Sleep Mode Request */
\r
13471 byte WUPE :1; /* Wake-Up Enable */
\r
13472 byte TIME :1; /* Timer Enable */
\r
13473 byte SYNCH :1; /* Synchronized Status */
\r
13474 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
13475 byte RXACT :1; /* Receiver Active Status */
\r
13476 byte RXFRM :1; /* Received Frame Flag */
\r
13479 extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200);
\r
13480 #define CAN3CTL0 _CAN3CTL0.Byte
\r
13481 #define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ
\r
13482 #define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ
\r
13483 #define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE
\r
13484 #define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME
\r
13485 #define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH
\r
13486 #define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI
\r
13487 #define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT
\r
13488 #define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM
\r
13491 /*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/
\r
13495 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
13496 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
13497 byte WUPM :1; /* Wake-Up Mode */
\r
13499 byte LISTEN :1; /* Listen Only Mode */
\r
13500 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
13501 byte CLKSRC :1; /* MSCAN 3 Clock Source */
\r
13502 byte CANE :1; /* MSCAN 3 Enable */
\r
13505 extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201);
\r
13506 #define CAN3CTL1 _CAN3CTL1.Byte
\r
13507 #define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK
\r
13508 #define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK
\r
13509 #define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM
\r
13510 #define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN
\r
13511 #define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB
\r
13512 #define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC
\r
13513 #define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE
\r
13516 /*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/
\r
13520 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
13521 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
13522 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
13523 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
13524 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
13525 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
13526 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
13527 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
13534 extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202);
\r
13535 #define CAN3BTR0 _CAN3BTR0.Byte
\r
13536 #define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0
\r
13537 #define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1
\r
13538 #define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2
\r
13539 #define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3
\r
13540 #define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4
\r
13541 #define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5
\r
13542 #define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0
\r
13543 #define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1
\r
13544 #define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP
\r
13545 #define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW
\r
13548 /*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/
\r
13552 byte TSEG10 :1; /* Time Segment 1 */
\r
13553 byte TSEG11 :1; /* Time Segment 1 */
\r
13554 byte TSEG12 :1; /* Time Segment 1 */
\r
13555 byte TSEG13 :1; /* Time Segment 1 */
\r
13556 byte TSEG20 :1; /* Time Segment 2 */
\r
13557 byte TSEG21 :1; /* Time Segment 2 */
\r
13558 byte TSEG22 :1; /* Time Segment 2 */
\r
13559 byte SAMP :1; /* Sampling */
\r
13562 byte grpTSEG_10 :4;
\r
13563 byte grpTSEG_20 :3;
\r
13567 extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203);
\r
13568 #define CAN3BTR1 _CAN3BTR1.Byte
\r
13569 #define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10
\r
13570 #define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11
\r
13571 #define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12
\r
13572 #define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13
\r
13573 #define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20
\r
13574 #define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21
\r
13575 #define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22
\r
13576 #define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP
\r
13577 #define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10
\r
13578 #define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20
\r
13579 #define CAN3BTR1_TSEG CAN3BTR1_TSEG_10
\r
13582 /*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/
\r
13586 byte RXF :1; /* Receive Buffer Full */
\r
13587 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
13588 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
13589 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
13590 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
13591 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
13592 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
13593 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
13598 byte grpTSTAT :2;
\r
13599 byte grpRSTAT :2;
\r
13604 extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204);
\r
13605 #define CAN3RFLG _CAN3RFLG.Byte
\r
13606 #define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF
\r
13607 #define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF
\r
13608 #define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0
\r
13609 #define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1
\r
13610 #define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0
\r
13611 #define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1
\r
13612 #define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF
\r
13613 #define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF
\r
13614 #define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT
\r
13615 #define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT
\r
13618 /*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/
\r
13622 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
13623 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
13624 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
13625 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
13626 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
13627 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
13628 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
13629 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
13634 byte grpTSTATE :2;
\r
13635 byte grpRSTATE :2;
\r
13640 extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205);
\r
13641 #define CAN3RIER _CAN3RIER.Byte
\r
13642 #define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE
\r
13643 #define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE
\r
13644 #define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0
\r
13645 #define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1
\r
13646 #define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0
\r
13647 #define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1
\r
13648 #define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE
\r
13649 #define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE
\r
13650 #define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE
\r
13651 #define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE
\r
13654 /*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/
\r
13658 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
13659 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
13660 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
13676 extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206);
\r
13677 #define CAN3TFLG _CAN3TFLG.Byte
\r
13678 #define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0
\r
13679 #define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1
\r
13680 #define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2
\r
13681 #define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE
\r
13684 /*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/
\r
13688 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
13689 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
13690 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
13698 byte grpTXEIE :3;
\r
13706 extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207);
\r
13707 #define CAN3TIER _CAN3TIER.Byte
\r
13708 #define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0
\r
13709 #define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1
\r
13710 #define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2
\r
13711 #define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE
\r
13714 /*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/
\r
13718 byte ABTRQ0 :1; /* Abort Request 0 */
\r
13719 byte ABTRQ1 :1; /* Abort Request 1 */
\r
13720 byte ABTRQ2 :1; /* Abort Request 2 */
\r
13728 byte grpABTRQ :3;
\r
13736 extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208);
\r
13737 #define CAN3TARQ _CAN3TARQ.Byte
\r
13738 #define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0
\r
13739 #define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1
\r
13740 #define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2
\r
13741 #define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ
\r
13744 /*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/
\r
13748 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
13749 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
13750 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
13758 byte grpABTAK :3;
\r
13766 extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209);
\r
13767 #define CAN3TAAK _CAN3TAAK.Byte
\r
13768 #define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0
\r
13769 #define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1
\r
13770 #define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2
\r
13771 #define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK
\r
13774 /*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/
\r
13778 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
13779 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
13780 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
13796 extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A);
\r
13797 #define CAN3TBSEL _CAN3TBSEL.Byte
\r
13798 #define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0
\r
13799 #define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1
\r
13800 #define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2
\r
13801 #define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX
\r
13804 /*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/
\r
13808 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
13809 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
13810 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
13812 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
13813 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
13818 byte grpIDHIT :3;
\r
13825 extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B);
\r
13826 #define CAN3IDAC _CAN3IDAC.Byte
\r
13827 #define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0
\r
13828 #define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1
\r
13829 #define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2
\r
13830 #define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0
\r
13831 #define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1
\r
13832 #define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT
\r
13833 #define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM
\r
13836 /*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/
\r
13840 byte RXERR0 :1; /* Bit 0 */
\r
13841 byte RXERR1 :1; /* Bit 1 */
\r
13842 byte RXERR2 :1; /* Bit 2 */
\r
13843 byte RXERR3 :1; /* Bit 3 */
\r
13844 byte RXERR4 :1; /* Bit 4 */
\r
13845 byte RXERR5 :1; /* Bit 5 */
\r
13846 byte RXERR6 :1; /* Bit 6 */
\r
13847 byte RXERR7 :1; /* Bit 7 */
\r
13850 byte grpRXERR :8;
\r
13853 extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E);
\r
13854 #define CAN3RXERR _CAN3RXERR.Byte
\r
13855 #define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0
\r
13856 #define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1
\r
13857 #define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2
\r
13858 #define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3
\r
13859 #define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4
\r
13860 #define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5
\r
13861 #define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6
\r
13862 #define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7
\r
13863 #define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR
\r
13866 /*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/
\r
13870 byte TXERR0 :1; /* Bit 0 */
\r
13871 byte TXERR1 :1; /* Bit 1 */
\r
13872 byte TXERR2 :1; /* Bit 2 */
\r
13873 byte TXERR3 :1; /* Bit 3 */
\r
13874 byte TXERR4 :1; /* Bit 4 */
\r
13875 byte TXERR5 :1; /* Bit 5 */
\r
13876 byte TXERR6 :1; /* Bit 6 */
\r
13877 byte TXERR7 :1; /* Bit 7 */
\r
13880 byte grpTXERR :8;
\r
13883 extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F);
\r
13884 #define CAN3TXERR _CAN3TXERR.Byte
\r
13885 #define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0
\r
13886 #define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1
\r
13887 #define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2
\r
13888 #define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3
\r
13889 #define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4
\r
13890 #define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5
\r
13891 #define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6
\r
13892 #define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7
\r
13893 #define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR
\r
13896 /*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/
\r
13900 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
13901 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
13902 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
13903 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
13904 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
13905 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
13906 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
13907 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
13913 extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210);
\r
13914 #define CAN3IDAR0 _CAN3IDAR0.Byte
\r
13915 #define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0
\r
13916 #define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1
\r
13917 #define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2
\r
13918 #define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3
\r
13919 #define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4
\r
13920 #define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5
\r
13921 #define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6
\r
13922 #define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7
\r
13923 #define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC
\r
13926 /*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/
\r
13930 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
13931 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
13932 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
13933 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
13934 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
13935 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
13936 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
13937 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
13943 extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211);
\r
13944 #define CAN3IDAR1 _CAN3IDAR1.Byte
\r
13945 #define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0
\r
13946 #define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1
\r
13947 #define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2
\r
13948 #define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3
\r
13949 #define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4
\r
13950 #define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5
\r
13951 #define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6
\r
13952 #define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7
\r
13953 #define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC
\r
13956 /*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/
\r
13960 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
13961 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
13962 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
13963 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
13964 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
13965 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
13966 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
13967 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
13973 extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212);
\r
13974 #define CAN3IDAR2 _CAN3IDAR2.Byte
\r
13975 #define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0
\r
13976 #define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1
\r
13977 #define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2
\r
13978 #define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3
\r
13979 #define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4
\r
13980 #define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5
\r
13981 #define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6
\r
13982 #define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7
\r
13983 #define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC
\r
13986 /*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/
\r
13990 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
13991 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
13992 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
13993 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
13994 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
13995 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
13996 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
13997 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
14003 extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213);
\r
14004 #define CAN3IDAR3 _CAN3IDAR3.Byte
\r
14005 #define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0
\r
14006 #define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1
\r
14007 #define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2
\r
14008 #define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3
\r
14009 #define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4
\r
14010 #define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5
\r
14011 #define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6
\r
14012 #define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7
\r
14013 #define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC
\r
14016 /*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/
\r
14020 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14021 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14022 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14023 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14024 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14025 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14026 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14027 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14033 extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214);
\r
14034 #define CAN3IDMR0 _CAN3IDMR0.Byte
\r
14035 #define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0
\r
14036 #define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1
\r
14037 #define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2
\r
14038 #define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3
\r
14039 #define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4
\r
14040 #define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5
\r
14041 #define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6
\r
14042 #define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7
\r
14043 #define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM
\r
14046 /*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/
\r
14050 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14051 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14052 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14053 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14054 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14055 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14056 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14057 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14063 extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215);
\r
14064 #define CAN3IDMR1 _CAN3IDMR1.Byte
\r
14065 #define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0
\r
14066 #define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1
\r
14067 #define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2
\r
14068 #define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3
\r
14069 #define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4
\r
14070 #define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5
\r
14071 #define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6
\r
14072 #define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7
\r
14073 #define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM
\r
14076 /*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/
\r
14080 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14081 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14082 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14083 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14084 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14085 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14086 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14087 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14093 extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216);
\r
14094 #define CAN3IDMR2 _CAN3IDMR2.Byte
\r
14095 #define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0
\r
14096 #define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1
\r
14097 #define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2
\r
14098 #define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3
\r
14099 #define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4
\r
14100 #define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5
\r
14101 #define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6
\r
14102 #define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7
\r
14103 #define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM
\r
14106 /*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/
\r
14110 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14111 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14112 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14113 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14114 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14115 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14116 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14117 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14123 extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217);
\r
14124 #define CAN3IDMR3 _CAN3IDMR3.Byte
\r
14125 #define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0
\r
14126 #define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1
\r
14127 #define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2
\r
14128 #define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3
\r
14129 #define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4
\r
14130 #define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5
\r
14131 #define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6
\r
14132 #define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7
\r
14133 #define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM
\r
14136 /*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/
\r
14140 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
14141 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
14142 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
14143 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
14144 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
14145 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
14146 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
14147 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
14153 extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218);
\r
14154 #define CAN3IDAR4 _CAN3IDAR4.Byte
\r
14155 #define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0
\r
14156 #define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1
\r
14157 #define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2
\r
14158 #define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3
\r
14159 #define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4
\r
14160 #define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5
\r
14161 #define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6
\r
14162 #define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7
\r
14163 #define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC
\r
14166 /*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/
\r
14170 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
14171 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
14172 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
14173 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
14174 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
14175 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
14176 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
14177 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
14183 extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219);
\r
14184 #define CAN3IDAR5 _CAN3IDAR5.Byte
\r
14185 #define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0
\r
14186 #define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1
\r
14187 #define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2
\r
14188 #define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3
\r
14189 #define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4
\r
14190 #define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5
\r
14191 #define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6
\r
14192 #define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7
\r
14193 #define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC
\r
14196 /*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/
\r
14200 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
14201 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
14202 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
14203 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
14204 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
14205 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
14206 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
14207 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
14213 extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A);
\r
14214 #define CAN3IDAR6 _CAN3IDAR6.Byte
\r
14215 #define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0
\r
14216 #define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1
\r
14217 #define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2
\r
14218 #define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3
\r
14219 #define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4
\r
14220 #define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5
\r
14221 #define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6
\r
14222 #define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7
\r
14223 #define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC
\r
14226 /*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/
\r
14230 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
14231 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
14232 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
14233 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
14234 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
14235 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
14236 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
14237 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
14243 extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B);
\r
14244 #define CAN3IDAR7 _CAN3IDAR7.Byte
\r
14245 #define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0
\r
14246 #define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1
\r
14247 #define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2
\r
14248 #define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3
\r
14249 #define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4
\r
14250 #define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5
\r
14251 #define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6
\r
14252 #define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7
\r
14253 #define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC
\r
14256 /*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/
\r
14260 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14261 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14262 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14263 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14264 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14265 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14266 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14267 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14273 extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C);
\r
14274 #define CAN3IDMR4 _CAN3IDMR4.Byte
\r
14275 #define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0
\r
14276 #define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1
\r
14277 #define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2
\r
14278 #define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3
\r
14279 #define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4
\r
14280 #define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5
\r
14281 #define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6
\r
14282 #define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7
\r
14283 #define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM
\r
14286 /*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/
\r
14290 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14291 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14292 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14293 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14294 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14295 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14296 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14297 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14303 extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D);
\r
14304 #define CAN3IDMR5 _CAN3IDMR5.Byte
\r
14305 #define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0
\r
14306 #define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1
\r
14307 #define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2
\r
14308 #define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3
\r
14309 #define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4
\r
14310 #define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5
\r
14311 #define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6
\r
14312 #define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7
\r
14313 #define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM
\r
14316 /*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/
\r
14320 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14321 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14322 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14323 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14324 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14325 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14326 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14327 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14333 extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E);
\r
14334 #define CAN3IDMR6 _CAN3IDMR6.Byte
\r
14335 #define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0
\r
14336 #define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1
\r
14337 #define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2
\r
14338 #define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3
\r
14339 #define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4
\r
14340 #define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5
\r
14341 #define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6
\r
14342 #define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7
\r
14343 #define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM
\r
14346 /*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/
\r
14350 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
14351 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
14352 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
14353 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
14354 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
14355 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
14356 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
14357 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
14363 extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F);
\r
14364 #define CAN3IDMR7 _CAN3IDMR7.Byte
\r
14365 #define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0
\r
14366 #define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1
\r
14367 #define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2
\r
14368 #define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3
\r
14369 #define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4
\r
14370 #define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5
\r
14371 #define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6
\r
14372 #define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7
\r
14373 #define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM
\r
14376 /*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/
\r
14380 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
14381 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
14382 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
14383 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
14384 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
14385 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
14386 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
14387 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
14390 byte grpID_21 :8;
\r
14393 extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220);
\r
14394 #define CAN3RXIDR0 _CAN3RXIDR0.Byte
\r
14395 #define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21
\r
14396 #define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22
\r
14397 #define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23
\r
14398 #define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24
\r
14399 #define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25
\r
14400 #define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26
\r
14401 #define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27
\r
14402 #define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28
\r
14403 #define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21
\r
14404 #define CAN3RXIDR0_ID CAN3RXIDR0_ID_21
\r
14407 /*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/
\r
14411 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
14412 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
14413 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
14414 byte IDE :1; /* ID Extended */
\r
14415 byte SRR :1; /* Substitute Remote Request */
\r
14416 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
14417 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
14418 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
14421 byte grpID_15 :3;
\r
14424 byte grpID_18 :3;
\r
14427 extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221);
\r
14428 #define CAN3RXIDR1 _CAN3RXIDR1.Byte
\r
14429 #define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15
\r
14430 #define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16
\r
14431 #define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17
\r
14432 #define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE
\r
14433 #define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR
\r
14434 #define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18
\r
14435 #define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19
\r
14436 #define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20
\r
14437 #define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15
\r
14438 #define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18
\r
14439 #define CAN3RXIDR1_ID CAN3RXIDR1_ID_15
\r
14442 /*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/
\r
14446 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
14447 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
14448 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
14449 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
14450 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
14451 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
14452 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
14453 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
14459 extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222);
\r
14460 #define CAN3RXIDR2 _CAN3RXIDR2.Byte
\r
14461 #define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7
\r
14462 #define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8
\r
14463 #define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9
\r
14464 #define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10
\r
14465 #define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11
\r
14466 #define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12
\r
14467 #define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13
\r
14468 #define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14
\r
14469 #define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7
\r
14470 #define CAN3RXIDR2_ID CAN3RXIDR2_ID_7
\r
14473 /*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/
\r
14477 byte RTR :1; /* Remote Transmission Request */
\r
14478 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
14479 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
14480 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
14481 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
14482 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
14483 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
14484 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
14491 extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223);
\r
14492 #define CAN3RXIDR3 _CAN3RXIDR3.Byte
\r
14493 #define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR
\r
14494 #define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0
\r
14495 #define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1
\r
14496 #define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2
\r
14497 #define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3
\r
14498 #define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4
\r
14499 #define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5
\r
14500 #define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6
\r
14501 #define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID
\r
14504 /*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/
\r
14508 byte DB0 :1; /* Data Bit 0 */
\r
14509 byte DB1 :1; /* Data Bit 1 */
\r
14510 byte DB2 :1; /* Data Bit 2 */
\r
14511 byte DB3 :1; /* Data Bit 3 */
\r
14512 byte DB4 :1; /* Data Bit 4 */
\r
14513 byte DB5 :1; /* Data Bit 5 */
\r
14514 byte DB6 :1; /* Data Bit 6 */
\r
14515 byte DB7 :1; /* Data Bit 7 */
\r
14521 extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224);
\r
14522 #define CAN3RXDSR0 _CAN3RXDSR0.Byte
\r
14523 #define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0
\r
14524 #define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1
\r
14525 #define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2
\r
14526 #define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3
\r
14527 #define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4
\r
14528 #define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5
\r
14529 #define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6
\r
14530 #define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7
\r
14531 #define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB
\r
14534 /*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/
\r
14538 byte DB0 :1; /* Data Bit 0 */
\r
14539 byte DB1 :1; /* Data Bit 1 */
\r
14540 byte DB2 :1; /* Data Bit 2 */
\r
14541 byte DB3 :1; /* Data Bit 3 */
\r
14542 byte DB4 :1; /* Data Bit 4 */
\r
14543 byte DB5 :1; /* Data Bit 5 */
\r
14544 byte DB6 :1; /* Data Bit 6 */
\r
14545 byte DB7 :1; /* Data Bit 7 */
\r
14551 extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225);
\r
14552 #define CAN3RXDSR1 _CAN3RXDSR1.Byte
\r
14553 #define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0
\r
14554 #define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1
\r
14555 #define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2
\r
14556 #define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3
\r
14557 #define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4
\r
14558 #define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5
\r
14559 #define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6
\r
14560 #define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7
\r
14561 #define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB
\r
14564 /*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/
\r
14568 byte DB0 :1; /* Data Bit 0 */
\r
14569 byte DB1 :1; /* Data Bit 1 */
\r
14570 byte DB2 :1; /* Data Bit 2 */
\r
14571 byte DB3 :1; /* Data Bit 3 */
\r
14572 byte DB4 :1; /* Data Bit 4 */
\r
14573 byte DB5 :1; /* Data Bit 5 */
\r
14574 byte DB6 :1; /* Data Bit 6 */
\r
14575 byte DB7 :1; /* Data Bit 7 */
\r
14581 extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226);
\r
14582 #define CAN3RXDSR2 _CAN3RXDSR2.Byte
\r
14583 #define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0
\r
14584 #define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1
\r
14585 #define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2
\r
14586 #define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3
\r
14587 #define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4
\r
14588 #define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5
\r
14589 #define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6
\r
14590 #define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7
\r
14591 #define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB
\r
14594 /*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/
\r
14598 byte DB0 :1; /* Data Bit 0 */
\r
14599 byte DB1 :1; /* Data Bit 1 */
\r
14600 byte DB2 :1; /* Data Bit 2 */
\r
14601 byte DB3 :1; /* Data Bit 3 */
\r
14602 byte DB4 :1; /* Data Bit 4 */
\r
14603 byte DB5 :1; /* Data Bit 5 */
\r
14604 byte DB6 :1; /* Data Bit 6 */
\r
14605 byte DB7 :1; /* Data Bit 7 */
\r
14611 extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227);
\r
14612 #define CAN3RXDSR3 _CAN3RXDSR3.Byte
\r
14613 #define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0
\r
14614 #define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1
\r
14615 #define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2
\r
14616 #define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3
\r
14617 #define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4
\r
14618 #define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5
\r
14619 #define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6
\r
14620 #define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7
\r
14621 #define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB
\r
14624 /*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/
\r
14628 byte DB0 :1; /* Data Bit 0 */
\r
14629 byte DB1 :1; /* Data Bit 1 */
\r
14630 byte DB2 :1; /* Data Bit 2 */
\r
14631 byte DB3 :1; /* Data Bit 3 */
\r
14632 byte DB4 :1; /* Data Bit 4 */
\r
14633 byte DB5 :1; /* Data Bit 5 */
\r
14634 byte DB6 :1; /* Data Bit 6 */
\r
14635 byte DB7 :1; /* Data Bit 7 */
\r
14641 extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228);
\r
14642 #define CAN3RXDSR4 _CAN3RXDSR4.Byte
\r
14643 #define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0
\r
14644 #define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1
\r
14645 #define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2
\r
14646 #define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3
\r
14647 #define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4
\r
14648 #define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5
\r
14649 #define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6
\r
14650 #define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7
\r
14651 #define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB
\r
14654 /*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/
\r
14658 byte DB0 :1; /* Data Bit 0 */
\r
14659 byte DB1 :1; /* Data Bit 1 */
\r
14660 byte DB2 :1; /* Data Bit 2 */
\r
14661 byte DB3 :1; /* Data Bit 3 */
\r
14662 byte DB4 :1; /* Data Bit 4 */
\r
14663 byte DB5 :1; /* Data Bit 5 */
\r
14664 byte DB6 :1; /* Data Bit 6 */
\r
14665 byte DB7 :1; /* Data Bit 7 */
\r
14671 extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229);
\r
14672 #define CAN3RXDSR5 _CAN3RXDSR5.Byte
\r
14673 #define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0
\r
14674 #define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1
\r
14675 #define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2
\r
14676 #define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3
\r
14677 #define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4
\r
14678 #define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5
\r
14679 #define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6
\r
14680 #define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7
\r
14681 #define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB
\r
14684 /*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/
\r
14688 byte DB0 :1; /* Data Bit 0 */
\r
14689 byte DB1 :1; /* Data Bit 1 */
\r
14690 byte DB2 :1; /* Data Bit 2 */
\r
14691 byte DB3 :1; /* Data Bit 3 */
\r
14692 byte DB4 :1; /* Data Bit 4 */
\r
14693 byte DB5 :1; /* Data Bit 5 */
\r
14694 byte DB6 :1; /* Data Bit 6 */
\r
14695 byte DB7 :1; /* Data Bit 7 */
\r
14701 extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A);
\r
14702 #define CAN3RXDSR6 _CAN3RXDSR6.Byte
\r
14703 #define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0
\r
14704 #define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1
\r
14705 #define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2
\r
14706 #define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3
\r
14707 #define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4
\r
14708 #define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5
\r
14709 #define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6
\r
14710 #define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7
\r
14711 #define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB
\r
14714 /*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/
\r
14718 byte DB0 :1; /* Data Bit 0 */
\r
14719 byte DB1 :1; /* Data Bit 1 */
\r
14720 byte DB2 :1; /* Data Bit 2 */
\r
14721 byte DB3 :1; /* Data Bit 3 */
\r
14722 byte DB4 :1; /* Data Bit 4 */
\r
14723 byte DB5 :1; /* Data Bit 5 */
\r
14724 byte DB6 :1; /* Data Bit 6 */
\r
14725 byte DB7 :1; /* Data Bit 7 */
\r
14731 extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B);
\r
14732 #define CAN3RXDSR7 _CAN3RXDSR7.Byte
\r
14733 #define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0
\r
14734 #define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1
\r
14735 #define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2
\r
14736 #define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3
\r
14737 #define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4
\r
14738 #define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5
\r
14739 #define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6
\r
14740 #define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7
\r
14741 #define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB
\r
14744 /*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/
\r
14748 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
14749 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
14750 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
14751 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
14765 extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C);
\r
14766 #define CAN3RXDLR _CAN3RXDLR.Byte
\r
14767 #define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0
\r
14768 #define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1
\r
14769 #define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2
\r
14770 #define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3
\r
14771 #define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC
\r
14774 /*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/
\r
14778 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
14779 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
14780 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
14781 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
14782 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
14783 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
14784 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
14785 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
14788 byte grpID_21 :8;
\r
14791 extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230);
\r
14792 #define CAN3TXIDR0 _CAN3TXIDR0.Byte
\r
14793 #define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21
\r
14794 #define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22
\r
14795 #define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23
\r
14796 #define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24
\r
14797 #define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25
\r
14798 #define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26
\r
14799 #define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27
\r
14800 #define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28
\r
14801 #define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21
\r
14802 #define CAN3TXIDR0_ID CAN3TXIDR0_ID_21
\r
14805 /*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/
\r
14809 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
14810 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
14811 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
14812 byte IDE :1; /* ID Extended */
\r
14813 byte SRR :1; /* Substitute Remote Request */
\r
14814 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
14815 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
14816 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
14819 byte grpID_15 :3;
\r
14822 byte grpID_18 :3;
\r
14825 extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231);
\r
14826 #define CAN3TXIDR1 _CAN3TXIDR1.Byte
\r
14827 #define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15
\r
14828 #define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16
\r
14829 #define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17
\r
14830 #define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE
\r
14831 #define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR
\r
14832 #define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18
\r
14833 #define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19
\r
14834 #define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20
\r
14835 #define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15
\r
14836 #define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18
\r
14837 #define CAN3TXIDR1_ID CAN3TXIDR1_ID_15
\r
14840 /*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/
\r
14844 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
14845 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
14846 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
14847 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
14848 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
14849 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
14850 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
14851 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
14857 extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232);
\r
14858 #define CAN3TXIDR2 _CAN3TXIDR2.Byte
\r
14859 #define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7
\r
14860 #define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8
\r
14861 #define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9
\r
14862 #define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10
\r
14863 #define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11
\r
14864 #define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12
\r
14865 #define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13
\r
14866 #define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14
\r
14867 #define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7
\r
14868 #define CAN3TXIDR2_ID CAN3TXIDR2_ID_7
\r
14871 /*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/
\r
14875 byte RTR :1; /* Remote Transmission Request */
\r
14876 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
14877 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
14878 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
14879 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
14880 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
14881 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
14882 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
14889 extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233);
\r
14890 #define CAN3TXIDR3 _CAN3TXIDR3.Byte
\r
14891 #define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR
\r
14892 #define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0
\r
14893 #define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1
\r
14894 #define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2
\r
14895 #define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3
\r
14896 #define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4
\r
14897 #define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5
\r
14898 #define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6
\r
14899 #define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID
\r
14902 /*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/
\r
14906 byte DB0 :1; /* Data Bit 0 */
\r
14907 byte DB1 :1; /* Data Bit 1 */
\r
14908 byte DB2 :1; /* Data Bit 2 */
\r
14909 byte DB3 :1; /* Data Bit 3 */
\r
14910 byte DB4 :1; /* Data Bit 4 */
\r
14911 byte DB5 :1; /* Data Bit 5 */
\r
14912 byte DB6 :1; /* Data Bit 6 */
\r
14913 byte DB7 :1; /* Data Bit 7 */
\r
14919 extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234);
\r
14920 #define CAN3TXDSR0 _CAN3TXDSR0.Byte
\r
14921 #define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0
\r
14922 #define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1
\r
14923 #define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2
\r
14924 #define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3
\r
14925 #define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4
\r
14926 #define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5
\r
14927 #define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6
\r
14928 #define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7
\r
14929 #define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB
\r
14932 /*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/
\r
14936 byte DB0 :1; /* Data Bit 0 */
\r
14937 byte DB1 :1; /* Data Bit 1 */
\r
14938 byte DB2 :1; /* Data Bit 2 */
\r
14939 byte DB3 :1; /* Data Bit 3 */
\r
14940 byte DB4 :1; /* Data Bit 4 */
\r
14941 byte DB5 :1; /* Data Bit 5 */
\r
14942 byte DB6 :1; /* Data Bit 6 */
\r
14943 byte DB7 :1; /* Data Bit 7 */
\r
14949 extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235);
\r
14950 #define CAN3TXDSR1 _CAN3TXDSR1.Byte
\r
14951 #define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0
\r
14952 #define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1
\r
14953 #define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2
\r
14954 #define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3
\r
14955 #define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4
\r
14956 #define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5
\r
14957 #define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6
\r
14958 #define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7
\r
14959 #define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB
\r
14962 /*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/
\r
14966 byte DB0 :1; /* Data Bit 0 */
\r
14967 byte DB1 :1; /* Data Bit 1 */
\r
14968 byte DB2 :1; /* Data Bit 2 */
\r
14969 byte DB3 :1; /* Data Bit 3 */
\r
14970 byte DB4 :1; /* Data Bit 4 */
\r
14971 byte DB5 :1; /* Data Bit 5 */
\r
14972 byte DB6 :1; /* Data Bit 6 */
\r
14973 byte DB7 :1; /* Data Bit 7 */
\r
14979 extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236);
\r
14980 #define CAN3TXDSR2 _CAN3TXDSR2.Byte
\r
14981 #define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0
\r
14982 #define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1
\r
14983 #define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2
\r
14984 #define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3
\r
14985 #define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4
\r
14986 #define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5
\r
14987 #define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6
\r
14988 #define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7
\r
14989 #define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB
\r
14992 /*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/
\r
14996 byte DB0 :1; /* Data Bit 0 */
\r
14997 byte DB1 :1; /* Data Bit 1 */
\r
14998 byte DB2 :1; /* Data Bit 2 */
\r
14999 byte DB3 :1; /* Data Bit 3 */
\r
15000 byte DB4 :1; /* Data Bit 4 */
\r
15001 byte DB5 :1; /* Data Bit 5 */
\r
15002 byte DB6 :1; /* Data Bit 6 */
\r
15003 byte DB7 :1; /* Data Bit 7 */
\r
15009 extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237);
\r
15010 #define CAN3TXDSR3 _CAN3TXDSR3.Byte
\r
15011 #define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0
\r
15012 #define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1
\r
15013 #define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2
\r
15014 #define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3
\r
15015 #define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4
\r
15016 #define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5
\r
15017 #define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6
\r
15018 #define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7
\r
15019 #define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB
\r
15022 /*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/
\r
15026 byte DB0 :1; /* Data Bit 0 */
\r
15027 byte DB1 :1; /* Data Bit 1 */
\r
15028 byte DB2 :1; /* Data Bit 2 */
\r
15029 byte DB3 :1; /* Data Bit 3 */
\r
15030 byte DB4 :1; /* Data Bit 4 */
\r
15031 byte DB5 :1; /* Data Bit 5 */
\r
15032 byte DB6 :1; /* Data Bit 6 */
\r
15033 byte DB7 :1; /* Data Bit 7 */
\r
15039 extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238);
\r
15040 #define CAN3TXDSR4 _CAN3TXDSR4.Byte
\r
15041 #define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0
\r
15042 #define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1
\r
15043 #define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2
\r
15044 #define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3
\r
15045 #define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4
\r
15046 #define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5
\r
15047 #define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6
\r
15048 #define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7
\r
15049 #define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB
\r
15052 /*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/
\r
15056 byte DB0 :1; /* Data Bit 0 */
\r
15057 byte DB1 :1; /* Data Bit 1 */
\r
15058 byte DB2 :1; /* Data Bit 2 */
\r
15059 byte DB3 :1; /* Data Bit 3 */
\r
15060 byte DB4 :1; /* Data Bit 4 */
\r
15061 byte DB5 :1; /* Data Bit 5 */
\r
15062 byte DB6 :1; /* Data Bit 6 */
\r
15063 byte DB7 :1; /* Data Bit 7 */
\r
15069 extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239);
\r
15070 #define CAN3TXDSR5 _CAN3TXDSR5.Byte
\r
15071 #define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0
\r
15072 #define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1
\r
15073 #define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2
\r
15074 #define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3
\r
15075 #define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4
\r
15076 #define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5
\r
15077 #define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6
\r
15078 #define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7
\r
15079 #define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB
\r
15082 /*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/
\r
15086 byte DB0 :1; /* Data Bit 0 */
\r
15087 byte DB1 :1; /* Data Bit 1 */
\r
15088 byte DB2 :1; /* Data Bit 2 */
\r
15089 byte DB3 :1; /* Data Bit 3 */
\r
15090 byte DB4 :1; /* Data Bit 4 */
\r
15091 byte DB5 :1; /* Data Bit 5 */
\r
15092 byte DB6 :1; /* Data Bit 6 */
\r
15093 byte DB7 :1; /* Data Bit 7 */
\r
15099 extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A);
\r
15100 #define CAN3TXDSR6 _CAN3TXDSR6.Byte
\r
15101 #define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0
\r
15102 #define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1
\r
15103 #define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2
\r
15104 #define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3
\r
15105 #define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4
\r
15106 #define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5
\r
15107 #define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6
\r
15108 #define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7
\r
15109 #define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB
\r
15112 /*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/
\r
15116 byte DB0 :1; /* Data Bit 0 */
\r
15117 byte DB1 :1; /* Data Bit 1 */
\r
15118 byte DB2 :1; /* Data Bit 2 */
\r
15119 byte DB3 :1; /* Data Bit 3 */
\r
15120 byte DB4 :1; /* Data Bit 4 */
\r
15121 byte DB5 :1; /* Data Bit 5 */
\r
15122 byte DB6 :1; /* Data Bit 6 */
\r
15123 byte DB7 :1; /* Data Bit 7 */
\r
15129 extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B);
\r
15130 #define CAN3TXDSR7 _CAN3TXDSR7.Byte
\r
15131 #define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0
\r
15132 #define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1
\r
15133 #define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2
\r
15134 #define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3
\r
15135 #define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4
\r
15136 #define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5
\r
15137 #define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6
\r
15138 #define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7
\r
15139 #define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB
\r
15142 /*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/
\r
15146 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
15147 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
15148 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
15149 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
15163 extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C);
\r
15164 #define CAN3TXDLR _CAN3TXDLR.Byte
\r
15165 #define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0
\r
15166 #define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1
\r
15167 #define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2
\r
15168 #define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3
\r
15169 #define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC
\r
15172 /*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/
\r
15176 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
15177 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
15178 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
15179 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
15180 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
15181 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
15182 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
15183 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
15189 extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F);
\r
15190 #define CAN3TXTBPR _CAN3TXTBPR.Byte
\r
15191 #define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0
\r
15192 #define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1
\r
15193 #define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2
\r
15194 #define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3
\r
15195 #define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4
\r
15196 #define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5
\r
15197 #define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6
\r
15198 #define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7
\r
15199 #define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO
\r
15202 /*** PTT - Port T I/O Register; 0x00000240 ***/
\r
15206 byte PTT0 :1; /* Port T Bit 0 */
\r
15207 byte PTT1 :1; /* Port T Bit 1 */
\r
15208 byte PTT2 :1; /* Port T Bit 2 */
\r
15209 byte PTT3 :1; /* Port T Bit 3 */
\r
15210 byte PTT4 :1; /* Port T Bit 4 */
\r
15211 byte PTT5 :1; /* Port T Bit 5 */
\r
15212 byte PTT6 :1; /* Port T Bit 6 */
\r
15213 byte PTT7 :1; /* Port T Bit 7 */
\r
15219 extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
\r
15220 #define PTT _PTT.Byte
\r
15221 #define PTT_PTT0 _PTT.Bits.PTT0
\r
15222 #define PTT_PTT1 _PTT.Bits.PTT1
\r
15223 #define PTT_PTT2 _PTT.Bits.PTT2
\r
15224 #define PTT_PTT3 _PTT.Bits.PTT3
\r
15225 #define PTT_PTT4 _PTT.Bits.PTT4
\r
15226 #define PTT_PTT5 _PTT.Bits.PTT5
\r
15227 #define PTT_PTT6 _PTT.Bits.PTT6
\r
15228 #define PTT_PTT7 _PTT.Bits.PTT7
\r
15229 #define PTT_PTT _PTT.MergedBits.grpPTT
\r
15232 /*** PTIT - Port T Input; 0x00000241 ***/
\r
15236 byte PTIT0 :1; /* Port T Bit 0 */
\r
15237 byte PTIT1 :1; /* Port T Bit 1 */
\r
15238 byte PTIT2 :1; /* Port T Bit 2 */
\r
15239 byte PTIT3 :1; /* Port T Bit 3 */
\r
15240 byte PTIT4 :1; /* Port T Bit 4 */
\r
15241 byte PTIT5 :1; /* Port T Bit 5 */
\r
15242 byte PTIT6 :1; /* Port T Bit 6 */
\r
15243 byte PTIT7 :1; /* Port T Bit 7 */
\r
15249 extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
\r
15250 #define PTIT _PTIT.Byte
\r
15251 #define PTIT_PTIT0 _PTIT.Bits.PTIT0
\r
15252 #define PTIT_PTIT1 _PTIT.Bits.PTIT1
\r
15253 #define PTIT_PTIT2 _PTIT.Bits.PTIT2
\r
15254 #define PTIT_PTIT3 _PTIT.Bits.PTIT3
\r
15255 #define PTIT_PTIT4 _PTIT.Bits.PTIT4
\r
15256 #define PTIT_PTIT5 _PTIT.Bits.PTIT5
\r
15257 #define PTIT_PTIT6 _PTIT.Bits.PTIT6
\r
15258 #define PTIT_PTIT7 _PTIT.Bits.PTIT7
\r
15259 #define PTIT_PTIT _PTIT.MergedBits.grpPTIT
\r
15262 /*** DDRT - Port T Data Direction Register; 0x00000242 ***/
\r
15266 byte DDRT0 :1; /* Data Direction Port T Bit 0 */
\r
15267 byte DDRT1 :1; /* Data Direction Port T Bit 1 */
\r
15268 byte DDRT2 :1; /* Data Direction Port T Bit 2 */
\r
15269 byte DDRT3 :1; /* Data Direction Port T Bit 3 */
\r
15270 byte DDRT4 :1; /* Data Direction Port T Bit 4 */
\r
15271 byte DDRT5 :1; /* Data Direction Port T Bit 5 */
\r
15272 byte DDRT6 :1; /* Data Direction Port T Bit 6 */
\r
15273 byte DDRT7 :1; /* Data Direction Port T Bit 7 */
\r
15279 extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
\r
15280 #define DDRT _DDRT.Byte
\r
15281 #define DDRT_DDRT0 _DDRT.Bits.DDRT0
\r
15282 #define DDRT_DDRT1 _DDRT.Bits.DDRT1
\r
15283 #define DDRT_DDRT2 _DDRT.Bits.DDRT2
\r
15284 #define DDRT_DDRT3 _DDRT.Bits.DDRT3
\r
15285 #define DDRT_DDRT4 _DDRT.Bits.DDRT4
\r
15286 #define DDRT_DDRT5 _DDRT.Bits.DDRT5
\r
15287 #define DDRT_DDRT6 _DDRT.Bits.DDRT6
\r
15288 #define DDRT_DDRT7 _DDRT.Bits.DDRT7
\r
15289 #define DDRT_DDRT _DDRT.MergedBits.grpDDRT
\r
15292 /*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
\r
15296 byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */
\r
15297 byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */
\r
15298 byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */
\r
15299 byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */
\r
15300 byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */
\r
15301 byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */
\r
15302 byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */
\r
15303 byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */
\r
15309 extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
\r
15310 #define RDRT _RDRT.Byte
\r
15311 #define RDRT_RDRT0 _RDRT.Bits.RDRT0
\r
15312 #define RDRT_RDRT1 _RDRT.Bits.RDRT1
\r
15313 #define RDRT_RDRT2 _RDRT.Bits.RDRT2
\r
15314 #define RDRT_RDRT3 _RDRT.Bits.RDRT3
\r
15315 #define RDRT_RDRT4 _RDRT.Bits.RDRT4
\r
15316 #define RDRT_RDRT5 _RDRT.Bits.RDRT5
\r
15317 #define RDRT_RDRT6 _RDRT.Bits.RDRT6
\r
15318 #define RDRT_RDRT7 _RDRT.Bits.RDRT7
\r
15319 #define RDRT_RDRT _RDRT.MergedBits.grpRDRT
\r
15322 /*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
\r
15326 byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */
\r
15327 byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */
\r
15328 byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */
\r
15329 byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */
\r
15330 byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */
\r
15331 byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */
\r
15332 byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */
\r
15333 byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */
\r
15339 extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);
\r
15340 #define PERT _PERT.Byte
\r
15341 #define PERT_PERT0 _PERT.Bits.PERT0
\r
15342 #define PERT_PERT1 _PERT.Bits.PERT1
\r
15343 #define PERT_PERT2 _PERT.Bits.PERT2
\r
15344 #define PERT_PERT3 _PERT.Bits.PERT3
\r
15345 #define PERT_PERT4 _PERT.Bits.PERT4
\r
15346 #define PERT_PERT5 _PERT.Bits.PERT5
\r
15347 #define PERT_PERT6 _PERT.Bits.PERT6
\r
15348 #define PERT_PERT7 _PERT.Bits.PERT7
\r
15349 #define PERT_PERT _PERT.MergedBits.grpPERT
\r
15352 /*** PPST - Port T Polarity Select Register; 0x00000245 ***/
\r
15356 byte PPST0 :1; /* Pull Select Port T Bit 0 */
\r
15357 byte PPST1 :1; /* Pull Select Port T Bit 1 */
\r
15358 byte PPST2 :1; /* Pull Select Port T Bit 2 */
\r
15359 byte PPST3 :1; /* Pull Select Port T Bit 3 */
\r
15360 byte PPST4 :1; /* Pull Select Port T Bit 4 */
\r
15361 byte PPST5 :1; /* Pull Select Port T Bit 5 */
\r
15362 byte PPST6 :1; /* Pull Select Port T Bit 6 */
\r
15363 byte PPST7 :1; /* Pull Select Port T Bit 7 */
\r
15369 extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);
\r
15370 #define PPST _PPST.Byte
\r
15371 #define PPST_PPST0 _PPST.Bits.PPST0
\r
15372 #define PPST_PPST1 _PPST.Bits.PPST1
\r
15373 #define PPST_PPST2 _PPST.Bits.PPST2
\r
15374 #define PPST_PPST3 _PPST.Bits.PPST3
\r
15375 #define PPST_PPST4 _PPST.Bits.PPST4
\r
15376 #define PPST_PPST5 _PPST.Bits.PPST5
\r
15377 #define PPST_PPST6 _PPST.Bits.PPST6
\r
15378 #define PPST_PPST7 _PPST.Bits.PPST7
\r
15379 #define PPST_PPST _PPST.MergedBits.grpPPST
\r
15382 /*** PTS - Port S I/O Register; 0x00000248 ***/
\r
15386 byte PTS0 :1; /* Port S Bit 0 */
\r
15387 byte PTS1 :1; /* Port S Bit 1 */
\r
15388 byte PTS2 :1; /* Port S Bit 2 */
\r
15389 byte PTS3 :1; /* Port S Bit 3 */
\r
15390 byte PTS4 :1; /* Port S Bit 4 */
\r
15391 byte PTS5 :1; /* Port S Bit 5 */
\r
15392 byte PTS6 :1; /* Port S Bit 6 */
\r
15393 byte PTS7 :1; /* Port S Bit 7 */
\r
15399 extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);
\r
15400 #define PTS _PTS.Byte
\r
15401 #define PTS_PTS0 _PTS.Bits.PTS0
\r
15402 #define PTS_PTS1 _PTS.Bits.PTS1
\r
15403 #define PTS_PTS2 _PTS.Bits.PTS2
\r
15404 #define PTS_PTS3 _PTS.Bits.PTS3
\r
15405 #define PTS_PTS4 _PTS.Bits.PTS4
\r
15406 #define PTS_PTS5 _PTS.Bits.PTS5
\r
15407 #define PTS_PTS6 _PTS.Bits.PTS6
\r
15408 #define PTS_PTS7 _PTS.Bits.PTS7
\r
15409 #define PTS_PTS _PTS.MergedBits.grpPTS
\r
15412 /*** PTIS - Port S Input; 0x00000249 ***/
\r
15416 byte PTIS0 :1; /* Port S Bit 0 */
\r
15417 byte PTIS1 :1; /* Port S Bit 1 */
\r
15418 byte PTIS2 :1; /* Port S Bit 2 */
\r
15419 byte PTIS3 :1; /* Port S Bit 3 */
\r
15420 byte PTIS4 :1; /* Port S Bit 4 */
\r
15421 byte PTIS5 :1; /* Port S Bit 5 */
\r
15422 byte PTIS6 :1; /* Port S Bit 6 */
\r
15423 byte PTIS7 :1; /* Port S Bit 7 */
\r
15429 extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);
\r
15430 #define PTIS _PTIS.Byte
\r
15431 #define PTIS_PTIS0 _PTIS.Bits.PTIS0
\r
15432 #define PTIS_PTIS1 _PTIS.Bits.PTIS1
\r
15433 #define PTIS_PTIS2 _PTIS.Bits.PTIS2
\r
15434 #define PTIS_PTIS3 _PTIS.Bits.PTIS3
\r
15435 #define PTIS_PTIS4 _PTIS.Bits.PTIS4
\r
15436 #define PTIS_PTIS5 _PTIS.Bits.PTIS5
\r
15437 #define PTIS_PTIS6 _PTIS.Bits.PTIS6
\r
15438 #define PTIS_PTIS7 _PTIS.Bits.PTIS7
\r
15439 #define PTIS_PTIS _PTIS.MergedBits.grpPTIS
\r
15442 /*** DDRS - Port S Data Direction Register; 0x0000024A ***/
\r
15446 byte DDRS0 :1; /* Data Direction Port S Bit 0 */
\r
15447 byte DDRS1 :1; /* Data Direction Port S Bit 1 */
\r
15448 byte DDRS2 :1; /* Data Direction Port S Bit 2 */
\r
15449 byte DDRS3 :1; /* Data Direction Port S Bit 3 */
\r
15450 byte DDRS4 :1; /* Data Direction Port S Bit 4 */
\r
15451 byte DDRS5 :1; /* Data Direction Port S Bit 5 */
\r
15452 byte DDRS6 :1; /* Data Direction Port S Bit 6 */
\r
15453 byte DDRS7 :1; /* Data Direction Port S Bit 7 */
\r
15459 extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);
\r
15460 #define DDRS _DDRS.Byte
\r
15461 #define DDRS_DDRS0 _DDRS.Bits.DDRS0
\r
15462 #define DDRS_DDRS1 _DDRS.Bits.DDRS1
\r
15463 #define DDRS_DDRS2 _DDRS.Bits.DDRS2
\r
15464 #define DDRS_DDRS3 _DDRS.Bits.DDRS3
\r
15465 #define DDRS_DDRS4 _DDRS.Bits.DDRS4
\r
15466 #define DDRS_DDRS5 _DDRS.Bits.DDRS5
\r
15467 #define DDRS_DDRS6 _DDRS.Bits.DDRS6
\r
15468 #define DDRS_DDRS7 _DDRS.Bits.DDRS7
\r
15469 #define DDRS_DDRS _DDRS.MergedBits.grpDDRS
\r
15472 /*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/
\r
15476 byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */
\r
15477 byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */
\r
15478 byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */
\r
15479 byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */
\r
15480 byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */
\r
15481 byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */
\r
15482 byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */
\r
15483 byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */
\r
15489 extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);
\r
15490 #define RDRS _RDRS.Byte
\r
15491 #define RDRS_RDRS0 _RDRS.Bits.RDRS0
\r
15492 #define RDRS_RDRS1 _RDRS.Bits.RDRS1
\r
15493 #define RDRS_RDRS2 _RDRS.Bits.RDRS2
\r
15494 #define RDRS_RDRS3 _RDRS.Bits.RDRS3
\r
15495 #define RDRS_RDRS4 _RDRS.Bits.RDRS4
\r
15496 #define RDRS_RDRS5 _RDRS.Bits.RDRS5
\r
15497 #define RDRS_RDRS6 _RDRS.Bits.RDRS6
\r
15498 #define RDRS_RDRS7 _RDRS.Bits.RDRS7
\r
15499 #define RDRS_RDRS _RDRS.MergedBits.grpRDRS
\r
15502 /*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/
\r
15506 byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */
\r
15507 byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */
\r
15508 byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */
\r
15509 byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */
\r
15510 byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */
\r
15511 byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */
\r
15512 byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */
\r
15513 byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */
\r
15519 extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);
\r
15520 #define PERS _PERS.Byte
\r
15521 #define PERS_PERS0 _PERS.Bits.PERS0
\r
15522 #define PERS_PERS1 _PERS.Bits.PERS1
\r
15523 #define PERS_PERS2 _PERS.Bits.PERS2
\r
15524 #define PERS_PERS3 _PERS.Bits.PERS3
\r
15525 #define PERS_PERS4 _PERS.Bits.PERS4
\r
15526 #define PERS_PERS5 _PERS.Bits.PERS5
\r
15527 #define PERS_PERS6 _PERS.Bits.PERS6
\r
15528 #define PERS_PERS7 _PERS.Bits.PERS7
\r
15529 #define PERS_PERS _PERS.MergedBits.grpPERS
\r
15532 /*** PPSS - Port S Polarity Select Register; 0x0000024D ***/
\r
15536 byte PPSS0 :1; /* Pull Select Port S Bit 0 */
\r
15537 byte PPSS1 :1; /* Pull Select Port S Bit 1 */
\r
15538 byte PPSS2 :1; /* Pull Select Port S Bit 2 */
\r
15539 byte PPSS3 :1; /* Pull Select Port S Bit 3 */
\r
15540 byte PPSS4 :1; /* Pull Select Port S Bit 4 */
\r
15541 byte PPSS5 :1; /* Pull Select Port S Bit 5 */
\r
15542 byte PPSS6 :1; /* Pull Select Port S Bit 6 */
\r
15543 byte PPSS7 :1; /* Pull Select Port S Bit 7 */
\r
15549 extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);
\r
15550 #define PPSS _PPSS.Byte
\r
15551 #define PPSS_PPSS0 _PPSS.Bits.PPSS0
\r
15552 #define PPSS_PPSS1 _PPSS.Bits.PPSS1
\r
15553 #define PPSS_PPSS2 _PPSS.Bits.PPSS2
\r
15554 #define PPSS_PPSS3 _PPSS.Bits.PPSS3
\r
15555 #define PPSS_PPSS4 _PPSS.Bits.PPSS4
\r
15556 #define PPSS_PPSS5 _PPSS.Bits.PPSS5
\r
15557 #define PPSS_PPSS6 _PPSS.Bits.PPSS6
\r
15558 #define PPSS_PPSS7 _PPSS.Bits.PPSS7
\r
15559 #define PPSS_PPSS _PPSS.MergedBits.grpPPSS
\r
15562 /*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/
\r
15566 byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */
\r
15567 byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */
\r
15568 byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */
\r
15569 byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */
\r
15570 byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */
\r
15571 byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */
\r
15572 byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */
\r
15573 byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */
\r
15579 extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);
\r
15580 #define WOMS _WOMS.Byte
\r
15581 #define WOMS_WOMS0 _WOMS.Bits.WOMS0
\r
15582 #define WOMS_WOMS1 _WOMS.Bits.WOMS1
\r
15583 #define WOMS_WOMS2 _WOMS.Bits.WOMS2
\r
15584 #define WOMS_WOMS3 _WOMS.Bits.WOMS3
\r
15585 #define WOMS_WOMS4 _WOMS.Bits.WOMS4
\r
15586 #define WOMS_WOMS5 _WOMS.Bits.WOMS5
\r
15587 #define WOMS_WOMS6 _WOMS.Bits.WOMS6
\r
15588 #define WOMS_WOMS7 _WOMS.Bits.WOMS7
\r
15589 #define WOMS_WOMS _WOMS.MergedBits.grpWOMS
\r
15592 /*** PTM - Port M I/O Register; 0x00000250 ***/
\r
15596 byte PTM0 :1; /* Port T Bit 0 */
\r
15597 byte PTM1 :1; /* Port T Bit 1 */
\r
15598 byte PTM2 :1; /* Port T Bit 2 */
\r
15599 byte PTM3 :1; /* Port T Bit 3 */
\r
15600 byte PTM4 :1; /* Port T Bit 4 */
\r
15601 byte PTM5 :1; /* Port T Bit 5 */
\r
15602 byte PTM6 :1; /* Port T Bit 6 */
\r
15603 byte PTM7 :1; /* Port T Bit 7 */
\r
15609 extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);
\r
15610 #define PTM _PTM.Byte
\r
15611 #define PTM_PTM0 _PTM.Bits.PTM0
\r
15612 #define PTM_PTM1 _PTM.Bits.PTM1
\r
15613 #define PTM_PTM2 _PTM.Bits.PTM2
\r
15614 #define PTM_PTM3 _PTM.Bits.PTM3
\r
15615 #define PTM_PTM4 _PTM.Bits.PTM4
\r
15616 #define PTM_PTM5 _PTM.Bits.PTM5
\r
15617 #define PTM_PTM6 _PTM.Bits.PTM6
\r
15618 #define PTM_PTM7 _PTM.Bits.PTM7
\r
15619 #define PTM_PTM _PTM.MergedBits.grpPTM
\r
15622 /*** PTIM - Port M Input; 0x00000251 ***/
\r
15626 byte PTIM0 :1; /* Port M Bit 0 */
\r
15627 byte PTIM1 :1; /* Port M Bit 1 */
\r
15628 byte PTIM2 :1; /* Port M Bit 2 */
\r
15629 byte PTIM3 :1; /* Port M Bit 3 */
\r
15630 byte PTIM4 :1; /* Port M Bit 4 */
\r
15631 byte PTIM5 :1; /* Port M Bit 5 */
\r
15632 byte PTIM6 :1; /* Port M Bit 6 */
\r
15633 byte PTIM7 :1; /* Port M Bit 7 */
\r
15639 extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);
\r
15640 #define PTIM _PTIM.Byte
\r
15641 #define PTIM_PTIM0 _PTIM.Bits.PTIM0
\r
15642 #define PTIM_PTIM1 _PTIM.Bits.PTIM1
\r
15643 #define PTIM_PTIM2 _PTIM.Bits.PTIM2
\r
15644 #define PTIM_PTIM3 _PTIM.Bits.PTIM3
\r
15645 #define PTIM_PTIM4 _PTIM.Bits.PTIM4
\r
15646 #define PTIM_PTIM5 _PTIM.Bits.PTIM5
\r
15647 #define PTIM_PTIM6 _PTIM.Bits.PTIM6
\r
15648 #define PTIM_PTIM7 _PTIM.Bits.PTIM7
\r
15649 #define PTIM_PTIM _PTIM.MergedBits.grpPTIM
\r
15652 /*** DDRM - Port M Data Direction Register; 0x00000252 ***/
\r
15656 byte DDRM0 :1; /* Data Direction Port M Bit 0 */
\r
15657 byte DDRM1 :1; /* Data Direction Port M Bit 1 */
\r
15658 byte DDRM2 :1; /* Data Direction Port M Bit 2 */
\r
15659 byte DDRM3 :1; /* Data Direction Port M Bit 3 */
\r
15660 byte DDRM4 :1; /* Data Direction Port M Bit 4 */
\r
15661 byte DDRM5 :1; /* Data Direction Port M Bit 5 */
\r
15662 byte DDRM6 :1; /* Data Direction Port M Bit 6 */
\r
15663 byte DDRM7 :1; /* Data Direction Port M Bit 7 */
\r
15669 extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);
\r
15670 #define DDRM _DDRM.Byte
\r
15671 #define DDRM_DDRM0 _DDRM.Bits.DDRM0
\r
15672 #define DDRM_DDRM1 _DDRM.Bits.DDRM1
\r
15673 #define DDRM_DDRM2 _DDRM.Bits.DDRM2
\r
15674 #define DDRM_DDRM3 _DDRM.Bits.DDRM3
\r
15675 #define DDRM_DDRM4 _DDRM.Bits.DDRM4
\r
15676 #define DDRM_DDRM5 _DDRM.Bits.DDRM5
\r
15677 #define DDRM_DDRM6 _DDRM.Bits.DDRM6
\r
15678 #define DDRM_DDRM7 _DDRM.Bits.DDRM7
\r
15679 #define DDRM_DDRM _DDRM.MergedBits.grpDDRM
\r
15682 /*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/
\r
15686 byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */
\r
15687 byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */
\r
15688 byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */
\r
15689 byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */
\r
15690 byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */
\r
15691 byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */
\r
15692 byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */
\r
15693 byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */
\r
15699 extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);
\r
15700 #define RDRM _RDRM.Byte
\r
15701 #define RDRM_RDRM0 _RDRM.Bits.RDRM0
\r
15702 #define RDRM_RDRM1 _RDRM.Bits.RDRM1
\r
15703 #define RDRM_RDRM2 _RDRM.Bits.RDRM2
\r
15704 #define RDRM_RDRM3 _RDRM.Bits.RDRM3
\r
15705 #define RDRM_RDRM4 _RDRM.Bits.RDRM4
\r
15706 #define RDRM_RDRM5 _RDRM.Bits.RDRM5
\r
15707 #define RDRM_RDRM6 _RDRM.Bits.RDRM6
\r
15708 #define RDRM_RDRM7 _RDRM.Bits.RDRM7
\r
15709 #define RDRM_RDRM _RDRM.MergedBits.grpRDRM
\r
15712 /*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/
\r
15716 byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */
\r
15717 byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */
\r
15718 byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */
\r
15719 byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */
\r
15720 byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */
\r
15721 byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */
\r
15722 byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */
\r
15723 byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */
\r
15729 extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);
\r
15730 #define PERM _PERM.Byte
\r
15731 #define PERM_PERM0 _PERM.Bits.PERM0
\r
15732 #define PERM_PERM1 _PERM.Bits.PERM1
\r
15733 #define PERM_PERM2 _PERM.Bits.PERM2
\r
15734 #define PERM_PERM3 _PERM.Bits.PERM3
\r
15735 #define PERM_PERM4 _PERM.Bits.PERM4
\r
15736 #define PERM_PERM5 _PERM.Bits.PERM5
\r
15737 #define PERM_PERM6 _PERM.Bits.PERM6
\r
15738 #define PERM_PERM7 _PERM.Bits.PERM7
\r
15739 #define PERM_PERM _PERM.MergedBits.grpPERM
\r
15742 /*** PPSM - Port M Polarity Select Register; 0x00000255 ***/
\r
15746 byte PPSM0 :1; /* Pull Select Port M Bit 0 */
\r
15747 byte PPSM1 :1; /* Pull Select Port M Bit 1 */
\r
15748 byte PPSM2 :1; /* Pull Select Port M Bit 2 */
\r
15749 byte PPSM3 :1; /* Pull Select Port M Bit 3 */
\r
15750 byte PPSM4 :1; /* Pull Select Port M Bit 4 */
\r
15751 byte PPSM5 :1; /* Pull Select Port M Bit 5 */
\r
15752 byte PPSM6 :1; /* Pull Select Port M Bit 6 */
\r
15753 byte PPSM7 :1; /* Pull Select Port M Bit 7 */
\r
15759 extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);
\r
15760 #define PPSM _PPSM.Byte
\r
15761 #define PPSM_PPSM0 _PPSM.Bits.PPSM0
\r
15762 #define PPSM_PPSM1 _PPSM.Bits.PPSM1
\r
15763 #define PPSM_PPSM2 _PPSM.Bits.PPSM2
\r
15764 #define PPSM_PPSM3 _PPSM.Bits.PPSM3
\r
15765 #define PPSM_PPSM4 _PPSM.Bits.PPSM4
\r
15766 #define PPSM_PPSM5 _PPSM.Bits.PPSM5
\r
15767 #define PPSM_PPSM6 _PPSM.Bits.PPSM6
\r
15768 #define PPSM_PPSM7 _PPSM.Bits.PPSM7
\r
15769 #define PPSM_PPSM _PPSM.MergedBits.grpPPSM
\r
15772 /*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/
\r
15776 byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */
\r
15777 byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */
\r
15778 byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */
\r
15779 byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */
\r
15780 byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */
\r
15781 byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */
\r
15782 byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */
\r
15783 byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */
\r
15789 extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);
\r
15790 #define WOMM _WOMM.Byte
\r
15791 #define WOMM_WOMM0 _WOMM.Bits.WOMM0
\r
15792 #define WOMM_WOMM1 _WOMM.Bits.WOMM1
\r
15793 #define WOMM_WOMM2 _WOMM.Bits.WOMM2
\r
15794 #define WOMM_WOMM3 _WOMM.Bits.WOMM3
\r
15795 #define WOMM_WOMM4 _WOMM.Bits.WOMM4
\r
15796 #define WOMM_WOMM5 _WOMM.Bits.WOMM5
\r
15797 #define WOMM_WOMM6 _WOMM.Bits.WOMM6
\r
15798 #define WOMM_WOMM7 _WOMM.Bits.WOMM7
\r
15799 #define WOMM_WOMM _WOMM.MergedBits.grpWOMM
\r
15802 /*** MODRR - Module Routing Register; 0x00000257 ***/
\r
15806 byte MODRR0 :1; /* CAN0 Routing */
\r
15807 byte MODRR1 :1; /* CAN0 Routing */
\r
15808 byte MODRR2 :1; /* CAN4 Routing */
\r
15809 byte MODRR3 :1; /* CAN4 Routing */
\r
15810 byte MODRR4 :1; /* SPI0 Routing */
\r
15811 byte MODRR5 :1; /* SPI1 Routing */
\r
15812 byte MODRR6 :1; /* SPI2 Routing */
\r
15816 byte grpMODRR :7;
\r
15820 extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257);
\r
15821 #define MODRR _MODRR.Byte
\r
15822 #define MODRR_MODRR0 _MODRR.Bits.MODRR0
\r
15823 #define MODRR_MODRR1 _MODRR.Bits.MODRR1
\r
15824 #define MODRR_MODRR2 _MODRR.Bits.MODRR2
\r
15825 #define MODRR_MODRR3 _MODRR.Bits.MODRR3
\r
15826 #define MODRR_MODRR4 _MODRR.Bits.MODRR4
\r
15827 #define MODRR_MODRR5 _MODRR.Bits.MODRR5
\r
15828 #define MODRR_MODRR6 _MODRR.Bits.MODRR6
\r
15829 #define MODRR_MODRR _MODRR.MergedBits.grpMODRR
\r
15832 /*** PTP - Port P I/O Register; 0x00000258 ***/
\r
15836 byte PTP0 :1; /* Port P Bit 0 */
\r
15837 byte PTP1 :1; /* Port P Bit 1 */
\r
15838 byte PTP2 :1; /* Port P Bit 2 */
\r
15839 byte PTP3 :1; /* Port P Bit 3 */
\r
15840 byte PTP4 :1; /* Port P Bit 4 */
\r
15841 byte PTP5 :1; /* Port P Bit 5 */
\r
15842 byte PTP6 :1; /* Port P Bit 6 */
\r
15843 byte PTP7 :1; /* Port P Bit 7 */
\r
15849 extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);
\r
15850 #define PTP _PTP.Byte
\r
15851 #define PTP_PTP0 _PTP.Bits.PTP0
\r
15852 #define PTP_PTP1 _PTP.Bits.PTP1
\r
15853 #define PTP_PTP2 _PTP.Bits.PTP2
\r
15854 #define PTP_PTP3 _PTP.Bits.PTP3
\r
15855 #define PTP_PTP4 _PTP.Bits.PTP4
\r
15856 #define PTP_PTP5 _PTP.Bits.PTP5
\r
15857 #define PTP_PTP6 _PTP.Bits.PTP6
\r
15858 #define PTP_PTP7 _PTP.Bits.PTP7
\r
15859 #define PTP_PTP _PTP.MergedBits.grpPTP
\r
15862 /*** PTIP - Port P Input; 0x00000259 ***/
\r
15866 byte PTIP0 :1; /* Port P Bit 0 */
\r
15867 byte PTIP1 :1; /* Port P Bit 1 */
\r
15868 byte PTIP2 :1; /* Port P Bit 2 */
\r
15869 byte PTIP3 :1; /* Port P Bit 3 */
\r
15870 byte PTIP4 :1; /* Port P Bit 4 */
\r
15871 byte PTIP5 :1; /* Port P Bit 5 */
\r
15872 byte PTIP6 :1; /* Port P Bit 6 */
\r
15873 byte PTIP7 :1; /* Port P Bit 7 */
\r
15879 extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);
\r
15880 #define PTIP _PTIP.Byte
\r
15881 #define PTIP_PTIP0 _PTIP.Bits.PTIP0
\r
15882 #define PTIP_PTIP1 _PTIP.Bits.PTIP1
\r
15883 #define PTIP_PTIP2 _PTIP.Bits.PTIP2
\r
15884 #define PTIP_PTIP3 _PTIP.Bits.PTIP3
\r
15885 #define PTIP_PTIP4 _PTIP.Bits.PTIP4
\r
15886 #define PTIP_PTIP5 _PTIP.Bits.PTIP5
\r
15887 #define PTIP_PTIP6 _PTIP.Bits.PTIP6
\r
15888 #define PTIP_PTIP7 _PTIP.Bits.PTIP7
\r
15889 #define PTIP_PTIP _PTIP.MergedBits.grpPTIP
\r
15892 /*** DDRP - Port P Data Direction Register; 0x0000025A ***/
\r
15896 byte DDRP0 :1; /* Data Direction Port P Bit 0 */
\r
15897 byte DDRP1 :1; /* Data Direction Port P Bit 1 */
\r
15898 byte DDRP2 :1; /* Data Direction Port P Bit 2 */
\r
15899 byte DDRP3 :1; /* Data Direction Port P Bit 3 */
\r
15900 byte DDRP4 :1; /* Data Direction Port P Bit 4 */
\r
15901 byte DDRP5 :1; /* Data Direction Port P Bit 5 */
\r
15902 byte DDRP6 :1; /* Data Direction Port P Bit 6 */
\r
15903 byte DDRP7 :1; /* Data Direction Port P Bit 7 */
\r
15909 extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);
\r
15910 #define DDRP _DDRP.Byte
\r
15911 #define DDRP_DDRP0 _DDRP.Bits.DDRP0
\r
15912 #define DDRP_DDRP1 _DDRP.Bits.DDRP1
\r
15913 #define DDRP_DDRP2 _DDRP.Bits.DDRP2
\r
15914 #define DDRP_DDRP3 _DDRP.Bits.DDRP3
\r
15915 #define DDRP_DDRP4 _DDRP.Bits.DDRP4
\r
15916 #define DDRP_DDRP5 _DDRP.Bits.DDRP5
\r
15917 #define DDRP_DDRP6 _DDRP.Bits.DDRP6
\r
15918 #define DDRP_DDRP7 _DDRP.Bits.DDRP7
\r
15919 #define DDRP_DDRP _DDRP.MergedBits.grpDDRP
\r
15922 /*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/
\r
15926 byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */
\r
15927 byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */
\r
15928 byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */
\r
15929 byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */
\r
15930 byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */
\r
15931 byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */
\r
15932 byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */
\r
15933 byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */
\r
15939 extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);
\r
15940 #define RDRP _RDRP.Byte
\r
15941 #define RDRP_RDRP0 _RDRP.Bits.RDRP0
\r
15942 #define RDRP_RDRP1 _RDRP.Bits.RDRP1
\r
15943 #define RDRP_RDRP2 _RDRP.Bits.RDRP2
\r
15944 #define RDRP_RDRP3 _RDRP.Bits.RDRP3
\r
15945 #define RDRP_RDRP4 _RDRP.Bits.RDRP4
\r
15946 #define RDRP_RDRP5 _RDRP.Bits.RDRP5
\r
15947 #define RDRP_RDRP6 _RDRP.Bits.RDRP6
\r
15948 #define RDRP_RDRP7 _RDRP.Bits.RDRP7
\r
15949 #define RDRP_RDRP _RDRP.MergedBits.grpRDRP
\r
15952 /*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/
\r
15956 byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */
\r
15957 byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */
\r
15958 byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */
\r
15959 byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */
\r
15960 byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */
\r
15961 byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */
\r
15962 byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */
\r
15963 byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */
\r
15969 extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);
\r
15970 #define PERP _PERP.Byte
\r
15971 #define PERP_PERP0 _PERP.Bits.PERP0
\r
15972 #define PERP_PERP1 _PERP.Bits.PERP1
\r
15973 #define PERP_PERP2 _PERP.Bits.PERP2
\r
15974 #define PERP_PERP3 _PERP.Bits.PERP3
\r
15975 #define PERP_PERP4 _PERP.Bits.PERP4
\r
15976 #define PERP_PERP5 _PERP.Bits.PERP5
\r
15977 #define PERP_PERP6 _PERP.Bits.PERP6
\r
15978 #define PERP_PERP7 _PERP.Bits.PERP7
\r
15979 #define PERP_PERP _PERP.MergedBits.grpPERP
\r
15982 /*** PPSP - Port P Polarity Select Register; 0x0000025D ***/
\r
15986 byte PPSP0 :1; /* Pull Select Port P Bit 0 */
\r
15987 byte PPSP1 :1; /* Pull Select Port P Bit 1 */
\r
15988 byte PPSP2 :1; /* Pull Select Port P Bit 2 */
\r
15989 byte PPSP3 :1; /* Pull Select Port P Bit 3 */
\r
15990 byte PPSP4 :1; /* Pull Select Port P Bit 4 */
\r
15991 byte PPSP5 :1; /* Pull Select Port P Bit 5 */
\r
15992 byte PPSP6 :1; /* Pull Select Port P Bit 6 */
\r
15993 byte PPSP7 :1; /* Pull Select Port P Bit 7 */
\r
15999 extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);
\r
16000 #define PPSP _PPSP.Byte
\r
16001 #define PPSP_PPSP0 _PPSP.Bits.PPSP0
\r
16002 #define PPSP_PPSP1 _PPSP.Bits.PPSP1
\r
16003 #define PPSP_PPSP2 _PPSP.Bits.PPSP2
\r
16004 #define PPSP_PPSP3 _PPSP.Bits.PPSP3
\r
16005 #define PPSP_PPSP4 _PPSP.Bits.PPSP4
\r
16006 #define PPSP_PPSP5 _PPSP.Bits.PPSP5
\r
16007 #define PPSP_PPSP6 _PPSP.Bits.PPSP6
\r
16008 #define PPSP_PPSP7 _PPSP.Bits.PPSP7
\r
16009 #define PPSP_PPSP _PPSP.MergedBits.grpPPSP
\r
16012 /*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/
\r
16016 byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */
\r
16017 byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */
\r
16018 byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */
\r
16019 byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */
\r
16020 byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */
\r
16021 byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */
\r
16022 byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */
\r
16023 byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */
\r
16029 extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);
\r
16030 #define PIEP _PIEP.Byte
\r
16031 #define PIEP_PIEP0 _PIEP.Bits.PIEP0
\r
16032 #define PIEP_PIEP1 _PIEP.Bits.PIEP1
\r
16033 #define PIEP_PIEP2 _PIEP.Bits.PIEP2
\r
16034 #define PIEP_PIEP3 _PIEP.Bits.PIEP3
\r
16035 #define PIEP_PIEP4 _PIEP.Bits.PIEP4
\r
16036 #define PIEP_PIEP5 _PIEP.Bits.PIEP5
\r
16037 #define PIEP_PIEP6 _PIEP.Bits.PIEP6
\r
16038 #define PIEP_PIEP7 _PIEP.Bits.PIEP7
\r
16039 #define PIEP_PIEP _PIEP.MergedBits.grpPIEP
\r
16042 /*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/
\r
16046 byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */
\r
16047 byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */
\r
16048 byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */
\r
16049 byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */
\r
16050 byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */
\r
16051 byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */
\r
16052 byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */
\r
16053 byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */
\r
16059 extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);
\r
16060 #define PIFP _PIFP.Byte
\r
16061 #define PIFP_PIFP0 _PIFP.Bits.PIFP0
\r
16062 #define PIFP_PIFP1 _PIFP.Bits.PIFP1
\r
16063 #define PIFP_PIFP2 _PIFP.Bits.PIFP2
\r
16064 #define PIFP_PIFP3 _PIFP.Bits.PIFP3
\r
16065 #define PIFP_PIFP4 _PIFP.Bits.PIFP4
\r
16066 #define PIFP_PIFP5 _PIFP.Bits.PIFP5
\r
16067 #define PIFP_PIFP6 _PIFP.Bits.PIFP6
\r
16068 #define PIFP_PIFP7 _PIFP.Bits.PIFP7
\r
16069 #define PIFP_PIFP _PIFP.MergedBits.grpPIFP
\r
16072 /*** PTH - Port H I/O Register; 0x00000260 ***/
\r
16076 byte PTH0 :1; /* Port H Bit 0 */
\r
16077 byte PTH1 :1; /* Port H Bit 1 */
\r
16078 byte PTH2 :1; /* Port H Bit 2 */
\r
16079 byte PTH3 :1; /* Port H Bit 3 */
\r
16080 byte PTH4 :1; /* Port H Bit 4 */
\r
16081 byte PTH5 :1; /* Port H Bit 5 */
\r
16082 byte PTH6 :1; /* Port H Bit 6 */
\r
16083 byte PTH7 :1; /* Port H Bit 7 */
\r
16089 extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260);
\r
16090 #define PTH _PTH.Byte
\r
16091 #define PTH_PTH0 _PTH.Bits.PTH0
\r
16092 #define PTH_PTH1 _PTH.Bits.PTH1
\r
16093 #define PTH_PTH2 _PTH.Bits.PTH2
\r
16094 #define PTH_PTH3 _PTH.Bits.PTH3
\r
16095 #define PTH_PTH4 _PTH.Bits.PTH4
\r
16096 #define PTH_PTH5 _PTH.Bits.PTH5
\r
16097 #define PTH_PTH6 _PTH.Bits.PTH6
\r
16098 #define PTH_PTH7 _PTH.Bits.PTH7
\r
16099 #define PTH_PTH _PTH.MergedBits.grpPTH
\r
16102 /*** PTIH - Port H Input Register; 0x00000261 ***/
\r
16106 byte PTIH0 :1; /* Port H Bit 0 */
\r
16107 byte PTIH1 :1; /* Port H Bit 1 */
\r
16108 byte PTIH2 :1; /* Port H Bit 2 */
\r
16109 byte PTIH3 :1; /* Port H Bit 3 */
\r
16110 byte PTIH4 :1; /* Port H Bit 4 */
\r
16111 byte PTIH5 :1; /* Port H Bit 5 */
\r
16112 byte PTIH6 :1; /* Port H Bit 6 */
\r
16113 byte PTIH7 :1; /* Port H Bit 7 */
\r
16119 extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261);
\r
16120 #define PTIH _PTIH.Byte
\r
16121 #define PTIH_PTIH0 _PTIH.Bits.PTIH0
\r
16122 #define PTIH_PTIH1 _PTIH.Bits.PTIH1
\r
16123 #define PTIH_PTIH2 _PTIH.Bits.PTIH2
\r
16124 #define PTIH_PTIH3 _PTIH.Bits.PTIH3
\r
16125 #define PTIH_PTIH4 _PTIH.Bits.PTIH4
\r
16126 #define PTIH_PTIH5 _PTIH.Bits.PTIH5
\r
16127 #define PTIH_PTIH6 _PTIH.Bits.PTIH6
\r
16128 #define PTIH_PTIH7 _PTIH.Bits.PTIH7
\r
16129 #define PTIH_PTIH _PTIH.MergedBits.grpPTIH
\r
16132 /*** DDRH - Port H Data Direction Register; 0x00000262 ***/
\r
16136 byte DDRH0 :1; /* Data Direction Port H Bit 0 */
\r
16137 byte DDRH1 :1; /* Data Direction Port H Bit 1 */
\r
16138 byte DDRH2 :1; /* Data Direction Port H Bit 2 */
\r
16139 byte DDRH3 :1; /* Data Direction Port H Bit 3 */
\r
16140 byte DDRH4 :1; /* Data Direction Port H Bit 4 */
\r
16141 byte DDRH5 :1; /* Data Direction Port H Bit 5 */
\r
16142 byte DDRH6 :1; /* Data Direction Port H Bit 6 */
\r
16143 byte DDRH7 :1; /* Data Direction Port H Bit 7 */
\r
16149 extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262);
\r
16150 #define DDRH _DDRH.Byte
\r
16151 #define DDRH_DDRH0 _DDRH.Bits.DDRH0
\r
16152 #define DDRH_DDRH1 _DDRH.Bits.DDRH1
\r
16153 #define DDRH_DDRH2 _DDRH.Bits.DDRH2
\r
16154 #define DDRH_DDRH3 _DDRH.Bits.DDRH3
\r
16155 #define DDRH_DDRH4 _DDRH.Bits.DDRH4
\r
16156 #define DDRH_DDRH5 _DDRH.Bits.DDRH5
\r
16157 #define DDRH_DDRH6 _DDRH.Bits.DDRH6
\r
16158 #define DDRH_DDRH7 _DDRH.Bits.DDRH7
\r
16159 #define DDRH_DDRH _DDRH.MergedBits.grpDDRH
\r
16162 /*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/
\r
16166 byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */
\r
16167 byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */
\r
16168 byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */
\r
16169 byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */
\r
16170 byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */
\r
16171 byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */
\r
16172 byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */
\r
16173 byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */
\r
16179 extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263);
\r
16180 #define RDRH _RDRH.Byte
\r
16181 #define RDRH_RDRH0 _RDRH.Bits.RDRH0
\r
16182 #define RDRH_RDRH1 _RDRH.Bits.RDRH1
\r
16183 #define RDRH_RDRH2 _RDRH.Bits.RDRH2
\r
16184 #define RDRH_RDRH3 _RDRH.Bits.RDRH3
\r
16185 #define RDRH_RDRH4 _RDRH.Bits.RDRH4
\r
16186 #define RDRH_RDRH5 _RDRH.Bits.RDRH5
\r
16187 #define RDRH_RDRH6 _RDRH.Bits.RDRH6
\r
16188 #define RDRH_RDRH7 _RDRH.Bits.RDRH7
\r
16189 #define RDRH_RDRH _RDRH.MergedBits.grpRDRH
\r
16192 /*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/
\r
16196 byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */
\r
16197 byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */
\r
16198 byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */
\r
16199 byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */
\r
16200 byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */
\r
16201 byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */
\r
16202 byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */
\r
16203 byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */
\r
16209 extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264);
\r
16210 #define PERH _PERH.Byte
\r
16211 #define PERH_PERH0 _PERH.Bits.PERH0
\r
16212 #define PERH_PERH1 _PERH.Bits.PERH1
\r
16213 #define PERH_PERH2 _PERH.Bits.PERH2
\r
16214 #define PERH_PERH3 _PERH.Bits.PERH3
\r
16215 #define PERH_PERH4 _PERH.Bits.PERH4
\r
16216 #define PERH_PERH5 _PERH.Bits.PERH5
\r
16217 #define PERH_PERH6 _PERH.Bits.PERH6
\r
16218 #define PERH_PERH7 _PERH.Bits.PERH7
\r
16219 #define PERH_PERH _PERH.MergedBits.grpPERH
\r
16222 /*** PPSH - Port H Polarity Select Register; 0x00000265 ***/
\r
16226 byte PPSH0 :1; /* Pull Select Port H Bit 0 */
\r
16227 byte PPSH1 :1; /* Pull Select Port H Bit 1 */
\r
16228 byte PPSH2 :1; /* Pull Select Port H Bit 2 */
\r
16229 byte PPSH3 :1; /* Pull Select Port H Bit 3 */
\r
16230 byte PPSH4 :1; /* Pull Select Port H Bit 4 */
\r
16231 byte PPSH5 :1; /* Pull Select Port H Bit 5 */
\r
16232 byte PPSH6 :1; /* Pull Select Port H Bit 6 */
\r
16233 byte PPSH7 :1; /* Pull Select Port H Bit 7 */
\r
16239 extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265);
\r
16240 #define PPSH _PPSH.Byte
\r
16241 #define PPSH_PPSH0 _PPSH.Bits.PPSH0
\r
16242 #define PPSH_PPSH1 _PPSH.Bits.PPSH1
\r
16243 #define PPSH_PPSH2 _PPSH.Bits.PPSH2
\r
16244 #define PPSH_PPSH3 _PPSH.Bits.PPSH3
\r
16245 #define PPSH_PPSH4 _PPSH.Bits.PPSH4
\r
16246 #define PPSH_PPSH5 _PPSH.Bits.PPSH5
\r
16247 #define PPSH_PPSH6 _PPSH.Bits.PPSH6
\r
16248 #define PPSH_PPSH7 _PPSH.Bits.PPSH7
\r
16249 #define PPSH_PPSH _PPSH.MergedBits.grpPPSH
\r
16252 /*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/
\r
16256 byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */
\r
16257 byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */
\r
16258 byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */
\r
16259 byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */
\r
16260 byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */
\r
16261 byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */
\r
16262 byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */
\r
16263 byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */
\r
16269 extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266);
\r
16270 #define PIEH _PIEH.Byte
\r
16271 #define PIEH_PIEH0 _PIEH.Bits.PIEH0
\r
16272 #define PIEH_PIEH1 _PIEH.Bits.PIEH1
\r
16273 #define PIEH_PIEH2 _PIEH.Bits.PIEH2
\r
16274 #define PIEH_PIEH3 _PIEH.Bits.PIEH3
\r
16275 #define PIEH_PIEH4 _PIEH.Bits.PIEH4
\r
16276 #define PIEH_PIEH5 _PIEH.Bits.PIEH5
\r
16277 #define PIEH_PIEH6 _PIEH.Bits.PIEH6
\r
16278 #define PIEH_PIEH7 _PIEH.Bits.PIEH7
\r
16279 #define PIEH_PIEH _PIEH.MergedBits.grpPIEH
\r
16282 /*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/
\r
16286 byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */
\r
16287 byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */
\r
16288 byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */
\r
16289 byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */
\r
16290 byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */
\r
16291 byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */
\r
16292 byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */
\r
16293 byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */
\r
16299 extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267);
\r
16300 #define PIFH _PIFH.Byte
\r
16301 #define PIFH_PIFH0 _PIFH.Bits.PIFH0
\r
16302 #define PIFH_PIFH1 _PIFH.Bits.PIFH1
\r
16303 #define PIFH_PIFH2 _PIFH.Bits.PIFH2
\r
16304 #define PIFH_PIFH3 _PIFH.Bits.PIFH3
\r
16305 #define PIFH_PIFH4 _PIFH.Bits.PIFH4
\r
16306 #define PIFH_PIFH5 _PIFH.Bits.PIFH5
\r
16307 #define PIFH_PIFH6 _PIFH.Bits.PIFH6
\r
16308 #define PIFH_PIFH7 _PIFH.Bits.PIFH7
\r
16309 #define PIFH_PIFH _PIFH.MergedBits.grpPIFH
\r
16312 /*** PTJ - Port J I/O Register; 0x00000268 ***/
\r
16316 byte PTJ0 :1; /* Port J Bit 0 */
\r
16317 byte PTJ1 :1; /* Port J Bit 1 */
\r
16322 byte PTJ6 :1; /* Port J Bit 6 */
\r
16323 byte PTJ7 :1; /* Port J Bit 7 */
\r
16331 byte grpPTJ_6 :2;
\r
16334 extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);
\r
16335 #define PTJ _PTJ.Byte
\r
16336 #define PTJ_PTJ0 _PTJ.Bits.PTJ0
\r
16337 #define PTJ_PTJ1 _PTJ.Bits.PTJ1
\r
16338 #define PTJ_PTJ6 _PTJ.Bits.PTJ6
\r
16339 #define PTJ_PTJ7 _PTJ.Bits.PTJ7
\r
16340 #define PTJ_PTJ _PTJ.MergedBits.grpPTJ
\r
16341 #define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6
\r
16344 /*** PTIJ - Port J Input Register; 0x00000269 ***/
\r
16348 byte PTIJ0 :1; /* Port J Bit 0 */
\r
16349 byte PTIJ1 :1; /* Port J Bit 1 */
\r
16354 byte PTIJ6 :1; /* Port J Bit 6 */
\r
16355 byte PTIJ7 :1; /* Port J Bit 7 */
\r
16363 byte grpPTIJ_6 :2;
\r
16366 extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);
\r
16367 #define PTIJ _PTIJ.Byte
\r
16368 #define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0
\r
16369 #define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1
\r
16370 #define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6
\r
16371 #define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7
\r
16372 #define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ
\r
16373 #define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6
\r
16376 /*** DDRJ - Port J Data Direction Register; 0x0000026A ***/
\r
16380 byte DDRJ0 :1; /* Data Direction Port J Bit 0 */
\r
16381 byte DDRJ1 :1; /* Data Direction Port J Bit 1 */
\r
16386 byte DDRJ6 :1; /* Data Direction Port J Bit 6 */
\r
16387 byte DDRJ7 :1; /* Data Direction Port J Bit 7 */
\r
16395 byte grpDDRJ_6 :2;
\r
16398 extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);
\r
16399 #define DDRJ _DDRJ.Byte
\r
16400 #define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0
\r
16401 #define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1
\r
16402 #define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6
\r
16403 #define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7
\r
16404 #define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ
\r
16405 #define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6
\r
16408 /*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/
\r
16412 byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */
\r
16413 byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */
\r
16418 byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */
\r
16419 byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */
\r
16427 byte grpRDRJ_6 :2;
\r
16430 extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);
\r
16431 #define RDRJ _RDRJ.Byte
\r
16432 #define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0
\r
16433 #define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1
\r
16434 #define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6
\r
16435 #define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7
\r
16436 #define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ
\r
16437 #define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6
\r
16440 /*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/
\r
16444 byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */
\r
16445 byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */
\r
16450 byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */
\r
16451 byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */
\r
16459 byte grpPERJ_6 :2;
\r
16462 extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);
\r
16463 #define PERJ _PERJ.Byte
\r
16464 #define PERJ_PERJ0 _PERJ.Bits.PERJ0
\r
16465 #define PERJ_PERJ1 _PERJ.Bits.PERJ1
\r
16466 #define PERJ_PERJ6 _PERJ.Bits.PERJ6
\r
16467 #define PERJ_PERJ7 _PERJ.Bits.PERJ7
\r
16468 #define PERJ_PERJ _PERJ.MergedBits.grpPERJ
\r
16469 #define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6
\r
16472 /*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/
\r
16476 byte PPSJ0 :1; /* Pull Select Port J Bit 0 */
\r
16477 byte PPSJ1 :1; /* Pull Select Port J Bit 1 */
\r
16482 byte PPSJ6 :1; /* Pull Select Port J Bit 6 */
\r
16483 byte PPSJ7 :1; /* Pull Select Port J Bit 7 */
\r
16491 byte grpPPSJ_6 :2;
\r
16494 extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);
\r
16495 #define PPSJ _PPSJ.Byte
\r
16496 #define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0
\r
16497 #define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1
\r
16498 #define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6
\r
16499 #define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7
\r
16500 #define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ
\r
16501 #define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6
\r
16504 /*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/
\r
16508 byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */
\r
16509 byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */
\r
16514 byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */
\r
16515 byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */
\r
16523 byte grpPIEJ_6 :2;
\r
16526 extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);
\r
16527 #define PIEJ _PIEJ.Byte
\r
16528 #define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0
\r
16529 #define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1
\r
16530 #define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6
\r
16531 #define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7
\r
16532 #define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ
\r
16533 #define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6
\r
16536 /*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/
\r
16540 byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */
\r
16541 byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */
\r
16546 byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */
\r
16547 byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */
\r
16555 byte grpPIFJ_6 :2;
\r
16558 extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);
\r
16559 #define PIFJ _PIFJ.Byte
\r
16560 #define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0
\r
16561 #define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1
\r
16562 #define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6
\r
16563 #define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7
\r
16564 #define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ
\r
16565 #define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6
\r
16568 /*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/
\r
16572 byte INITRQ :1; /* Initialization Mode Request */
\r
16573 byte SLPRQ :1; /* Sleep Mode Request */
\r
16574 byte WUPE :1; /* Wake-Up Enable */
\r
16575 byte TIME :1; /* Timer Enable */
\r
16576 byte SYNCH :1; /* Synchronized Status */
\r
16577 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
16578 byte RXACT :1; /* Receiver Active Status */
\r
16579 byte RXFRM :1; /* Received Frame Flag */
\r
16582 extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280);
\r
16583 #define CAN4CTL0 _CAN4CTL0.Byte
\r
16584 #define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ
\r
16585 #define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ
\r
16586 #define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE
\r
16587 #define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME
\r
16588 #define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH
\r
16589 #define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI
\r
16590 #define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT
\r
16591 #define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM
\r
16594 /*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/
\r
16598 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
16599 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
16600 byte WUPM :1; /* Wake-Up Mode */
\r
16602 byte LISTEN :1; /* Listen Only Mode */
\r
16603 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
16604 byte CLKSRC :1; /* MSCAN4 Clock Source */
\r
16605 byte CANE :1; /* MSCAN4 Enable */
\r
16608 extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281);
\r
16609 #define CAN4CTL1 _CAN4CTL1.Byte
\r
16610 #define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK
\r
16611 #define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK
\r
16612 #define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM
\r
16613 #define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN
\r
16614 #define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB
\r
16615 #define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC
\r
16616 #define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE
\r
16619 /*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/
\r
16623 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
16624 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
16625 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
16626 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
16627 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
16628 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
16629 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
16630 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
16637 extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282);
\r
16638 #define CAN4BTR0 _CAN4BTR0.Byte
\r
16639 #define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0
\r
16640 #define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1
\r
16641 #define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2
\r
16642 #define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3
\r
16643 #define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4
\r
16644 #define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5
\r
16645 #define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0
\r
16646 #define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1
\r
16647 #define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP
\r
16648 #define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW
\r
16651 /*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/
\r
16655 byte TSEG10 :1; /* Time Segment 1 */
\r
16656 byte TSEG11 :1; /* Time Segment 1 */
\r
16657 byte TSEG12 :1; /* Time Segment 1 */
\r
16658 byte TSEG13 :1; /* Time Segment 1 */
\r
16659 byte TSEG20 :1; /* Time Segment 2 */
\r
16660 byte TSEG21 :1; /* Time Segment 2 */
\r
16661 byte TSEG22 :1; /* Time Segment 2 */
\r
16662 byte SAMP :1; /* Sampling */
\r
16665 byte grpTSEG_10 :4;
\r
16666 byte grpTSEG_20 :3;
\r
16670 extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283);
\r
16671 #define CAN4BTR1 _CAN4BTR1.Byte
\r
16672 #define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10
\r
16673 #define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11
\r
16674 #define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12
\r
16675 #define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13
\r
16676 #define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20
\r
16677 #define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21
\r
16678 #define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22
\r
16679 #define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP
\r
16680 #define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10
\r
16681 #define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20
\r
16682 #define CAN4BTR1_TSEG CAN4BTR1_TSEG_10
\r
16685 /*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/
\r
16689 byte RXF :1; /* Receive Buffer Full */
\r
16690 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
16691 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
16692 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
16693 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
16694 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
16695 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
16696 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
16701 byte grpTSTAT :2;
\r
16702 byte grpRSTAT :2;
\r
16707 extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284);
\r
16708 #define CAN4RFLG _CAN4RFLG.Byte
\r
16709 #define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF
\r
16710 #define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF
\r
16711 #define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0
\r
16712 #define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1
\r
16713 #define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0
\r
16714 #define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1
\r
16715 #define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF
\r
16716 #define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF
\r
16717 #define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT
\r
16718 #define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT
\r
16721 /*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/
\r
16725 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
16726 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
16727 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
16728 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
16729 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
16730 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
16731 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
16732 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
16737 byte grpTSTATE :2;
\r
16738 byte grpRSTATE :2;
\r
16743 extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285);
\r
16744 #define CAN4RIER _CAN4RIER.Byte
\r
16745 #define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE
\r
16746 #define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE
\r
16747 #define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0
\r
16748 #define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1
\r
16749 #define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0
\r
16750 #define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1
\r
16751 #define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE
\r
16752 #define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE
\r
16753 #define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE
\r
16754 #define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE
\r
16757 /*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/
\r
16761 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
16762 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
16763 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
16779 extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286);
\r
16780 #define CAN4TFLG _CAN4TFLG.Byte
\r
16781 #define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0
\r
16782 #define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1
\r
16783 #define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2
\r
16784 #define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE
\r
16787 /*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/
\r
16791 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
16792 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
16793 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
16801 byte grpTXEIE :3;
\r
16809 extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287);
\r
16810 #define CAN4TIER _CAN4TIER.Byte
\r
16811 #define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0
\r
16812 #define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1
\r
16813 #define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2
\r
16814 #define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE
\r
16817 /*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/
\r
16821 byte ABTRQ0 :1; /* Abort Request 0 */
\r
16822 byte ABTRQ1 :1; /* Abort Request 1 */
\r
16823 byte ABTRQ2 :1; /* Abort Request 2 */
\r
16831 byte grpABTRQ :3;
\r
16839 extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288);
\r
16840 #define CAN4TARQ _CAN4TARQ.Byte
\r
16841 #define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0
\r
16842 #define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1
\r
16843 #define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2
\r
16844 #define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ
\r
16847 /*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/
\r
16851 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
16852 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
16853 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
16861 byte grpABTAK :3;
\r
16869 extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289);
\r
16870 #define CAN4TAAK _CAN4TAAK.Byte
\r
16871 #define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0
\r
16872 #define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1
\r
16873 #define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2
\r
16874 #define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK
\r
16877 /*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/
\r
16881 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
16882 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
16883 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
16899 extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A);
\r
16900 #define CAN4TBSEL _CAN4TBSEL.Byte
\r
16901 #define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0
\r
16902 #define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1
\r
16903 #define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2
\r
16904 #define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX
\r
16907 /*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/
\r
16911 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
16912 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
16913 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
16915 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
16916 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
16921 byte grpIDHIT :3;
\r
16928 extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B);
\r
16929 #define CAN4IDAC _CAN4IDAC.Byte
\r
16930 #define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0
\r
16931 #define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1
\r
16932 #define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2
\r
16933 #define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0
\r
16934 #define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1
\r
16935 #define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT
\r
16936 #define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM
\r
16939 /*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/
\r
16943 byte RXERR0 :1; /* Bit 0 */
\r
16944 byte RXERR1 :1; /* Bit 1 */
\r
16945 byte RXERR2 :1; /* Bit 2 */
\r
16946 byte RXERR3 :1; /* Bit 3 */
\r
16947 byte RXERR4 :1; /* Bit 4 */
\r
16948 byte RXERR5 :1; /* Bit 5 */
\r
16949 byte RXERR6 :1; /* Bit 6 */
\r
16950 byte RXERR7 :1; /* Bit 7 */
\r
16953 byte grpRXERR :8;
\r
16956 extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E);
\r
16957 #define CAN4RXERR _CAN4RXERR.Byte
\r
16958 #define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0
\r
16959 #define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1
\r
16960 #define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2
\r
16961 #define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3
\r
16962 #define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4
\r
16963 #define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5
\r
16964 #define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6
\r
16965 #define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7
\r
16966 #define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR
\r
16969 /*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/
\r
16973 byte TXERR0 :1; /* Bit 0 */
\r
16974 byte TXERR1 :1; /* Bit 1 */
\r
16975 byte TXERR2 :1; /* Bit 2 */
\r
16976 byte TXERR3 :1; /* Bit 3 */
\r
16977 byte TXERR4 :1; /* Bit 4 */
\r
16978 byte TXERR5 :1; /* Bit 5 */
\r
16979 byte TXERR6 :1; /* Bit 6 */
\r
16980 byte TXERR7 :1; /* Bit 7 */
\r
16983 byte grpTXERR :8;
\r
16986 extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F);
\r
16987 #define CAN4TXERR _CAN4TXERR.Byte
\r
16988 #define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0
\r
16989 #define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1
\r
16990 #define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2
\r
16991 #define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3
\r
16992 #define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4
\r
16993 #define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5
\r
16994 #define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6
\r
16995 #define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7
\r
16996 #define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR
\r
16999 /*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/
\r
17003 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17004 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17005 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17006 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17007 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17008 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17009 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17010 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17016 extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290);
\r
17017 #define CAN4IDAR0 _CAN4IDAR0.Byte
\r
17018 #define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0
\r
17019 #define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1
\r
17020 #define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2
\r
17021 #define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3
\r
17022 #define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4
\r
17023 #define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5
\r
17024 #define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6
\r
17025 #define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7
\r
17026 #define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC
\r
17029 /*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/
\r
17033 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17034 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17035 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17036 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17037 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17038 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17039 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17040 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17046 extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291);
\r
17047 #define CAN4IDAR1 _CAN4IDAR1.Byte
\r
17048 #define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0
\r
17049 #define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1
\r
17050 #define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2
\r
17051 #define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3
\r
17052 #define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4
\r
17053 #define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5
\r
17054 #define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6
\r
17055 #define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7
\r
17056 #define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC
\r
17059 /*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/
\r
17063 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17064 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17065 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17066 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17067 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17068 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17069 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17070 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17076 extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292);
\r
17077 #define CAN4IDAR2 _CAN4IDAR2.Byte
\r
17078 #define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0
\r
17079 #define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1
\r
17080 #define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2
\r
17081 #define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3
\r
17082 #define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4
\r
17083 #define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5
\r
17084 #define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6
\r
17085 #define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7
\r
17086 #define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC
\r
17089 /*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/
\r
17093 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17094 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17095 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17096 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17097 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17098 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17099 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17100 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17106 extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293);
\r
17107 #define CAN4IDAR3 _CAN4IDAR3.Byte
\r
17108 #define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0
\r
17109 #define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1
\r
17110 #define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2
\r
17111 #define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3
\r
17112 #define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4
\r
17113 #define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5
\r
17114 #define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6
\r
17115 #define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7
\r
17116 #define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC
\r
17119 /*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/
\r
17123 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17124 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17125 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17126 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17127 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17128 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17129 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17130 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17136 extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294);
\r
17137 #define CAN4IDMR0 _CAN4IDMR0.Byte
\r
17138 #define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0
\r
17139 #define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1
\r
17140 #define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2
\r
17141 #define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3
\r
17142 #define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4
\r
17143 #define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5
\r
17144 #define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6
\r
17145 #define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7
\r
17146 #define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM
\r
17149 /*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/
\r
17153 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17154 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17155 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17156 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17157 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17158 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17159 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17160 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17166 extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295);
\r
17167 #define CAN4IDMR1 _CAN4IDMR1.Byte
\r
17168 #define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0
\r
17169 #define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1
\r
17170 #define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2
\r
17171 #define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3
\r
17172 #define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4
\r
17173 #define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5
\r
17174 #define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6
\r
17175 #define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7
\r
17176 #define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM
\r
17179 /*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/
\r
17183 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17184 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17185 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17186 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17187 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17188 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17189 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17190 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17196 extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296);
\r
17197 #define CAN4IDMR2 _CAN4IDMR2.Byte
\r
17198 #define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0
\r
17199 #define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1
\r
17200 #define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2
\r
17201 #define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3
\r
17202 #define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4
\r
17203 #define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5
\r
17204 #define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6
\r
17205 #define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7
\r
17206 #define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM
\r
17209 /*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/
\r
17213 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17214 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17215 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17216 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17217 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17218 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17219 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17220 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17226 extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297);
\r
17227 #define CAN4IDMR3 _CAN4IDMR3.Byte
\r
17228 #define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0
\r
17229 #define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1
\r
17230 #define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2
\r
17231 #define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3
\r
17232 #define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4
\r
17233 #define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5
\r
17234 #define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6
\r
17235 #define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7
\r
17236 #define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM
\r
17239 /*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/
\r
17243 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17244 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17245 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17246 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17247 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17248 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17249 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17250 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17256 extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298);
\r
17257 #define CAN4IDAR4 _CAN4IDAR4.Byte
\r
17258 #define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0
\r
17259 #define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1
\r
17260 #define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2
\r
17261 #define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3
\r
17262 #define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4
\r
17263 #define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5
\r
17264 #define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6
\r
17265 #define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7
\r
17266 #define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC
\r
17269 /*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/
\r
17273 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17274 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17275 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17276 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17277 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17278 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17279 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17280 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17286 extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299);
\r
17287 #define CAN4IDAR5 _CAN4IDAR5.Byte
\r
17288 #define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0
\r
17289 #define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1
\r
17290 #define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2
\r
17291 #define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3
\r
17292 #define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4
\r
17293 #define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5
\r
17294 #define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6
\r
17295 #define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7
\r
17296 #define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC
\r
17299 /*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/
\r
17303 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17304 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17305 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17306 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17307 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17308 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17309 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17310 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17316 extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A);
\r
17317 #define CAN4IDAR6 _CAN4IDAR6.Byte
\r
17318 #define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0
\r
17319 #define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1
\r
17320 #define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2
\r
17321 #define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3
\r
17322 #define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4
\r
17323 #define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5
\r
17324 #define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6
\r
17325 #define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7
\r
17326 #define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC
\r
17329 /*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/
\r
17333 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
17334 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
17335 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
17336 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
17337 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
17338 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
17339 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
17340 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
17346 extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B);
\r
17347 #define CAN4IDAR7 _CAN4IDAR7.Byte
\r
17348 #define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0
\r
17349 #define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1
\r
17350 #define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2
\r
17351 #define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3
\r
17352 #define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4
\r
17353 #define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5
\r
17354 #define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6
\r
17355 #define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7
\r
17356 #define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC
\r
17359 /*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/
\r
17363 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17364 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17365 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17366 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17367 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17368 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17369 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17370 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17376 extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C);
\r
17377 #define CAN4IDMR4 _CAN4IDMR4.Byte
\r
17378 #define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0
\r
17379 #define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1
\r
17380 #define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2
\r
17381 #define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3
\r
17382 #define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4
\r
17383 #define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5
\r
17384 #define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6
\r
17385 #define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7
\r
17386 #define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM
\r
17389 /*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/
\r
17393 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17394 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17395 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17396 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17397 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17398 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17399 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17400 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17406 extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D);
\r
17407 #define CAN4IDMR5 _CAN4IDMR5.Byte
\r
17408 #define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0
\r
17409 #define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1
\r
17410 #define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2
\r
17411 #define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3
\r
17412 #define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4
\r
17413 #define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5
\r
17414 #define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6
\r
17415 #define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7
\r
17416 #define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM
\r
17419 /*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/
\r
17423 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17424 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17425 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17426 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17427 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17428 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17429 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17430 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17436 extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E);
\r
17437 #define CAN4IDMR6 _CAN4IDMR6.Byte
\r
17438 #define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0
\r
17439 #define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1
\r
17440 #define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2
\r
17441 #define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3
\r
17442 #define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4
\r
17443 #define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5
\r
17444 #define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6
\r
17445 #define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7
\r
17446 #define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM
\r
17449 /*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/
\r
17453 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
17454 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
17455 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
17456 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
17457 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
17458 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
17459 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
17460 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
17466 extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F);
\r
17467 #define CAN4IDMR7 _CAN4IDMR7.Byte
\r
17468 #define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0
\r
17469 #define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1
\r
17470 #define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2
\r
17471 #define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3
\r
17472 #define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4
\r
17473 #define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5
\r
17474 #define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6
\r
17475 #define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7
\r
17476 #define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM
\r
17479 /*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/
\r
17483 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
17484 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
17485 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
17486 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
17487 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
17488 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
17489 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
17490 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
17493 byte grpID_21 :8;
\r
17496 extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0);
\r
17497 #define CAN4RXIDR0 _CAN4RXIDR0.Byte
\r
17498 #define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21
\r
17499 #define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22
\r
17500 #define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23
\r
17501 #define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24
\r
17502 #define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25
\r
17503 #define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26
\r
17504 #define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27
\r
17505 #define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28
\r
17506 #define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21
\r
17507 #define CAN4RXIDR0_ID CAN4RXIDR0_ID_21
\r
17510 /*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/
\r
17514 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
17515 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
17516 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
17517 byte IDE :1; /* ID Extended */
\r
17518 byte SRR :1; /* Substitute Remote Request */
\r
17519 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
17520 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
17521 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
17524 byte grpID_15 :3;
\r
17527 byte grpID_18 :3;
\r
17530 extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1);
\r
17531 #define CAN4RXIDR1 _CAN4RXIDR1.Byte
\r
17532 #define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15
\r
17533 #define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16
\r
17534 #define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17
\r
17535 #define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE
\r
17536 #define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR
\r
17537 #define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18
\r
17538 #define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19
\r
17539 #define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20
\r
17540 #define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15
\r
17541 #define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18
\r
17542 #define CAN4RXIDR1_ID CAN4RXIDR1_ID_15
\r
17545 /*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/
\r
17549 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
17550 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
17551 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
17552 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
17553 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
17554 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
17555 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
17556 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
17562 extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2);
\r
17563 #define CAN4RXIDR2 _CAN4RXIDR2.Byte
\r
17564 #define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7
\r
17565 #define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8
\r
17566 #define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9
\r
17567 #define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10
\r
17568 #define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11
\r
17569 #define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12
\r
17570 #define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13
\r
17571 #define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14
\r
17572 #define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7
\r
17573 #define CAN4RXIDR2_ID CAN4RXIDR2_ID_7
\r
17576 /*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/
\r
17580 byte RTR :1; /* Remote Transmission Request */
\r
17581 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
17582 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
17583 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
17584 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
17585 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
17586 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
17587 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
17594 extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3);
\r
17595 #define CAN4RXIDR3 _CAN4RXIDR3.Byte
\r
17596 #define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR
\r
17597 #define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0
\r
17598 #define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1
\r
17599 #define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2
\r
17600 #define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3
\r
17601 #define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4
\r
17602 #define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5
\r
17603 #define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6
\r
17604 #define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID
\r
17607 /*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/
\r
17611 byte DB0 :1; /* Data Bit 0 */
\r
17612 byte DB1 :1; /* Data Bit 1 */
\r
17613 byte DB2 :1; /* Data Bit 2 */
\r
17614 byte DB3 :1; /* Data Bit 3 */
\r
17615 byte DB4 :1; /* Data Bit 4 */
\r
17616 byte DB5 :1; /* Data Bit 5 */
\r
17617 byte DB6 :1; /* Data Bit 6 */
\r
17618 byte DB7 :1; /* Data Bit 7 */
\r
17624 extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4);
\r
17625 #define CAN4RXDSR0 _CAN4RXDSR0.Byte
\r
17626 #define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0
\r
17627 #define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1
\r
17628 #define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2
\r
17629 #define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3
\r
17630 #define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4
\r
17631 #define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5
\r
17632 #define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6
\r
17633 #define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7
\r
17634 #define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB
\r
17637 /*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/
\r
17641 byte DB0 :1; /* Data Bit 0 */
\r
17642 byte DB1 :1; /* Data Bit 1 */
\r
17643 byte DB2 :1; /* Data Bit 2 */
\r
17644 byte DB3 :1; /* Data Bit 3 */
\r
17645 byte DB4 :1; /* Data Bit 4 */
\r
17646 byte DB5 :1; /* Data Bit 5 */
\r
17647 byte DB6 :1; /* Data Bit 6 */
\r
17648 byte DB7 :1; /* Data Bit 7 */
\r
17654 extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5);
\r
17655 #define CAN4RXDSR1 _CAN4RXDSR1.Byte
\r
17656 #define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0
\r
17657 #define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1
\r
17658 #define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2
\r
17659 #define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3
\r
17660 #define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4
\r
17661 #define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5
\r
17662 #define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6
\r
17663 #define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7
\r
17664 #define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB
\r
17667 /*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/
\r
17671 byte DB0 :1; /* Data Bit 0 */
\r
17672 byte DB1 :1; /* Data Bit 1 */
\r
17673 byte DB2 :1; /* Data Bit 2 */
\r
17674 byte DB3 :1; /* Data Bit 3 */
\r
17675 byte DB4 :1; /* Data Bit 4 */
\r
17676 byte DB5 :1; /* Data Bit 5 */
\r
17677 byte DB6 :1; /* Data Bit 6 */
\r
17678 byte DB7 :1; /* Data Bit 7 */
\r
17684 extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6);
\r
17685 #define CAN4RXDSR2 _CAN4RXDSR2.Byte
\r
17686 #define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0
\r
17687 #define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1
\r
17688 #define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2
\r
17689 #define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3
\r
17690 #define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4
\r
17691 #define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5
\r
17692 #define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6
\r
17693 #define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7
\r
17694 #define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB
\r
17697 /*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/
\r
17701 byte DB0 :1; /* Data Bit 0 */
\r
17702 byte DB1 :1; /* Data Bit 1 */
\r
17703 byte DB2 :1; /* Data Bit 2 */
\r
17704 byte DB3 :1; /* Data Bit 3 */
\r
17705 byte DB4 :1; /* Data Bit 4 */
\r
17706 byte DB5 :1; /* Data Bit 5 */
\r
17707 byte DB6 :1; /* Data Bit 6 */
\r
17708 byte DB7 :1; /* Data Bit 7 */
\r
17714 extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7);
\r
17715 #define CAN4RXDSR3 _CAN4RXDSR3.Byte
\r
17716 #define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0
\r
17717 #define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1
\r
17718 #define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2
\r
17719 #define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3
\r
17720 #define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4
\r
17721 #define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5
\r
17722 #define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6
\r
17723 #define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7
\r
17724 #define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB
\r
17727 /*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/
\r
17731 byte DB0 :1; /* Data Bit 0 */
\r
17732 byte DB1 :1; /* Data Bit 1 */
\r
17733 byte DB2 :1; /* Data Bit 2 */
\r
17734 byte DB3 :1; /* Data Bit 3 */
\r
17735 byte DB4 :1; /* Data Bit 4 */
\r
17736 byte DB5 :1; /* Data Bit 5 */
\r
17737 byte DB6 :1; /* Data Bit 6 */
\r
17738 byte DB7 :1; /* Data Bit 7 */
\r
17744 extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8);
\r
17745 #define CAN4RXDSR4 _CAN4RXDSR4.Byte
\r
17746 #define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0
\r
17747 #define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1
\r
17748 #define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2
\r
17749 #define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3
\r
17750 #define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4
\r
17751 #define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5
\r
17752 #define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6
\r
17753 #define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7
\r
17754 #define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB
\r
17757 /*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/
\r
17761 byte DB0 :1; /* Data Bit 0 */
\r
17762 byte DB1 :1; /* Data Bit 1 */
\r
17763 byte DB2 :1; /* Data Bit 2 */
\r
17764 byte DB3 :1; /* Data Bit 3 */
\r
17765 byte DB4 :1; /* Data Bit 4 */
\r
17766 byte DB5 :1; /* Data Bit 5 */
\r
17767 byte DB6 :1; /* Data Bit 6 */
\r
17768 byte DB7 :1; /* Data Bit 7 */
\r
17774 extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9);
\r
17775 #define CAN4RXDSR5 _CAN4RXDSR5.Byte
\r
17776 #define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0
\r
17777 #define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1
\r
17778 #define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2
\r
17779 #define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3
\r
17780 #define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4
\r
17781 #define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5
\r
17782 #define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6
\r
17783 #define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7
\r
17784 #define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB
\r
17787 /*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/
\r
17791 byte DB0 :1; /* Data Bit 0 */
\r
17792 byte DB1 :1; /* Data Bit 1 */
\r
17793 byte DB2 :1; /* Data Bit 2 */
\r
17794 byte DB3 :1; /* Data Bit 3 */
\r
17795 byte DB4 :1; /* Data Bit 4 */
\r
17796 byte DB5 :1; /* Data Bit 5 */
\r
17797 byte DB6 :1; /* Data Bit 6 */
\r
17798 byte DB7 :1; /* Data Bit 7 */
\r
17804 extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA);
\r
17805 #define CAN4RXDSR6 _CAN4RXDSR6.Byte
\r
17806 #define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0
\r
17807 #define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1
\r
17808 #define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2
\r
17809 #define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3
\r
17810 #define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4
\r
17811 #define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5
\r
17812 #define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6
\r
17813 #define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7
\r
17814 #define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB
\r
17817 /*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/
\r
17821 byte DB0 :1; /* Data Bit 0 */
\r
17822 byte DB1 :1; /* Data Bit 1 */
\r
17823 byte DB2 :1; /* Data Bit 2 */
\r
17824 byte DB3 :1; /* Data Bit 3 */
\r
17825 byte DB4 :1; /* Data Bit 4 */
\r
17826 byte DB5 :1; /* Data Bit 5 */
\r
17827 byte DB6 :1; /* Data Bit 6 */
\r
17828 byte DB7 :1; /* Data Bit 7 */
\r
17834 extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB);
\r
17835 #define CAN4RXDSR7 _CAN4RXDSR7.Byte
\r
17836 #define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0
\r
17837 #define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1
\r
17838 #define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2
\r
17839 #define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3
\r
17840 #define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4
\r
17841 #define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5
\r
17842 #define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6
\r
17843 #define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7
\r
17844 #define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB
\r
17847 /*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/
\r
17851 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
17852 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
17853 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
17854 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
17868 extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC);
\r
17869 #define CAN4RXDLR _CAN4RXDLR.Byte
\r
17870 #define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0
\r
17871 #define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1
\r
17872 #define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2
\r
17873 #define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3
\r
17874 #define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC
\r
17877 /*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/
\r
17881 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
17882 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
17883 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
17884 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
17885 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
17886 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
17887 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
17888 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
17891 byte grpID_21 :8;
\r
17894 extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0);
\r
17895 #define CAN4TXIDR0 _CAN4TXIDR0.Byte
\r
17896 #define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21
\r
17897 #define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22
\r
17898 #define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23
\r
17899 #define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24
\r
17900 #define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25
\r
17901 #define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26
\r
17902 #define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27
\r
17903 #define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28
\r
17904 #define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21
\r
17905 #define CAN4TXIDR0_ID CAN4TXIDR0_ID_21
\r
17908 /*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/
\r
17912 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
17913 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
17914 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
17915 byte IDE :1; /* ID Extended */
\r
17916 byte SRR :1; /* Substitute Remote Request */
\r
17917 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
17918 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
17919 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
17922 byte grpID_15 :3;
\r
17925 byte grpID_18 :3;
\r
17928 extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1);
\r
17929 #define CAN4TXIDR1 _CAN4TXIDR1.Byte
\r
17930 #define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15
\r
17931 #define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16
\r
17932 #define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17
\r
17933 #define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE
\r
17934 #define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR
\r
17935 #define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18
\r
17936 #define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19
\r
17937 #define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20
\r
17938 #define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15
\r
17939 #define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18
\r
17940 #define CAN4TXIDR1_ID CAN4TXIDR1_ID_15
\r
17943 /*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/
\r
17947 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
17948 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
17949 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
17950 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
17951 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
17952 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
17953 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
17954 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
17960 extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2);
\r
17961 #define CAN4TXIDR2 _CAN4TXIDR2.Byte
\r
17962 #define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7
\r
17963 #define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8
\r
17964 #define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9
\r
17965 #define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10
\r
17966 #define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11
\r
17967 #define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12
\r
17968 #define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13
\r
17969 #define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14
\r
17970 #define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7
\r
17971 #define CAN4TXIDR2_ID CAN4TXIDR2_ID_7
\r
17974 /*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/
\r
17978 byte RTR :1; /* Remote Transmission Request */
\r
17979 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
17980 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
17981 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
17982 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
17983 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
17984 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
17985 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
17992 extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3);
\r
17993 #define CAN4TXIDR3 _CAN4TXIDR3.Byte
\r
17994 #define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR
\r
17995 #define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0
\r
17996 #define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1
\r
17997 #define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2
\r
17998 #define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3
\r
17999 #define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4
\r
18000 #define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5
\r
18001 #define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6
\r
18002 #define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID
\r
18005 /*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/
\r
18009 byte DB0 :1; /* Data Bit 0 */
\r
18010 byte DB1 :1; /* Data Bit 1 */
\r
18011 byte DB2 :1; /* Data Bit 2 */
\r
18012 byte DB3 :1; /* Data Bit 3 */
\r
18013 byte DB4 :1; /* Data Bit 4 */
\r
18014 byte DB5 :1; /* Data Bit 5 */
\r
18015 byte DB6 :1; /* Data Bit 6 */
\r
18016 byte DB7 :1; /* Data Bit 7 */
\r
18022 extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4);
\r
18023 #define CAN4TXDSR0 _CAN4TXDSR0.Byte
\r
18024 #define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0
\r
18025 #define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1
\r
18026 #define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2
\r
18027 #define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3
\r
18028 #define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4
\r
18029 #define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5
\r
18030 #define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6
\r
18031 #define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7
\r
18032 #define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB
\r
18035 /*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/
\r
18039 byte DB0 :1; /* Data Bit 0 */
\r
18040 byte DB1 :1; /* Data Bit 1 */
\r
18041 byte DB2 :1; /* Data Bit 2 */
\r
18042 byte DB3 :1; /* Data Bit 3 */
\r
18043 byte DB4 :1; /* Data Bit 4 */
\r
18044 byte DB5 :1; /* Data Bit 5 */
\r
18045 byte DB6 :1; /* Data Bit 6 */
\r
18046 byte DB7 :1; /* Data Bit 7 */
\r
18052 extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5);
\r
18053 #define CAN4TXDSR1 _CAN4TXDSR1.Byte
\r
18054 #define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0
\r
18055 #define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1
\r
18056 #define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2
\r
18057 #define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3
\r
18058 #define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4
\r
18059 #define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5
\r
18060 #define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6
\r
18061 #define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7
\r
18062 #define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB
\r
18065 /*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/
\r
18069 byte DB0 :1; /* Data Bit 0 */
\r
18070 byte DB1 :1; /* Data Bit 1 */
\r
18071 byte DB2 :1; /* Data Bit 2 */
\r
18072 byte DB3 :1; /* Data Bit 3 */
\r
18073 byte DB4 :1; /* Data Bit 4 */
\r
18074 byte DB5 :1; /* Data Bit 5 */
\r
18075 byte DB6 :1; /* Data Bit 6 */
\r
18076 byte DB7 :1; /* Data Bit 7 */
\r
18082 extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6);
\r
18083 #define CAN4TXDSR2 _CAN4TXDSR2.Byte
\r
18084 #define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0
\r
18085 #define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1
\r
18086 #define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2
\r
18087 #define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3
\r
18088 #define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4
\r
18089 #define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5
\r
18090 #define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6
\r
18091 #define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7
\r
18092 #define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB
\r
18095 /*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/
\r
18099 byte DB0 :1; /* Data Bit 0 */
\r
18100 byte DB1 :1; /* Data Bit 1 */
\r
18101 byte DB2 :1; /* Data Bit 2 */
\r
18102 byte DB3 :1; /* Data Bit 3 */
\r
18103 byte DB4 :1; /* Data Bit 4 */
\r
18104 byte DB5 :1; /* Data Bit 5 */
\r
18105 byte DB6 :1; /* Data Bit 6 */
\r
18106 byte DB7 :1; /* Data Bit 7 */
\r
18112 extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7);
\r
18113 #define CAN4TXDSR3 _CAN4TXDSR3.Byte
\r
18114 #define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0
\r
18115 #define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1
\r
18116 #define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2
\r
18117 #define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3
\r
18118 #define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4
\r
18119 #define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5
\r
18120 #define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6
\r
18121 #define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7
\r
18122 #define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB
\r
18125 /*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/
\r
18129 byte DB0 :1; /* Data Bit 0 */
\r
18130 byte DB1 :1; /* Data Bit 1 */
\r
18131 byte DB2 :1; /* Data Bit 2 */
\r
18132 byte DB3 :1; /* Data Bit 3 */
\r
18133 byte DB4 :1; /* Data Bit 4 */
\r
18134 byte DB5 :1; /* Data Bit 5 */
\r
18135 byte DB6 :1; /* Data Bit 6 */
\r
18136 byte DB7 :1; /* Data Bit 7 */
\r
18142 extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8);
\r
18143 #define CAN4TXDSR4 _CAN4TXDSR4.Byte
\r
18144 #define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0
\r
18145 #define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1
\r
18146 #define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2
\r
18147 #define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3
\r
18148 #define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4
\r
18149 #define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5
\r
18150 #define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6
\r
18151 #define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7
\r
18152 #define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB
\r
18155 /*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/
\r
18159 byte DB0 :1; /* Data Bit 0 */
\r
18160 byte DB1 :1; /* Data Bit 1 */
\r
18161 byte DB2 :1; /* Data Bit 2 */
\r
18162 byte DB3 :1; /* Data Bit 3 */
\r
18163 byte DB4 :1; /* Data Bit 4 */
\r
18164 byte DB5 :1; /* Data Bit 5 */
\r
18165 byte DB6 :1; /* Data Bit 6 */
\r
18166 byte DB7 :1; /* Data Bit 7 */
\r
18172 extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9);
\r
18173 #define CAN4TXDSR5 _CAN4TXDSR5.Byte
\r
18174 #define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0
\r
18175 #define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1
\r
18176 #define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2
\r
18177 #define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3
\r
18178 #define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4
\r
18179 #define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5
\r
18180 #define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6
\r
18181 #define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7
\r
18182 #define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB
\r
18185 /*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/
\r
18189 byte DB0 :1; /* Data Bit 0 */
\r
18190 byte DB1 :1; /* Data Bit 1 */
\r
18191 byte DB2 :1; /* Data Bit 2 */
\r
18192 byte DB3 :1; /* Data Bit 3 */
\r
18193 byte DB4 :1; /* Data Bit 4 */
\r
18194 byte DB5 :1; /* Data Bit 5 */
\r
18195 byte DB6 :1; /* Data Bit 6 */
\r
18196 byte DB7 :1; /* Data Bit 7 */
\r
18202 extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA);
\r
18203 #define CAN4TXDSR6 _CAN4TXDSR6.Byte
\r
18204 #define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0
\r
18205 #define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1
\r
18206 #define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2
\r
18207 #define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3
\r
18208 #define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4
\r
18209 #define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5
\r
18210 #define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6
\r
18211 #define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7
\r
18212 #define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB
\r
18215 /*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/
\r
18219 byte DB0 :1; /* Data Bit 0 */
\r
18220 byte DB1 :1; /* Data Bit 1 */
\r
18221 byte DB2 :1; /* Data Bit 2 */
\r
18222 byte DB3 :1; /* Data Bit 3 */
\r
18223 byte DB4 :1; /* Data Bit 4 */
\r
18224 byte DB5 :1; /* Data Bit 5 */
\r
18225 byte DB6 :1; /* Data Bit 6 */
\r
18226 byte DB7 :1; /* Data Bit 7 */
\r
18232 extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB);
\r
18233 #define CAN4TXDSR7 _CAN4TXDSR7.Byte
\r
18234 #define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0
\r
18235 #define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1
\r
18236 #define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2
\r
18237 #define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3
\r
18238 #define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4
\r
18239 #define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5
\r
18240 #define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6
\r
18241 #define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7
\r
18242 #define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB
\r
18245 /*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/
\r
18249 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
18250 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
18251 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
18252 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
18266 extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC);
\r
18267 #define CAN4TXDLR _CAN4TXDLR.Byte
\r
18268 #define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0
\r
18269 #define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1
\r
18270 #define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2
\r
18271 #define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3
\r
18272 #define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC
\r
18275 /*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/
\r
18279 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
18280 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
18281 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
18282 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
18283 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
18284 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
18285 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
18286 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
18292 extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF);
\r
18293 #define CAN4TXTBPR _CAN4TXTBPR.Byte
\r
18294 #define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0
\r
18295 #define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1
\r
18296 #define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2
\r
18297 #define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3
\r
18298 #define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4
\r
18299 #define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5
\r
18300 #define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6
\r
18301 #define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7
\r
18302 #define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO
\r
18305 /*** BDMSTS - BDM Status Register; 0x0000FF01 ***/
\r
18310 byte UNSEC :1; /* Unsecure */
\r
18311 byte CLKSW :1; /* Clock switch */
\r
18312 byte TRACE :1; /* TRACE1 BDM firmware command is being executed */
\r
18313 byte SDV :1; /* Shift data valid */
\r
18314 byte ENTAG :1; /* Tagging enable */
\r
18315 byte BDMACT :1; /* BDM active status */
\r
18316 byte ENBDM :1; /* Enable BDM */
\r
18319 extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);
\r
18320 #define BDMSTS _BDMSTS.Byte
\r
18321 #define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC
\r
18322 #define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW
\r
18323 #define BDMSTS_TRACE _BDMSTS.Bits.TRACE
\r
18324 #define BDMSTS_SDV _BDMSTS.Bits.SDV
\r
18325 #define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG
\r
18326 #define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT
\r
18327 #define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM
\r
18330 /*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/
\r
18334 byte CCR0 :1; /* BDM CCR Holding Bit 0 */
\r
18335 byte CCR1 :1; /* BDM CCR Holding Bit 1 */
\r
18336 byte CCR2 :1; /* BDM CCR Holding Bit 2 */
\r
18337 byte CCR3 :1; /* BDM CCR Holding Bit 3 */
\r
18338 byte CCR4 :1; /* BDM CCR Holding Bit 4 */
\r
18339 byte CCR5 :1; /* BDM CCR Holding Bit 5 */
\r
18340 byte CCR6 :1; /* BDM CCR Holding Bit 6 */
\r
18341 byte CCR7 :1; /* BDM CCR Holding Bit 7 */
\r
18347 extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);
\r
18348 #define BDMCCR _BDMCCR.Byte
\r
18349 #define BDMCCR_CCR0 _BDMCCR.Bits.CCR0
\r
18350 #define BDMCCR_CCR1 _BDMCCR.Bits.CCR1
\r
18351 #define BDMCCR_CCR2 _BDMCCR.Bits.CCR2
\r
18352 #define BDMCCR_CCR3 _BDMCCR.Bits.CCR3
\r
18353 #define BDMCCR_CCR4 _BDMCCR.Bits.CCR4
\r
18354 #define BDMCCR_CCR5 _BDMCCR.Bits.CCR5
\r
18355 #define BDMCCR_CCR6 _BDMCCR.Bits.CCR6
\r
18356 #define BDMCCR_CCR7 _BDMCCR.Bits.CCR7
\r
18357 #define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR
\r
18360 /*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/
\r
18367 byte REG11 :1; /* Internal register map position */
\r
18368 byte REG12 :1; /* Internal register map position */
\r
18369 byte REG13 :1; /* Internal register map position */
\r
18370 byte REG14 :1; /* Internal register map position */
\r
18371 byte REG15 :1; /* Internal register map position */
\r
18377 byte grpREG_11 :5;
\r
18380 extern volatile BDMINRSTR _BDMINR @(0x0000FF07);
\r
18381 #define BDMINR _BDMINR.Byte
\r
18382 #define BDMINR_REG11 _BDMINR.Bits.REG11
\r
18383 #define BDMINR_REG12 _BDMINR.Bits.REG12
\r
18384 #define BDMINR_REG13 _BDMINR.Bits.REG13
\r
18385 #define BDMINR_REG14 _BDMINR.Bits.REG14
\r
18386 #define BDMINR_REG15 _BDMINR.Bits.REG15
\r
18387 #define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11
\r
18388 #define BDMINR_REG BDMINR_REG_11
\r
18391 /* Watchdog reset macro */
\r
18393 #define __RESET_WATCHDOG() /* empty */
\r
18395 #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
\r
18401 ** ###################################################################
\r
18403 ** This file was created by UNIS Processor Expert 03.33 for
\r
18404 ** the Motorola HCS12 series of microcontrollers.
\r
18406 ** ###################################################################
\r