git.sur5r.net Git - freertos/blob - FreeRTOS-Labs/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/trcStreamingPort.c

   1 \r
   2 #include "trcRecorder.h"\r
   3 \r
   4 #if (TRC_USE_TRACEALYZER_RECORDER == 1)\r
   5 #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)\r
   6 \r
   7 static void itm_write_32(uint32_t data);\r
   8 \r
   9 volatile int32_t tz_host_command_bytes_to_read = 0; // This is set by the Tracealyzer host application (to the number of bytes written), after having written to tz_host_commands. Set to zero by the read function after the message in tz_host_commands has been read.\r
  10 volatile char tz_host_command_data[32];\r
  11 \r
  12 /* This reads "command" data from a RAM buffer, written by a host macro in the debugger */\r
  13 int32_t read_from_host(void* ptrData, uint32_t size, int32_t* ptrBytesRead)\r
  14 {\r
  15         if ( tz_host_command_bytes_to_read > 0)\r
  16         {               \r
  17                 int i;\r
  18                 uint8_t * bytesBuffer = (uint8_t*) ptrData;\r
  19 \r
  20                 if (ptrBytesRead != NULL)\r
  21                         *ptrBytesRead = (int32_t)tz_host_command_bytes_to_read;\r
  22         \r
  23                 if (tz_host_command_bytes_to_read != size)\r
  24                 {\r
  25                         return -1;\r
  26                 }\r
  27                         \r
  28                 for (i=0; i < tz_host_command_bytes_to_read; i++)\r
  29                 {\r
  30                         bytesBuffer[i] = tz_host_command_data[i];\r
  31                 }\r
  32                 \r
  33                 tz_host_command_bytes_to_read = 0;\r
  34         }\r
  35 \r
  36         return 0;\r
  37 }\r
  38 \r
  39 static void itm_write_32(uint32_t data)\r
  40 {       \r
  41      if   ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      // Trace enabled\r
  42            (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      // ITM enabled\r
  43            (ITM->TER & (1UL << TRC_CFG_ITM_PORT)))                  // ITM port enabled\r
  44     {\r
  45         while (ITM->PORT[TRC_CFG_ITM_PORT].u32 == 0);     // Block until room in ITM FIFO - This stream port is always in "blocking mode", since intended for high-speed ITM!\r
  46         ITM->PORT[TRC_CFG_ITM_PORT].u32 = data;           // Write the data\r
  47         }       \r
  48 }\r
  49 \r
  50 /* This is assumed to execute from within the recorder, with interrupts disabled */\r
  51 int32_t itm_write(void* ptrData, uint32_t size, int32_t* ptrBytesWritten)\r
  52 {\r
  53         uint32_t bytesWritten = 0;\r
  54         uint32_t* ptr32 = (uint32_t*)ptrData;\r
  55         \r
  56         if (size % 4 != 0) return -2;\r
  57                 \r
  58         while(bytesWritten < size)\r
  59         {\r
  60                 itm_write_32(*ptr32);\r
  61                 ptr32++;\r
  62                 bytesWritten += 4;\r
  63         }\r
  64 \r
  65         *ptrBytesWritten = bytesWritten;\r
  66         \r
  67         return 0;\r
  68 }\r
  69 \r
  70 #endif\r
  71 #endif\r