git.sur5r.net Git - freertos/blob - FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c

   1 /**********************************************************************\r
   2 * $Id$          lpc18xx_gpdma.c         2011-06-02\r
   3 *//**\r
   4 * @file         lpc18xx_gpdma.c\r
   5 * @brief        Contains all functions support for GPDMA firmware library\r
   6 *                       on LPC18xx\r
   7 * @version      1.0\r
   8 * @date         02. June. 2011\r
   9 * @author       NXP MCU SW Application Team\r
  10 *\r
  11 * Copyright(C) 2011, NXP Semiconductor\r
  12 * All rights reserved.\r
  13 *\r
  14 ***********************************************************************\r
  15 * Software that is described herein is for illustrative purposes only\r
  16 * which provides customers with programming information regarding the\r
  17 * products. This software is supplied "AS IS" without any warranties.\r
  18 * NXP Semiconductors assumes no responsibility or liability for the\r
  19 * use of the software, conveys no license or title under any patent,\r
  20 * copyright, or mask work right to the product. NXP Semiconductors\r
  21 * reserves the right to make changes in the software without\r
  22 * notification. NXP Semiconductors also make no representation or\r
  23 * warranty that such application will be suitable for the specified\r
  24 * use without further testing or modification.\r
  25 **********************************************************************/\r
  26 \r
  27 /* Peripheral group ----------------------------------------------------------- */\r
  28 /** @addtogroup GPDMA\r
  29  * @{\r
  30  */\r
  31 \r
  32 /* Includes ------------------------------------------------------------------- */\r
  33 #include "lpc18xx_gpdma.h"\r
  34 //#include "lpc18xx_cgu.h"\r
  35 \r
  36 /* If this source file built with example, the LPC18xx FW library configuration\r
  37  * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
  38  * otherwise the default FW library configuration file must be included instead\r
  39  */\r
  40 #ifdef __BUILD_WITH_EXAMPLE__\r
  41 #include "lpc18xx_libcfg.h"\r
  42 #else\r
  43 #include "lpc18xx_libcfg_default.h"\r
  44 #endif /* __BUILD_WITH_EXAMPLE__ */\r
  45 \r
  46 #ifdef _GPDMA\r
  47 \r
  48 /** GPDMA Mux definitions */\r
  49 #define DMAMUX_ADDRESS          0x4004311C\r
  50 \r
  51 /* Private Functions ----------------------------------------------------------- */\r
  52 /** @\r
  53  * @{\r
  54  */\r
  55 uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number);\r
  56 /**\r
  57  * @}\r
  58  */\r
  59 \r
  60 /* Private Variables ---------------------------------------------------------- */\r
  61 /** @defgroup GPDMA_Private_Variables GPDMA Private Variables\r
  62  * @{\r
  63  */\r
  64 \r
  65 /**\r
  66  * @brief Lookup Table of Connection Type matched with\r
  67  * Peripheral Data (FIFO) register base address\r
  68  */\r
  69 #ifdef __ICCARM__\r
  70 volatile const void *GPDMA_LUTPerAddr[] = {\r
  71                 (&LPC_SPIFI->DAT),                      // SPIFI\r
  72                 (&LPC_TIMER0->MR),                              // MAT0.0\r
  73                 (&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx\r
  74                 ((uint32_t*)&LPC_TIMER0->MR + 1),                               // MAT0.1\r
  75                 (&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx\r
  76                 (&LPC_TIMER1->MR),                              // MAT1.0\r
  77                 (&LPC_UART1->/*RBTHDLR.*/THR),  // UART1 Tx\r
  78                 ((uint32_t*)&LPC_TIMER1->MR + 1),                               // MAT1.1\r
  79                 (&LPC_UART1->/*RBTHDLR.*/RBR),  // UART1 Rx\r
  80                 (&LPC_TIMER2->MR),                              // MAT2.0\r
  81                 (&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx\r
  82                 ((uint32_t*)&LPC_TIMER2->MR + 1),                               // MAT2.1\r
  83                 (&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx\r
  84                 (&LPC_TIMER3->MR),                              // MAT3.0\r
  85                 (&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx\r
  86                 0,      // to be defined: SCT DMA request 0\r
  87                 ((uint32_t*)&LPC_TIMER3->MR + 1),                               // MAT3.1\r
  88                 (&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx\r
  89                 0,      // to be defined: SCT DMA request 1\r
  90                 (&LPC_SSP0->DR),                                // SSP0 Rx\r
  91                 (&LPC_I2S0->TXFIFO),                    // I2S channel 0\r
  92                 (&LPC_SSP0->DR),                                // SSP0 Tx\r
  93                 (&LPC_I2S0->RXFIFO),                    // I2S channel 1\r
  94                 (&LPC_SSP1->DR),                                // SSP1 Rx\r
  95                 (&LPC_SSP1->DR),                                // SSP1 Tx\r
  96                 (&LPC_ADC0->GDR),                               // ADC 0\r
  97                 (&LPC_ADC1->GDR),                               // ADC 1\r
  98                 (&LPC_DAC->CR)                          // DAC\r
  99 };\r
 100 #else\r
 101 const uint32_t GPDMA_LUTPerAddr[] = {\r
 102 //              ((uint32_t)&LPC_SPIFI->DAT),                    // SPIFI\r
 103                 ((uint32_t)0),                  // SPIFI\r
 104                 ((uint32_t)&LPC_TIMER0->MR[0]),                         // MAT0.0\r
 105                 ((uint32_t)&LPC_USART0->/*RBTHDLR.*/THR),       // UART0 Tx\r
 106                 ((uint32_t)&LPC_TIMER0->MR[1]),                         // MAT0.1\r
 107                 ((uint32_t)&LPC_USART0->/*RBTHDLR.*/RBR),       // UART0 Rx\r
 108                 ((uint32_t)&LPC_TIMER1->MR[0]),                         // MAT1.0\r
 109                 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR),        // UART1 Tx\r
 110                 ((uint32_t)&LPC_TIMER1->MR[1]),                         // MAT1.1\r
 111                 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR),        // UART1 Rx\r
 112                 ((uint32_t)&LPC_TIMER2->MR[0]),                         // MAT2.0\r
 113                 ((uint32_t)&LPC_USART2->/*RBTHDLR.*/THR),       // UART2 Tx\r
 114                 ((uint32_t)&LPC_TIMER2->MR[1]),                         // MAT2.1\r
 115                 ((uint32_t)&LPC_USART2->/*RBTHDLR.*/RBR),       // UART2 Rx\r
 116                 ((uint32_t)&LPC_TIMER3->MR[0]),                         // MAT3.0\r
 117                 ((uint32_t)&LPC_USART3->/*RBTHDLR.*/THR),       // UART3 Tx\r
 118                 0,      // to be defined: SCT DMA request 0\r
 119                 ((uint32_t)&LPC_TIMER3->MR[1]),                         // MAT3.1\r
 120                 ((uint32_t)&LPC_USART3->/*RBTHDLR.*/RBR),       // UART3 Rx\r
 121                 0,      // to be defined: SCT DMA request 1\r
 122                 ((uint32_t)&LPC_SSP0->DR),                              // SSP0 Rx\r
 123                 ((uint32_t)&LPC_I2S0->TXFIFO),                  // I2S channel 0\r
 124                 ((uint32_t)&LPC_SSP0->DR),                              // SSP0 Tx\r
 125                 ((uint32_t)&LPC_I2S0->RXFIFO),                  // I2S channel 1\r
 126                 ((uint32_t)&LPC_SSP1->DR),                              // SSP1 Rx\r
 127                 ((uint32_t)&LPC_SSP1->DR),                              // SSP1 Tx\r
 128                 ((uint32_t)&LPC_ADC0->GDR),                             // ADC 0\r
 129                 ((uint32_t)&LPC_ADC1->GDR),                             // ADC 1\r
 130                 ((uint32_t)&LPC_DAC->CR)                                // DAC\r
 131 };\r
 132 #endif\r
 133 /**\r
 134  * @brief Lookup Table of GPDMA Channel Number matched with\r
 135  * GPDMA channel pointer\r
 136  */\r
 137 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {\r
 138                 LPC_GPDMACH0,   // GPDMA Channel 0\r
 139                 LPC_GPDMACH1,   // GPDMA Channel 1\r
 140                 LPC_GPDMACH2,   // GPDMA Channel 2\r
 141                 LPC_GPDMACH3,   // GPDMA Channel 3\r
 142                 LPC_GPDMACH4,   // GPDMA Channel 4\r
 143                 LPC_GPDMACH5,   // GPDMA Channel 5\r
 144                 LPC_GPDMACH6,   // GPDMA Channel 6\r
 145                 LPC_GPDMACH7,   // GPDMA Channel 7\r
 146 };\r
 147 /**\r
 148  * @brief Optimized Peripheral Source and Destination burst size\r
 149  */\r
 150 const uint8_t GPDMA_LUTPerBurst[] = {\r
 151                 GPDMA_BSIZE_4,                          // SPIFI\r
 152                 GPDMA_BSIZE_1,                          // MAT0.0\r
 153                 GPDMA_BSIZE_1,                          // UART0 Tx\r
 154                 GPDMA_BSIZE_1,                          // MAT0.1\r
 155                 GPDMA_BSIZE_1,                          // UART0 Rx\r
 156                 GPDMA_BSIZE_1,                          // MAT1.0\r
 157                 GPDMA_BSIZE_1,                          // UART1 Tx\r
 158                 GPDMA_BSIZE_1,                          // MAT1.1\r
 159                 GPDMA_BSIZE_1,                          // UART1 Rx\r
 160                 GPDMA_BSIZE_1,                          // MAT2.0\r
 161                 GPDMA_BSIZE_1,                          // UART2 Tx\r
 162                 GPDMA_BSIZE_1,                          // MAT2.1\r
 163                 GPDMA_BSIZE_1,                          // UART2 Rx\r
 164                 GPDMA_BSIZE_1,                          // MAT3.0\r
 165                 GPDMA_BSIZE_1,                          // UART3 Tx\r
 166                 0,      // to be defined: SCT DMA request 0\r
 167                 GPDMA_BSIZE_1,                          // MAT3.1\r
 168                 GPDMA_BSIZE_1,                          // UART3 Rx\r
 169                 0,      // to be defined: SCT DMA request 1\r
 170                 GPDMA_BSIZE_4,                          // SSP0 Rx\r
 171                 GPDMA_BSIZE_32,                         // I2S channel 0\r
 172                 GPDMA_BSIZE_4,                          // SSP0 Tx\r
 173                 GPDMA_BSIZE_32,                         // I2S channel 1\r
 174                 GPDMA_BSIZE_4,                          // SSP1 Rx\r
 175                 GPDMA_BSIZE_4,                          // SSP1 Tx\r
 176                 GPDMA_BSIZE_4,                          // ADC 0\r
 177                 GPDMA_BSIZE_4,                          // ADC 1\r
 178                 GPDMA_BSIZE_1,                          // DAC\r
 179 };\r
 180 /**\r
 181  * @brief Optimized Peripheral Source and Destination transfer width\r
 182  */\r
 183 const uint8_t GPDMA_LUTPerWid[] = {\r
 184                 GPDMA_WIDTH_WORD,                               // SPIFI\r
 185                 GPDMA_WIDTH_WORD,                               // MAT0.0\r
 186                 GPDMA_WIDTH_BYTE,                               // UART0 Tx\r
 187                 GPDMA_WIDTH_WORD,                               // MAT0.1\r
 188                 GPDMA_WIDTH_BYTE,                               // UART0 Rx\r
 189                 GPDMA_WIDTH_WORD,                               // MAT1.0\r
 190                 GPDMA_WIDTH_BYTE,                               // UART1 Tx\r
 191                 GPDMA_WIDTH_WORD,                               // MAT1.1\r
 192                 GPDMA_WIDTH_BYTE,                               // UART1 Rx\r
 193                 GPDMA_WIDTH_WORD,                               // MAT2.0\r
 194                 GPDMA_WIDTH_BYTE,                               // UART2 Tx\r
 195                 GPDMA_WIDTH_WORD,                               // MAT2.1\r
 196                 GPDMA_WIDTH_BYTE,                               // UART2 Rx\r
 197                 GPDMA_WIDTH_WORD,                               // MAT3.0\r
 198                 GPDMA_WIDTH_BYTE,                               // UART3 Tx\r
 199                 0,      // to be defined: SCT DMA request 0\r
 200                 GPDMA_WIDTH_WORD,                               // MAT3.1\r
 201                 GPDMA_WIDTH_BYTE,                               // UART3 Rx\r
 202                 0,      // to be defined: SCT DMA request 1\r
 203                 GPDMA_WIDTH_BYTE,                               // SSP0 Rx\r
 204                 GPDMA_WIDTH_WORD,                               // I2S channel 0\r
 205                 GPDMA_WIDTH_BYTE,                               // SSP0 Tx\r
 206                 GPDMA_WIDTH_WORD,                               // I2S channel 1\r
 207                 GPDMA_WIDTH_BYTE,                               // SSP1 Rx\r
 208                 GPDMA_WIDTH_BYTE,                               // SSP1 Tx\r
 209                 GPDMA_WIDTH_WORD,                               // ADC 0\r
 210                 GPDMA_WIDTH_WORD,                               // ADC 1\r
 211                 GPDMA_WIDTH_WORD,                               // DAC\r
 212 };\r
 213 \r
 214 /**\r
 215  * @}\r
 216  */\r
 217 \r
 218 /* Private Functions ----------------------------------------------------------- */\r
 219 /** @\r
 220  * @{\r
 221  */\r
 222 \r
 223 /********************************************************************//**\r
 224  * @brief               Control which set of peripherals is connected to the\r
 225  *                              DMA controller\r
 226  * @param[in]   gpdma_peripheral_connection_number      GPDMA peripheral\r
 227  *                              connection number, should be:\r
 228  *                                      - GPDMA_CONN_SPIFI                      :SPIFI\r
 229  *                                      - GPDMA_CONN_MAT0_0                     :Timer 0, match channel 0\r
 230  *                                      - GPDMA_CONN_MAT0_1                     :Timer 0, match channel 1\r
 231  *                                      - GPDMA_CONN_MAT1_0                     :Timer 1, match channel 0\r
 232  *                                      - GPDMA_CONN_MAT1_1                     :Timer 1, match channel 1\r
 233  *                                      - GPDMA_CONN_MAT2_0                     :Timer 2, match channel 0\r
 234  *                                      - GPDMA_CONN_MAT2_1                     :Timer 2, match channel 1\r
 235  *                                      - GPDMA_CONN_MAT3_0                     :Timer 3, match channel 0\r
 236  *                                      - GPDMA_CONN_MAT3_1                     :Timer 3, match channel 1\r
 237  *                                      - GPDMA_CONN_UART0_Tx           :USART 0 transmit\r
 238  *                                      - GPDMA_CONN_UART0_Rx           :USART 0 receive\r
 239  *                                      - GPDMA_CONN_UART1_Tx           :USART 1 transmit\r
 240  *                                      - GPDMA_CONN_UART1_Rx           :USART 1 receive\r
 241  *                                      - GPDMA_CONN_UART2_Tx           :USART 2 transmit\r
 242  *                                      - GPDMA_CONN_UART2_Rx           :USART 2 receive\r
 243  *                                      - GPDMA_CONN_UART3_Tx           :USART 3 transmit\r
 244  *                                      - GPDMA_CONN_UART3_Rx           :USART 3 receive\r
 245  *                                      - GPDMA_CONN_SCT_0                      :SCT output 0\r
 246  *                                      - GPDMA_CONN_SCT_1                      :SCT output 1\r
 247  *                                      - GPDMA_CONN_I2S_Channel_0      :I2S channel 0\r
 248  *                                      - GPDMA_CONN_I2S_Channel_1      :I2S channel 1\r
 249  *                                      - GPDMA_CONN_SSP0_Tx            :SSP0 transmit\r
 250  *                                      - GPDMA_CONN_SSP0_Rx            :SSP0 receive\r
 251  *                                      - GPDMA_CONN_SSP1_Tx            :SSP1 transmit\r
 252  *                                      - GPDMA_CONN_SSP1_Rx            :SSP1 receive\r
 253  *                                      - GPDMA_CONN_ADC_0                      :ADC0\r
 254  *                                      - GPDMA_CONN_ADC_1                      :ADC1\r
 255  *                                      - GPDMA_CONN_DAC                        :DAC\r
 256  * @return      channel number, could be in range: 0..16\r
 257  *********************************************************************/\r
 258 uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)\r
 259 {\r
 260         uint32_t *dmamux_reg = (uint32_t*)DMAMUX_ADDRESS;\r
 261         uint8_t function, channel;\r
 262 \r
 263         switch(gpdma_peripheral_connection_number)\r
 264         {\r
 265                 case GPDMA_CONN_SPIFI:          function = 0; channel = 0; break;\r
 266                 case GPDMA_CONN_MAT0_0:         function = 0; channel = 1; break;\r
 267                 case GPDMA_CONN_UART0_Tx:       function = 1; channel = 1; break;\r
 268                 case GPDMA_CONN_MAT0_1:         function = 0; channel = 2; break;\r
 269                 case GPDMA_CONN_UART0_Rx:       function = 1; channel = 2; break;\r
 270                 case GPDMA_CONN_MAT1_0:         function = 0; channel = 3; break;\r
 271                 case GPDMA_CONN_UART1_Tx:       function = 1; channel = 3; break;\r
 272                 case GPDMA_CONN_MAT1_1:         function = 0; channel = 4; break;\r
 273                 case GPDMA_CONN_UART1_Rx:       function = 1; channel = 4; break;\r
 274                 case GPDMA_CONN_MAT2_0:         function = 0; channel = 5; break;\r
 275                 case GPDMA_CONN_UART2_Tx:       function = 1; channel = 5; break;\r
 276                 case GPDMA_CONN_MAT2_1:         function = 0; channel = 6; break;\r
 277                 case GPDMA_CONN_UART2_Rx:       function = 1; channel = 6; break;\r
 278                 case GPDMA_CONN_MAT3_0:         function = 0; channel = 7; break;\r
 279                 case GPDMA_CONN_UART3_Tx:       function = 1; channel = 7; break;\r
 280                 case GPDMA_CONN_SCT_0:          function = 2; channel = 7; break;\r
 281                 case GPDMA_CONN_MAT3_1:         function = 0; channel = 8; break;\r
 282                 case GPDMA_CONN_UART3_Rx:       function = 1; channel = 8; break;\r
 283                 case GPDMA_CONN_SCT_1:          function = 2; channel = 8; break;\r
 284                 case GPDMA_CONN_SSP0_Rx:        function = 0; channel = 9; break;\r
 285                 case GPDMA_CONN_I2S_Channel_0:function = 1; channel = 9; break;\r
 286                 case GPDMA_CONN_SSP0_Tx:        function = 0; channel = 10; break;\r
 287                 case GPDMA_CONN_I2S_Channel_1:function = 1; channel = 10; break;\r
 288                 case GPDMA_CONN_SSP1_Rx:        function = 0; channel = 11; break;\r
 289                 case GPDMA_CONN_SSP1_Tx:        function = 0; channel = 12; break;\r
 290                 case GPDMA_CONN_ADC_0:          function = 0; channel = 13; break;\r
 291                 case GPDMA_CONN_ADC_1:          function = 0; channel = 14; break;\r
 292                 case GPDMA_CONN_DAC:            function = 0; channel = 15; break;\r
 293                 default:                                        function = 3; channel = 15; break;\r
 294         }\r
 295         //Set select function to dmamux register\r
 296         *dmamux_reg &= ~(0x03<<(2*channel));\r
 297         *dmamux_reg |= (function<<(2*channel));\r
 298 \r
 299         return channel;\r
 300 }\r
 301 /**\r
 302  * @}\r
 303  */\r
 304 \r
 305 /* Public Functions ----------------------------------------------------------- */\r
 306 /** @addtogroup GPDMA_Public_Functions\r
 307  * @{\r
 308  */\r
 309 \r
 310 /********************************************************************//**\r
 311  * @brief               Initialize GPDMA controller\r
 312  * @param[in]   None\r
 313  * @return              None\r
 314  *********************************************************************/\r
 315 void GPDMA_Init(void)\r
 316 {\r
 317         /* to be defined Enable GPDMA clock */\r
 318         // enabled default on reset\r
 319 \r
 320         // Reset all channel configuration register\r
 321         LPC_GPDMACH0->CConfig = 0;\r
 322         LPC_GPDMACH1->CConfig = 0;\r
 323         LPC_GPDMACH2->CConfig = 0;\r
 324         LPC_GPDMACH3->CConfig = 0;\r
 325         LPC_GPDMACH4->CConfig = 0;\r
 326         LPC_GPDMACH5->CConfig = 0;\r
 327         LPC_GPDMACH6->CConfig = 0;\r
 328         LPC_GPDMACH7->CConfig = 0;\r
 329 \r
 330         /* Clear all DMA interrupt and error flag */\r
 331         LPC_GPDMA->INTTCCLEAR = 0xFF;\r
 332         LPC_GPDMA->INTERRCLR = 0xFF;\r
 333 }\r
 334 \r
 335 /********************************************************************//**\r
 336  * @brief               Setup GPDMA channel peripheral according to the specified\r
 337  *              parameters in the GPDMAChannelConfig.\r
 338  * @param[in]   GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure\r
 339  *                              that contains the configuration information for the specified\r
 340  *                              GPDMA channel peripheral.\r
 341  * @return              Setup status, could be:\r
 342  *                                      - ERROR         :if selected channel is enabled before\r
 343  *                                      - SUCCESS       :if channel is configured successfully\r
 344  *********************************************************************/\r
 345 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)\r
 346 {\r
 347         LPC_GPDMACH_TypeDef *pDMAch;\r
 348         uint8_t SrcPeripheral=0, DestPeripheral=0;\r
 349 \r
 350         if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {\r
 351                 // This channel is enabled, return ERROR, need to release this channel first\r
 352                 return ERROR;\r
 353         }\r
 354 \r
 355         // Get Channel pointer\r
 356         pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];\r
 357 \r
 358         // Reset the Interrupt status\r
 359         LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);\r
 360         LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);\r
 361 \r
 362         // Clear DMA configure\r
 363         pDMAch->CControl = 0x00;\r
 364         pDMAch->CConfig = 0x00;\r
 365 \r
 366         /* Assign Linker List Item value */\r
 367         pDMAch->CLLI = GPDMAChannelConfig->DMALLI;\r
 368 \r
 369         /* Set value to Channel Control Registers */\r
 370         switch (GPDMAChannelConfig->TransferType)\r
 371         {\r
 372         // Memory to memory\r
 373         case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:\r
 374                 // Assign physical source and destination address\r
 375                 pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;\r
 376                 pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;\r
 377                 pDMAch->CControl\r
 378                                 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \\r
 379                                                 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \\r
 380                                                 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \\r
 381                                                 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \\r
 382                                                 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \\r
 383                                                 | GPDMA_DMACCxControl_SI \\r
 384                                                 | GPDMA_DMACCxControl_DI \\r
 385                                                 | GPDMA_DMACCxControl_I;\r
 386                 break;\r
 387         // Memory to peripheral\r
 388         case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:\r
 389                 // Assign physical source\r
 390                 pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;\r
 391                 // Assign peripheral destination address\r
 392                 pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];\r
 393                 pDMAch->CControl\r
 394                                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
 395                                                 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
 396                                                 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
 397                                                 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
 398                                                 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
 399                                                 | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \\r
 400                                                 | GPDMA_DMACCxControl_SI \\r
 401                                                 | GPDMA_DMACCxControl_I;\r
 402                 DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);\r
 403                 break;\r
 404         // Peripheral to memory\r
 405         case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:\r
 406                 // Assign peripheral source address\r
 407                 pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];\r
 408                 // Assign memory destination address\r
 409                 pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;\r
 410                 pDMAch->CControl\r
 411                                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
 412                                                 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
 413                                                 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
 414                                                 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
 415                                                 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
 416                                                 | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \\r
 417                                                 | GPDMA_DMACCxControl_DI \\r
 418                                                 | GPDMA_DMACCxControl_I;\r
 419                 SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);\r
 420                 break;\r
 421         // Peripheral to peripheral\r
 422         case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:\r
 423                 // Assign peripheral source address\r
 424                 pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];\r
 425                 // Assign peripheral destination address\r
 426                 pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];\r
 427                 pDMAch->CControl\r
 428                                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
 429                                                 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
 430                                                 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
 431                                                 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
 432                                                 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
 433                                                 | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \\r
 434                                                 | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \\r
 435                                                 | GPDMA_DMACCxControl_I;\r
 436                 SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);\r
 437                 DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);\r
 438                 break;\r
 439 \r
 440         case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:\r
 441         case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:\r
 442         case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:\r
 443         case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:\r
 444                 //to be defined\r
 445         // Do not support any more transfer type, return ERROR\r
 446         default:\r
 447                 return ERROR;\r
 448         }\r
 449 \r
 450         /* Enable DMA channels, little endian */\r
 451         LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;\r
 452         while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));\r
 453 \r
 454         // Configure DMA Channel, enable Error Counter and Terminate counter\r
 455         pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \\r
 456                 | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \\r
 457                 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \\r
 458                 | GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);\r
 459 \r
 460         return SUCCESS;\r
 461 }\r
 462 \r
 463 \r
 464 /*********************************************************************//**\r
 465  * @brief               Enable/Disable DMA channel\r
 466  * @param[in]   channelNum      GPDMA channel, should be in range from 0 to 15\r
 467  * @param[in]   NewState        New State of this command, should be:\r
 468  *                                      - ENABLE.\r
 469  *                                      - DISABLE.\r
 470  * @return              None\r
 471  **********************************************************************/\r
 472 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)\r
 473 {\r
 474         LPC_GPDMACH_TypeDef *pDMAch;\r
 475 \r
 476         // Get Channel pointer\r
 477         pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];\r
 478 \r
 479         if (NewState == ENABLE) {\r
 480                 pDMAch->CConfig |= GPDMA_DMACCxConfig_E;\r
 481         } else {\r
 482                 pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;\r
 483         }\r
 484 }\r
 485 \r
 486 \r
 487 /*********************************************************************//**\r
 488  * @brief               Check if corresponding channel does have an active interrupt\r
 489  *                              request or not\r
 490  * @param[in]   type            type of status, should be:\r
 491  *                                      - GPDMA_STAT_INT                :GPDMA Interrupt Status\r
 492  *                                      - GPDMA_STAT_INTTC              :GPDMA Interrupt Terminal Count Request Status\r
 493  *                                      - GPDMA_STAT_INTERR             :GPDMA Interrupt Error Status\r
 494  *                                      - GPDMA_STAT_RAWINTTC   :GPDMA Raw Interrupt Terminal Count Status\r
 495  *                                      - GPDMA_STAT_RAWINTERR  :GPDMA Raw Error Interrupt Status\r
 496  *                                      - GPDMA_STAT_ENABLED_CH :GPDMA Enabled Channel Status\r
 497  * @param[in]   channel         GPDMA channel, should be in range from 0 to 7\r
 498  * @return              IntStatus       status of DMA channel interrupt after masking\r
 499  *                              Should be:\r
 500  *                                      - SET   :the corresponding channel has no active interrupt request\r
 501  *                                      - RESET :the corresponding channel does have an active interrupt request\r
 502  **********************************************************************/\r
 503 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)\r
 504 {\r
 505         CHECK_PARAM(PARAM_GPDMA_STAT(type));\r
 506         CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));\r
 507 \r
 508         switch (type)\r
 509         {\r
 510         case GPDMA_STAT_INT: //check status of DMA channel interrupts\r
 511                 if (LPC_GPDMA->INTSTAT & (GPDMA_DMACIntStat_Ch(channel)))\r
 512                         return SET;\r
 513                 return RESET;\r
 514         case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA\r
 515                 if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(channel))\r
 516                         return SET;\r
 517                 return RESET;\r
 518         case GPDMA_STAT_INTERR: //check interrupt status for DMA channels\r
 519                 if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntTCClear_Ch(channel))\r
 520                         return SET;\r
 521                 return RESET;\r
 522         case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels\r
 523                 if (LPC_GPDMA->RAWINTERRSTAT & GPDMA_DMACRawIntTCStat_Ch(channel))\r
 524                         return SET;\r
 525                 return RESET;\r
 526         case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels\r
 527                 if (LPC_GPDMA->RAWINTTCSTAT & GPDMA_DMACRawIntErrStat_Ch(channel))\r
 528                         return SET;\r
 529                 return RESET;\r
 530         default: //check enable status for DMA channels\r
 531                 if (LPC_GPDMA->ENBLDCHNS & GPDMA_DMACEnbldChns_Ch(channel))\r
 532                         return SET;\r
 533                 return RESET;\r
 534         }\r
 535 }\r
 536 \r
 537 /*********************************************************************//**\r
 538  * @brief               Clear one or more interrupt requests on DMA channels\r
 539  * @param[in]   type            type of interrupt request, should be:\r
 540  *                                      - GPDMA_STATCLR_INTTC   :GPDMA Interrupt Terminal Count Request Clear\r
 541  *                                      - GPDMA_STATCLR_INTERR  :GPDMA Interrupt Error Clear\r
 542  * @param[in]   channel         GPDMA channel, should be in range from 0 to 15\r
 543  * @return              None\r
 544  **********************************************************************/\r
 545 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)\r
 546 {\r
 547         CHECK_PARAM(PARAM_GPDMA_STATCLR(type));\r
 548         CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));\r
 549 \r
 550         if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel\r
 551                 LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(channel);\r
 552         else // clear the error interrupt request\r
 553                 LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(channel);\r
 554 }\r
 555 \r
 556 /**\r
 557  * @}\r
 558  */\r
 559 \r
 560 #endif /* _GPDMA */\r
 561 \r
 562 /**\r
 563  * @}\r
 564  */\r
 565 \r
 566 /* --------------------------------- End Of File ------------------------------ */\r
 567 \r