3 * Copyright (C) 2006-2013 wolfSSL Inc.
5 * This file is part of CyaSSL.
7 * CyaSSL is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * CyaSSL is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
28 #define PERIPH_BASE ((uint32_t)0x40000000)
29 /*-----------------------------------------------------------------------------
31 *----------------------------------------------------------------------------*/
32 #include "stm32f2xx.h"
34 #define assert_param(a)
37 #define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
38 #define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
39 #define Bcd2ToByte(v) \
40 ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F))
41 #define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
42 #define RTC_TR_MNT ((uint32_t)0x00007000)
43 #define RTC_TR_MNU ((uint32_t)0x00000F00)
45 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
46 #define CR_OFFSET (PWR_OFFSET + 0x00)
47 #define DBP_BitNumber 0x08
48 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
49 #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
50 #define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
53 /*-----------------------------------------------------------------------------
55 *----------------------------------------------------------------------------*/
56 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
62 ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ;
65 tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) ));
66 /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */
67 tmpcr1 |= (uint16_t)0x0000 ; /* CR1 |= TIM_CounterMode_Up */
70 TIM2->ARR = 0xffffffff ; /* ARR= TIM_Period */
71 TIM2->PSC = 60 ; /* PSC = TIM_Prescaler */
72 TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */
74 *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ;
75 /* TIM_Cmd(TIM2, ENABLE) ; */
80 return ((double)TIM2->CNT/1000000.0) ;