4 * \brief KSZ8051MNL (Ethernet PHY) driver for SAM.
6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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44 #ifndef ETHERNET_PHY_H_INCLUDED
45 #define ETHERNET_PHY_H_INCLUDED
53 // IEEE defined Registers
54 #define GMII_BMCR 0x00 // Basic Control
55 #define GMII_BMSR 0x01 // Basic Status
56 #define GMII_PHYID1 0x02 // PHY Idendifier 1
57 #define GMII_PHYID2 0x03 // PHY Idendifier 2
58 #define GMII_ANAR 0x04 // Auto_Negotiation Advertisement
59 #define GMII_ANLPAR 0x05 // Auto_negotiation Link Partner Ability
60 #define GMII_ANER 0x06 // Auto-negotiation Expansion
61 #define GMII_ANNPR 0x07 // Auto-negotiation Next Page
62 #define GMII_ANLPNPAR 0x08 // Link Partner Next Page Ability
63 //#define GMII_1000BTCR 9 // 1000Base-T Control // Reserved
64 //#define GMII_1000BTSR 10 // 1000Base-T Status // Reserved
65 #define GMII_AFECR1 0x11 // AFE Control 1
66 //#define GMII_ERDWR 12 // Extend Register - Data Write Register
67 //#define GMII_ERDRR 13 // Extend Register - Data Read Register
69 #define GMII_RXERCR 0x15 // RXER Counter
71 #define PHY_REG_01_BMSR 0x01 // Basic mode status register
72 #define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1
73 #define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2
74 #define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg
75 #define PHY_REG_05_LPA 0x05 // Link partner ability reg
76 #define PHY_REG_06_ANER 0x06 // 6 RW Auto-Negotiation Expansion Register
77 #define PHY_REG_07_ANNPTR 0x07 // 7 RW Auto-Negotiation Next Page TX
78 #define PHY_REG_08_RESERVED0 0x08 // 0x08..0x0Fh 8-15 RW RESERVED
80 #define PHY_REG_10_PHYSTS 0x10 // 16 RO PHY Status Register
81 #define PHY_REG_11_MICR 0x11 // 17 RW MII Interrupt Control Register
82 #define PHY_REG_12_MISR 0x12 // 18 RO MII Interrupt Status Register
83 #define PHY_REG_13_RESERVED1 0x13 // 19 RW RESERVED
84 #define PHY_REG_14_FCSCR 0x14 // 20 RO False Carrier Sense Counter Register
85 #define PHY_REG_15_RECR 0x15 // 21 RO Receive Error Counter Register
86 #define PHY_REG_16_PCSR 0x16 // 22 RW PCS Sub-Layer Configuration and Status Register
87 #define PHY_REG_17_RBR 0x17 // 23 RW RMII and Bypass Register
88 #define PHY_REG_18_LEDCR 0x18 // 24 RW LED Direct Control Register
89 #define PHY_REG_19_PHYCR 0x19 // 25 RW PHY Control Register
90 #define PHY_REG_1A_10BTSCR 0x1A // 26 RW 10Base-T Status/Control Register
91 #define PHY_REG_1B_CDCTRL1 0x1B // 27 RW CD Test Control Register and BIST Extensions Register
92 #define PHY_REG_1B_INT_CTRL 0x1B // 27 RW KSZ8041NL interrupt control
93 #define PHY_REG_1C_RESERVED2 0x1C // 28 RW RESERVED
94 #define PHY_REG_1D_EDCR 0x1D // 29 RW Energy Detect Control Register
95 #define PHY_REG_1E_RESERVED3 0x1E //
96 #define PHY_REG_1F_RESERVED4 0x1F // 30-31 RW RESERVED
98 #define PHY_REG_1E_PHYCR_1 0x1E //
99 #define PHY_REG_1F_PHYCR_2 0x1F //
101 #define PHY_SPEED_10 1
102 #define PHY_SPEED_100 2
103 #define PHY_SPEED_AUTO (PHY_SPEED_10|PHY_SPEED_100)
105 #define PHY_MDIX_DIRECT 1
106 #define PHY_MDIX_CROSSED 2
107 #define PHY_MDIX_AUTO (PHY_MDIX_CROSSED|PHY_MDIX_DIRECT)
109 #define PHY_DUPLEX_HALF 1
110 #define PHY_DUPLEX_FULL 2
111 #define PHY_DUPLEX_AUTO (PHY_DUPLEX_FULL|PHY_DUPLEX_HALF)
113 typedef struct _SPhyProps {
116 unsigned char duplex;
120 const char *phyPrintable (const SPhyProps *apProps);
122 extern SPhyProps phyProps;
124 #define GMII_OMSOR 0x16 // Operation Mode Strap Override
125 #define GMII_OMSSR 0x17 // Operation Mode Strap Status
126 #define GMII_ECR 0x18 // Expanded Control
127 //#define GMII_DPPSR 19 // Digital PMA/PCS Status
129 //#define GMII_RXERCR 21 // RXER Counter Register
131 #define GMII_ICSR 0x1B // Interrupt Control/Status
132 //#define GMII_DDC1R 28 // Digital Debug Control 1 Register
133 #define GMII_LCSR 0x1D // LinkMD Control/Status
136 #define GMII_PCR1 0x1E // PHY Control 1
137 #define GMII_PCR2 0x1F // PHY Control 2
141 #define GMII_CCR 256 // Common Control Register
142 #define GMII_SSR 257 // Strap Status Register
143 #define GMII_OMSOR 258 // Operation Mode Strap Override Register
144 #define GMII_OMSSR 259 // Operation Mode Strap Status Register
145 #define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register
146 #define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register
147 #define GMII_ATR 263 // Analog Test Register
151 // Bit definitions: GMII_BMCR 0x00 Basic Control
152 #define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
153 #define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
154 #define GMII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
155 #define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
156 #define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
157 #define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
158 #define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
159 #define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
160 #define GMII_COLLISION_TEST (1 << 7) // 1 = Enable COL test; 0 = Disable COL test
161 //#define GMII_SPEED_SELECT_MSB (1 << 6) // Reserved
162 // Reserved 6 to 0 // Read as 0, ignore on write
164 // Bit definitions: GMII_BMSR 0x01 Basic Status
165 #define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
166 #define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
167 #define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
168 #define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
169 #define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
170 // Reserved 10 to79 // Read as 0, ignore on write
171 //#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
173 #define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
174 #define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
175 #define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
176 #define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
177 #define GMII_LINK_STATUS (1 << 2) // Link Status
178 #define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
179 #define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
182 // Bit definitions: GMII_PHYID1 0x02 PHY Idendifier 1
183 // Bit definitions: GMII_PHYID2 0x03 PHY Idendifier 2
184 #define GMII_LSB_MASK 0x3F
185 #define GMII_OUI_MSB 0x0022
186 #define GMII_OUI_LSB 0x05
189 // Bit definitions: GMII_ANAR 0x04 Auto_Negotiation Advertisement
190 // Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability
191 #define GMII_NP (1 << 15) // Next page Indication
193 #define GMII_RF (1 << 13) // Remote Fault
194 // Reserved 12 // Write as 0, ignore on read
195 #define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
196 // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
197 #define GMII_100T4 (1 << 9) // 100BASE-T4 Support
198 #define GMII_100TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
199 #define GMII_100TX_HDX (1 << 7) // 100BASE-TX Support
200 #define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
201 #define GMII_10_HDX (1 << 5) // 10BASE-T Support
202 // Selector 4 to 0 // Protocol Selection Bits
203 #define GMII_AN_IEEE_802_3 0x0001 // [00001] = IEEE 802.3
206 // Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion
207 // Reserved 15 to 5 // Read as 0, ignore on write
208 #define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault
209 #define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able
210 #define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able
211 #define GMII_PAGE_RX (1 << 1) // New Page Received
212 #define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able
215 * \brief Perform a HW initialization to the PHY and set up clocks.
217 * This should be called only once to initialize the PHY pre-settings.
218 * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups).
219 * The COL pin is used to select MII mode on reset (pulled up for Reduced MII).
220 * The RXDV pin is used to select test mode on reset (pulled up for test mode).
221 * The above pins should be predefined for corresponding settings in resetPins.
222 * The GMAC peripheral pins are configured after the reset is done.
224 * \param p_gmac Pointer to the GMAC instance.
225 * \param uc_phy_addr PHY address.
226 * \param ul_mck GMAC MCK.
228 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
230 uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t ul_mck);
234 * \brief Get the Link & speed settings, and automatically set up the GMAC with the
237 * \param p_gmac Pointer to the GMAC instance.
238 * \param uc_phy_addr PHY address.
239 * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.
241 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
243 uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr,
244 uint8_t uc_apply_setting_flag);
248 * \brief Issue an auto negotiation of the PHY.
250 * \param p_gmac Pointer to the GMAC instance.
251 * \param uc_phy_addr PHY address.
253 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
255 uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr);
258 * \brief Issue a SW reset to reset all registers of the PHY.
260 * \param p_gmac Pointer to the GMAC instance.
261 * \param uc_phy_addr PHY address.
263 * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
265 uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr);
267 typedef struct xPHY_PROPS {
268 signed char phy_result;
272 unsigned char phy_chn;
274 extern PhyProps_t phy_props;
280 #endif /* #ifndef ETHERNET_PHY_H_INCLUDED */