4 * \brief KSZ8051MNL (Ethernet PHY) driver for SAM.
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef ETHERNET_PHY_H_INCLUDED
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45 #define ETHERNET_PHY_H_INCLUDED
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47 #include "compiler.h"
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53 // IEEE defined Registers
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54 #define GMII_BMCR 0x00 // Basic Control
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55 #define GMII_BMSR 0x01 // Basic Status
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56 #define GMII_PHYID1 0x02 // PHY Idendifier 1
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57 #define GMII_PHYID2 0x03 // PHY Idendifier 2
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58 #define GMII_ANAR 0x04 // Auto_Negotiation Advertisement
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59 #define GMII_ANLPAR 0x05 // Auto_negotiation Link Partner Ability
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60 #define GMII_ANER 0x06 // Auto-negotiation Expansion
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61 #define GMII_ANNPR 0x07 // Auto-negotiation Next Page
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62 #define GMII_ANLPNPAR 0x08 // Link Partner Next Page Ability
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63 //#define GMII_1000BTCR 9 // 1000Base-T Control // Reserved
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64 //#define GMII_1000BTSR 10 // 1000Base-T Status // Reserved
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65 #define GMII_AFECR1 0x11 // AFE Control 1
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66 //#define GMII_ERDWR 12 // Extend Register - Data Write Register
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67 //#define GMII_ERDRR 13 // Extend Register - Data Read Register
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69 #define GMII_RXERCR 0x15 // RXER Counter
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71 #define PHY_REG_01_BMSR 0x01 // Basic mode status register
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72 #define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1
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73 #define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2
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74 #define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg
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75 #define PHY_REG_05_LPA 0x05 // Link partner ability reg
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76 #define PHY_REG_06_ANER 0x06 // 6 RW Auto-Negotiation Expansion Register
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77 #define PHY_REG_07_ANNPTR 0x07 // 7 RW Auto-Negotiation Next Page TX
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78 #define PHY_REG_08_RESERVED0 0x08 // 0x08..0x0Fh 8-15 RW RESERVED
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80 #define PHY_REG_10_PHYSTS 0x10 // 16 RO PHY Status Register
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81 #define PHY_REG_11_MICR 0x11 // 17 RW MII Interrupt Control Register
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82 #define PHY_REG_12_MISR 0x12 // 18 RO MII Interrupt Status Register
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83 #define PHY_REG_13_RESERVED1 0x13 // 19 RW RESERVED
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84 #define PHY_REG_14_FCSCR 0x14 // 20 RO False Carrier Sense Counter Register
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85 #define PHY_REG_15_RECR 0x15 // 21 RO Receive Error Counter Register
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86 #define PHY_REG_16_PCSR 0x16 // 22 RW PCS Sub-Layer Configuration and Status Register
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87 #define PHY_REG_17_RBR 0x17 // 23 RW RMII and Bypass Register
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88 #define PHY_REG_18_LEDCR 0x18 // 24 RW LED Direct Control Register
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89 #define PHY_REG_19_PHYCR 0x19 // 25 RW PHY Control Register
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90 #define PHY_REG_1A_10BTSCR 0x1A // 26 RW 10Base-T Status/Control Register
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91 #define PHY_REG_1B_CDCTRL1 0x1B // 27 RW CD Test Control Register and BIST Extensions Register
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92 #define PHY_REG_1B_INT_CTRL 0x1B // 27 RW KSZ8041NL interrupt control
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93 #define PHY_REG_1C_RESERVED2 0x1C // 28 RW RESERVED
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94 #define PHY_REG_1D_EDCR 0x1D // 29 RW Energy Detect Control Register
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95 #define PHY_REG_1E_RESERVED3 0x1E //
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96 #define PHY_REG_1F_RESERVED4 0x1F // 30-31 RW RESERVED
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98 #define PHY_REG_1E_PHYCR_1 0x1E //
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99 #define PHY_REG_1F_PHYCR_2 0x1F //
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101 #define PHY_SPEED_10 1
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102 #define PHY_SPEED_100 2
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103 #define PHY_SPEED_AUTO (PHY_SPEED_10|PHY_SPEED_100)
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105 #define PHY_MDIX_DIRECT 1
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106 #define PHY_MDIX_CROSSED 2
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107 #define PHY_MDIX_AUTO (PHY_MDIX_CROSSED|PHY_MDIX_DIRECT)
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109 #define PHY_DUPLEX_HALF 1
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110 #define PHY_DUPLEX_FULL 2
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111 #define PHY_DUPLEX_AUTO (PHY_DUPLEX_FULL|PHY_DUPLEX_HALF)
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113 typedef struct _SPhyProps {
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114 unsigned char speed;
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115 unsigned char mdix;
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116 unsigned char duplex;
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117 unsigned char spare;
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120 const char *phyPrintable (const SPhyProps *apProps);
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122 extern SPhyProps phyProps;
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124 #define GMII_OMSOR 0x16 // Operation Mode Strap Override
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125 #define GMII_OMSSR 0x17 // Operation Mode Strap Status
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126 #define GMII_ECR 0x18 // Expanded Control
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127 //#define GMII_DPPSR 19 // Digital PMA/PCS Status
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129 //#define GMII_RXERCR 21 // RXER Counter Register
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131 #define GMII_ICSR 0x1B // Interrupt Control/Status
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132 //#define GMII_DDC1R 28 // Digital Debug Control 1 Register
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133 #define GMII_LCSR 0x1D // LinkMD Control/Status
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136 #define GMII_PCR1 0x1E // PHY Control 1
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137 #define GMII_PCR2 0x1F // PHY Control 2
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141 #define GMII_CCR 256 // Common Control Register
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142 #define GMII_SSR 257 // Strap Status Register
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143 #define GMII_OMSOR 258 // Operation Mode Strap Override Register
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144 #define GMII_OMSSR 259 // Operation Mode Strap Status Register
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145 #define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register
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146 #define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register
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147 #define GMII_ATR 263 // Analog Test Register
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151 // Bit definitions: GMII_BMCR 0x00 Basic Control
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152 #define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
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153 #define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
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154 #define GMII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
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155 #define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
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156 #define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
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157 #define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
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158 #define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
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159 #define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
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160 #define GMII_COLLISION_TEST (1 << 7) // 1 = Enable COL test; 0 = Disable COL test
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161 //#define GMII_SPEED_SELECT_MSB (1 << 6) // Reserved
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162 // Reserved 6 to 0 // Read as 0, ignore on write
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164 // Bit definitions: GMII_BMSR 0x01 Basic Status
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165 #define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
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166 #define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
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167 #define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
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168 #define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
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169 #define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
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170 // Reserved 10 to79 // Read as 0, ignore on write
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171 //#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
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173 #define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
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174 #define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
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175 #define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
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176 #define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
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177 #define GMII_LINK_STATUS (1 << 2) // Link Status
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178 #define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
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179 #define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
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182 // Bit definitions: GMII_PHYID1 0x02 PHY Idendifier 1
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183 // Bit definitions: GMII_PHYID2 0x03 PHY Idendifier 2
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184 #define GMII_LSB_MASK 0x3F
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185 #define GMII_OUI_MSB 0x0022
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186 #define GMII_OUI_LSB 0x05
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189 // Bit definitions: GMII_ANAR 0x04 Auto_Negotiation Advertisement
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190 // Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability
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191 #define GMII_NP (1 << 15) // Next page Indication
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193 #define GMII_RF (1 << 13) // Remote Fault
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194 // Reserved 12 // Write as 0, ignore on read
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195 #define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
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196 // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
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197 #define GMII_100T4 (1 << 9) // 100BASE-T4 Support
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198 #define GMII_100TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
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199 #define GMII_100TX_HDX (1 << 7) // 100BASE-TX Support
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200 #define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
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201 #define GMII_10_HDX (1 << 5) // 10BASE-T Support
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202 // Selector 4 to 0 // Protocol Selection Bits
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203 #define GMII_AN_IEEE_802_3 0x0001 // [00001] = IEEE 802.3
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206 // Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion
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207 // Reserved 15 to 5 // Read as 0, ignore on write
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208 #define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault
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209 #define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able
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210 #define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able
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211 #define GMII_PAGE_RX (1 << 1) // New Page Received
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212 #define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able
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215 * \brief Perform a HW initialization to the PHY and set up clocks.
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217 * This should be called only once to initialize the PHY pre-settings.
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218 * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups).
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219 * The COL pin is used to select MII mode on reset (pulled up for Reduced MII).
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220 * The RXDV pin is used to select test mode on reset (pulled up for test mode).
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221 * The above pins should be predefined for corresponding settings in resetPins.
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222 * The GMAC peripheral pins are configured after the reset is done.
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224 * \param p_gmac Pointer to the GMAC instance.
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225 * \param uc_phy_addr PHY address.
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226 * \param ul_mck GMAC MCK.
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228 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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230 uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t ul_mck);
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234 * \brief Get the Link & speed settings, and automatically set up the GMAC with the
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237 * \param p_gmac Pointer to the GMAC instance.
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238 * \param uc_phy_addr PHY address.
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239 * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.
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241 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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243 uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr,
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244 uint8_t uc_apply_setting_flag);
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248 * \brief Issue an auto negotiation of the PHY.
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250 * \param p_gmac Pointer to the GMAC instance.
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251 * \param uc_phy_addr PHY address.
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253 * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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255 uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr);
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258 * \brief Issue a SW reset to reset all registers of the PHY.
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260 * \param p_gmac Pointer to the GMAC instance.
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261 * \param uc_phy_addr PHY address.
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263 * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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265 uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr);
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267 typedef struct xPHY_PROPS {
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268 signed char phy_result;
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269 uint32_t phy_params;
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270 uint32_t phy_stat1;
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271 uint32_t phy_stat2;
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272 unsigned char phy_chn;
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274 extern PhyProps_t phy_props;
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280 #endif /* #ifndef ETHERNET_PHY_H_INCLUDED */
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